EP0253886A1 - Interconnects for wafer-scale-integrated assembly - Google Patents
Interconnects for wafer-scale-integrated assemblyInfo
- Publication number
- EP0253886A1 EP0253886A1 EP87902022A EP87902022A EP0253886A1 EP 0253886 A1 EP0253886 A1 EP 0253886A1 EP 87902022 A EP87902022 A EP 87902022A EP 87902022 A EP87902022 A EP 87902022A EP 0253886 A1 EP0253886 A1 EP 0253886A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- assembly
- wafers
- wafer
- emitting
- optical signals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 235000012431 wafers Nutrition 0.000 claims abstract description 81
- 230000003287 optical effect Effects 0.000 claims abstract description 28
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 17
- 239000010703 silicon Substances 0.000 claims abstract description 17
- 230000000644 propagated effect Effects 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 6
- 238000010521 absorption reaction Methods 0.000 claims description 3
- 230000003667 anti-reflective effect Effects 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 16
- 230000000712 assembly Effects 0.000 description 7
- 238000000429 assembly Methods 0.000 description 7
- 239000004020 conductor Substances 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 230000001902 propagating effect Effects 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 238000013459 approach Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000002146 bilateral effect Effects 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000002939 deleterious effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000013011 mating Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 239000012780 transparent material Substances 0.000 description 1
- NWONKYPBYAMBJT-UHFFFAOYSA-L zinc sulfate Chemical compound [Zn+2].[O-]S([O-])(=O)=O NWONKYPBYAMBJT-UHFFFAOYSA-L 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/12—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto
- H01L31/16—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto the semiconductor device sensitive to radiation being controlled by the light source or sources
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/42—Coupling light guides with opto-electronic elements
- G02B6/43—Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/12—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto
- H01L31/16—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto the semiconductor device sensitive to radiation being controlled by the light source or sources
- H01L31/167—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto the semiconductor device sensitive to radiation being controlled by the light source or sources the light sources and the devices sensitive to radiation all being semiconductor devices characterised by potential barriers
Definitions
- This invention relates to integrated-circuit chips and, more particularly, to an assembly that comprises a stack of wafers each of which includes multiple interconnected chips.
- the integrated-circuit art it is known to utilize a pattern of lithographically formed conductors on a semicon uctor wafer to interconnect a number of semiconductor chips and to connect the chips to input/output pads on the wafer.
- the chips to be interconnected are mounted on the surface of the wafer or in recesses formed in the wafer surface.
- the chips are fabricated in the wafer as integral parts thereof.
- wafer-scale-integrated (WSI) assemblies wafer-scale-integrated
- WSI assemblies are potentially faster than approaches based on individually packaged chips mounted and interconnected on a standard pr inted-circuit board.
- the size of the chip package limits the density of circuits in a system.
- circuits can be packed extremely close together on a single wafer, thus avoiding the major size limitations imposed by package size and thereby enabling faster performance due to substantial decreases in chip interconnection lengths.
- the desire to achieve a high degree of parallelism in WSI architectures has led to the development of three-dimensional assemblies comprising stacks of wafers of the type described above. In such a stacked-wafer assembly, multiple vertical connections are provided between wafers.
- WSI assembly Multiple wafers each including integrated- circuit chips are stacked to form a WSI assembly.
- Connections are established between wafers in the assembly by sending optical signals from the surface of one wafer to the surface of another. In accordance with the invention, these signals are transmitted directly through the material of one or more wafers in the 5 assembly.
- FIG. 1 i s a s impl ified schematic representation of a portion of a WSI assembl y compr is ing a chip-conta ining wafer and an assoc iated pl anar i zing 0 " member wh ich embody features o f the present invention ;
- F IG . 2 shows two o f the FIG . 1 arrangements together wi th a cover pl ate ;
- FIG . 3 represents the FIG . 2 components combined to form a stacked-wafer assembly; 5 and FIG. 4 ill ustrates in cross- section a portion of a spec i f ic il lustrative WSI assembly made in accordance with the pr inc iples o f the present invention .
- each board illustrated is a modified version of a known board in which multiple integrated-circuit chips are attached by face-down solder bonding to microminiature interconnections formed on the surface of a silicon wafer.
- Such known boards are described, for example, in "Wafer-Chip Assembly for Large-Scale
- additional chips comprising optical emitters and detectors are also attached to the interconnections on the silicon wafers.
- connections between boards are made by transmitting optical signals through the silicon material of the wafers between respective emitters and detectors.
- the board (FIG. 1) comprises a silicon wafer 10 having multiple chips solder bonded thereto. Only six of these chips, respectively designated by reference numerals 12 through 16, are shown in FIG. 1. Some of these chips comprise very-large-scale-integrated (VLSI) chips and others comprise optical emitters and/or detectors.
- VLSI very-large-scale-integrated
- FIG. 1 also indicates, by dashed lines 18, that the chips 12 through 16 are interconnected.
- the interconnections 18 comprise lithographically formed power and ground conductors and X- and Y-signal conductors respectively disposed in spa ⁇ ed-apart levels overlying the upper surface of the wafer 10.
- the signal conductors comprise aluminum or copper lines each about 2 micrometers (ym) thick and approximately 10 ⁇ wide. In some cases, it is advantageous to form the ground plane on the lower surface of the wafer 10. Such a particular illustrative case will be specified below in connection with the description of FIG. 4.
- the resulting single-wafer assembly has a nonplanar top exhibiting multiple protuberances.
- planarizing member 20 of the type shown in FIG. 1.
- the member 20 of FIG. 1 also comprises a silicon wafer.
- the member 20 includes openings therethrough in exact registry with and slightly larger in size than the respective chips 12 through 16 on the wafer 10.
- the thickness of the wafer 20 is slightly greater than the extent by which the most protruding one of the chips 12 through 16 extends above the surface of the assembly. In that way, when the assembly and the member 20 are brought together into intimate contact, a planar surface devoid of protuberances (but with openings therein) is achieved.
- the planarizing member 20 of FIG. 1 includes only recesses in the bottom surface thereof. These recesses are formed in respective registry with the chips 12 through 16 and are appropriately sized to accommodate the full height of . the chips. In that case, a truly planar top surface is realized when the member 20 and the wafer 10 are combined to form a composite WSI assembly.
- Various techniques are available for aligning the member 20 (FIG. 1) with respect to its associated chip-carrying wafer 10. One way of doing this is to include projections 22 through 24 on the wafer 10. These are designed to mate with corresponding openings (not shown in FIG. 1) formed in the bottom side of the member 20.
- FIG. 2 shows two composite WSI assemblies, each of the type represented in FIG. 1, designed to be stacked together.
- One assembly comprises planarizing member 26 and chip-carrying wafer 28.
- the wafer 28 includes seven chips mounted thereon in alignment with respective openings ir. the member 26.
- the other assembly which, for example, includes five chips, comprises planarizing member 30 and chip-carrying wafer 32.
- projections 34 through 36 are included on the top surface of the member 30. These are intended to mate with correspon ing openings (not shown) formed in the bottom of the wafer 28.
- a protective cover plate may be added.
- Such a cover comprising a silicon wafer 38 is shown in FIG. 2.
- FIG. 3 An assembled stack of wafers is depicted in FIG. 3. This particular illustrative stack includes the constituent elements described above and shown in FIG. 2.
- FIG. 4 represents a portion of an illustrative WSI assembly made in accordance with the invention.
- the depicted assembly comprises a silicon planarizing member 40 sandwiched between two chip-carrying silicon wafers 42 and 44.
- each of the wafers 42 and 44 of FIG. 4 is shown as having two optical components mounted thereon.
- the wafer 42 includes optical- signal emitter 46 and optical-signal detector 48
- the wafer 44 includes optical-signal emitter 50 and optical-signal detector 52.
- each wafer in the WSI assembly may include a multitude of optical emitters and detectors.
- the emitters 46 and 50 comprise lasers or light-emitting diodes designed to provide optical output signals at a wavelength in the range of about 1.1-to- 10 ⁇ m.
- silicon even if highly doped to render it conductive
- signals propagated downward by the emitter 46 toward the detector 52 will be transmitted through the silicon wafer 42 and the silicon member 40 in a relatively low-absorption way.
- signals from the emitter 50 will be propagated upward through the member 40 and the wafer 42 in a low-absorption manner to impinge upon the detector 48.
- the emitters 46 and 50 of FIG. 4 may each comprise a laser unit designed to emit at 1.3 or 1.55 ⁇ m.
- a unit may comprise, for example, an edge-emitting laser combined with a parabolic mirror in microminiature chip form.
- the optical emitters 46 and 50 and the optical detectors 48 and 52 of FIG. 4 comprise standard discrete elements or monolithic arrays that are fabricated and tested as individual components and then mounted in place and interconnected (for example by face-down solder bonding) to associated circuitry on their respective wafers.
- the emitters or detectors may be fabricated in place in the wafers 42 and 44 as integral parts thereof.
- silicon photodetectors can be made in that manner directly in the silicon wafers.
- optical emitters and detectors can then also be made in place as integral parts of the wafers.
- Each of the wafers 42 and 44 also typically includes multiple VLSI chips.
- these integrated-circuit chips are indicated by elements 54 and 56 which are representative of discrete individual chips that have been bonded and interconnected on their respective wafers.
- all the integrated circuitry, except for interconnects, included on the wafers 42 and 44 of FIG. 4 are embodied in the form of discrete individual chips mounted thereon.
- some or all "of the integrated circuitry is formed in surface portions of the wafers as integral parts thereof.
- FIG. 4 exemplifies both approaches.
- FIG. 4 schematically shows integrated-circuit portions 58 and 60 formed within the wafers 42 and 44, respectively. These portions constitute, for example, bipolar or metal-oxide- semiconductor driver circuitry respectively associated with and connected to the optical emitters 46 and 50.
- Surface regions 62 and 64 (FIG. 4) on the wafers 42 and 44 respectively represent multi-layer interconnection circuitry of the depicted WSI assembly. Thus, these regions include interleaved layers of insulating and conducting materials such as polyimide and aluminum or copper, as is well known in the art.
- the regions 62 and 64 or some parts thereof may include additional layers of materials such as silicon dioxide and/or silicon nitride.
- wafers 42 and 44 of FIG. 4 include ground planes 66 and 68 on the bottom surfaces thereof. These planes on the wafers 42 and 44 comprise, for example, 2- ⁇ m-thick layers of a conductive material such as aluminum or copper. To effect electrical connections between these ground planes and conductors in the surface regions 62 and 64, it is necessary that the wafers 42 and 44 or at least portions thereof be highly doped to render them conductive.
- the ground plane 66 is patterned to provide openings through which optical signals are propagated between the wafers 42 and 44 in the depicted WSI assembly. Such patterning typically enhances transmission by minimizing signal reflections and providing signal containment.
- any highly absorptive or reflective layers in the surface region 62 underlying the components 46 and 48 are advantageously removed.
- the region 62 includes layers of materials such as silicon dioxide and/or silicon nitride underlying the components 46 and 48, it is generally advantageous where possible to control the thicknesses of these layers to render them substantially antireflective.
- the illustrative planarizing member 40 shown in FIG. 4 includes recesses 70 through 72 formed in the bottom surface thereof. These recesses are designed to completely encompass the respective components 56, 50 and 52 when the bottom surface of the member 40 is brought into intimate contact with the top surface of the eg ion .64.
- an antireflective coating 74 is included on the bottom surface of the member 40 (FIG. 4) .
- a portion 76 of this layer is preferrably patterned to form a zone-plate lens for focusing optical signals emanating from the emitter 50 and directed at the detector 48.
- the zone-plate lens 76 may be formed at other levels in the path between optical components or, if optical signal levels are adequate, may be left out altogether.
- an air gap will invariably exist between at least some portions of the bottom surface of the member 40 and the top surface of the wafer 44, and between the member 40 and the wafer 42.
- any gaps that do exist are preferrably designed to be much greater than the wavelength of the propagating optical signals.
- the top surface of the planarizing member 40 of FIG. 4 includes, for example, a layer 78 of a material such as silicon nitride and a metallic layer 80.
- the layer 78 is proportioned to be antireflective, and the layer 80 is patterned to provide apertures that help to confine propagating optical beams.
- a zone-plate lens 82 is formed in the layer 78 for the purpose of focusing optical signals emanating from the emitter 46 and directed at the detector 52.
- the structure of FIG. 4 also includes protuberances 84 through 86 and mating holes 87 through 89 utilized for the purpose of aligning the member 40 and the wafers 42 and 44.
- the depicted structure can be held together in any one of a number of standard ways.
- a suitable mechanical clamp (not shown) may be employed for this purpose.
- an adhesive disposed on peripheral portions of the member 40 and the wafers 42 and 44 may be utilized to maintain the assembly together.
- the instrumentality used should allow for easy disassembly of the depicted structure. In that way, repair or modification of the WSI assembly is facilitated.
- Other wafers and planarizing members can be added to the structure shown in FIG.
- WSI assemblies can take many forms, many of which can incorporate the present invention.
- the assemblies can be made of other optically transparent materials, such as gallium arsenide.
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Optics & Photonics (AREA)
- Wire Bonding (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Un ensemble est obtenu en empilant plusieurs plaques en silicium intégrées à l'échelle d'une tranche. Des connexions entre des niveaux de l'ensemble sont réalisées par des signaux optiques transmis directement au travers des plaques de silicium.An assembly is obtained by stacking several silicon plates integrated on the scale of a wafer. Connections between levels of the assembly are made by optical signals transmitted directly through the silicon wafers.
Description
Claims
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US82062486A | 1986-01-21 | 1986-01-21 | |
US820624 | 1997-03-19 |
Publications (1)
Publication Number | Publication Date |
---|---|
EP0253886A1 true EP0253886A1 (en) | 1988-01-27 |
Family
ID=25231322
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP87902022A Withdrawn EP0253886A1 (en) | 1986-01-21 | 1986-12-24 | Interconnects for wafer-scale-integrated assembly |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP0253886A1 (en) |
JP (1) | JPS63502315A (en) |
KR (1) | KR880701024A (en) |
WO (1) | WO1987004566A1 (en) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0335104A3 (en) * | 1988-03-31 | 1991-11-06 | Siemens Aktiengesellschaft | Arrangement to optically couple one or a plurality of optical senders to one or a plurality of optical receivers of one or a plurality of integrated circuits |
GB2222720B (en) * | 1988-09-12 | 1992-03-25 | Stc Plc | Opto-electronic devices |
US5150196A (en) * | 1989-07-17 | 1992-09-22 | Hughes Aircraft Company | Hermetic sealing of wafer scale integrated wafer |
DE4005003C2 (en) * | 1990-02-19 | 2001-09-13 | Steve Cordell | Method of preventing knowledge of the structure or function of an integrated circuit |
US5146078A (en) * | 1991-01-10 | 1992-09-08 | At&T Bell Laboratories | Articles and systems comprising optically communicating logic elements including an electro-optical logic element |
US5200631A (en) * | 1991-08-06 | 1993-04-06 | International Business Machines Corporation | High speed optical interconnect |
CH685522A5 (en) * | 1991-09-10 | 1995-07-31 | Suisse Electronique Microtech | Method for positioning a first substrate on a second substrate and micromechanical device obtained positioning. |
JPH05251717A (en) * | 1992-03-04 | 1993-09-28 | Hitachi Ltd | Semiconductor package and semiconductor module |
DE4211899C2 (en) * | 1992-04-09 | 1998-07-16 | Daimler Benz Aerospace Ag | Microsystem laser arrangement and microsystem laser |
DK0603549T3 (en) * | 1992-11-25 | 2000-09-04 | Bosch Gmbh Robert | Device for connecting a light emitting element to a light receiving element |
DE4313493A1 (en) * | 1992-11-25 | 1994-05-26 | Ant Nachrichtentech | Arrangement for coupling an optical waveguide to a light-emitting or receiving element |
DE4323681A1 (en) * | 1993-07-15 | 1995-01-19 | Bosch Gmbh Robert | Arrangement for coupling at least one optical fiber to at least one optical receiving or transmitting element and a method for producing the arrangement |
US6831301B2 (en) * | 2001-10-15 | 2004-12-14 | Micron Technology, Inc. | Method and system for electrically coupling a chip to chip package |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1112992A (en) * | 1964-08-18 | 1968-05-08 | Texas Instruments Inc | Three-dimensional integrated circuits and methods of making same |
US3663194A (en) * | 1970-05-25 | 1972-05-16 | Ibm | Method for making monolithic opto-electronic structure |
US4169001A (en) * | 1976-10-18 | 1979-09-25 | International Business Machines Corporation | Method of making multilayer module having optical channels therein |
US4533833A (en) * | 1982-08-19 | 1985-08-06 | At&T Bell Laboratories | Optically coupled integrated circuit array |
FR2537825B3 (en) * | 1982-12-10 | 1987-11-13 | Thomson Csf Mat Tel | INTERCONNECTION SYSTEM FOR PRINTED CIRCUIT BOARDS |
-
1986
- 1986-12-24 EP EP87902022A patent/EP0253886A1/en not_active Withdrawn
- 1986-12-24 WO PCT/US1986/002805 patent/WO1987004566A1/en not_active Application Discontinuation
- 1986-12-24 JP JP87502051A patent/JPS63502315A/en active Pending
-
1987
- 1987-09-18 KR KR870700843A patent/KR880701024A/en not_active Application Discontinuation
Non-Patent Citations (1)
Title |
---|
See references of WO8704566A1 * |
Also Published As
Publication number | Publication date |
---|---|
JPS63502315A (en) | 1988-09-01 |
KR880701024A (en) | 1988-04-13 |
WO1987004566A1 (en) | 1987-07-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5424573A (en) | Semiconductor package having optical interconnection access | |
US6343171B1 (en) | Systems based on opto-electronic substrates with electrical and optical interconnections and methods for making | |
US6611635B1 (en) | Opto-electronic substrates with electrical and optical interconnections and methods for making | |
US8265432B2 (en) | Optical transceiver module with optical windows | |
US6845184B1 (en) | Multi-layer opto-electronic substrates with electrical and optical interconnections and methods for making | |
US7751659B2 (en) | Optical apparatus | |
JP3728147B2 (en) | Opto-electric hybrid wiring board | |
US7430127B2 (en) | Electronic circuit board | |
US5638469A (en) | Microelectronic module having optical and electrical interconnects | |
KR100441810B1 (en) | Electronic device to align light transmission structures | |
US5513021A (en) | Optical detectors and sources with merged holographic optical elements suitable for optoelectronic interconnects | |
JP4479875B2 (en) | Optical subassembly | |
JPH071792B2 (en) | Optical communication system | |
JP4640498B2 (en) | Element transfer method, element arrangement substrate, device and manufacturing method thereof | |
US7961989B2 (en) | Optical chassis, camera having an optical chassis, and associated methods | |
US20020039464A1 (en) | Optical reflective structures and method for making | |
JPH0763958A (en) | Substrate-embedded type inserting receptacle for connecting optical fiber bundle to module | |
US8330262B2 (en) | Processes for enhanced 3D integration and structures generated using the same | |
EP0253886A1 (en) | Interconnects for wafer-scale-integrated assembly | |
JPS59501431A (en) | Optically coupled integrated circuit array | |
JP2006258835A (en) | Optical waveguide module, photoelectric converter and optical waveguide member | |
JP4643891B2 (en) | Positioning method for parallel optical system connection device | |
JP3684112B2 (en) | Opto-electric hybrid board, driving method thereof, and electronic circuit device using the same | |
US11300740B1 (en) | Optical module package | |
JP3440679B2 (en) | Semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): DE FR GB IT NL |
|
17P | Request for examination filed |
Effective date: 19880120 |
|
17Q | First examination report despatched |
Effective date: 19910426 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN |
|
18D | Application deemed to be withdrawn |
Effective date: 19910907 |
|
RIN1 | Information on inventor provided before grant (corrected) |
Inventor name: TEWKSBURY, STUART, KEENE Inventor name: HORNAK, LAWRENCE, ANTHONY |