EP0242098A2

EP0242098A2 - Parallel computation circuit

Info

Publication number: EP0242098A2
Application number: EP87302964A
Authority: EP
Inventors: John Stewart Denker; Richard Edwin Howard; Lawrence David Jackel
Original assignee: American Telephone and Telegraph Co Inc; AT&T Corp
Current assignee: AT&T Corp
Priority date: 1986-04-14
Filing date: 1987-04-06
Publication date: 1987-10-21
Anticipated expiration: 2007-04-06
Also published as: US4755963A; SG23194G; CA1258133A; JPS62295186A; DE3787395T2; DE3787395D1; ES2042554T3; EP0242098B1; EP0242098A3; JPH0799526B2

Abstract

A highly interconnected analog network is constructed with inter-neurons (e.g., 16-18) that account for energy function terms of order greater than two. The network comprises analog amplifiers that are connected with a resistive interconnection matrix (30) which connects each amplifier output to the input of all other amplifiers. The connections embodied in the matrix are achieved with conductances whose values are computed in accordance with the set of problem restrictions, while the cost variables of the problem which are to be minimized are incorporated in the input signals.

Description

Background of the Invention

This relates to apparatus for parallel processing of signals.
In spite of the tremendous computational power of digital computers, for a variety of reasons many practical problems cannot effectively be solved by the digital computer. The reason may be that a closed form solution is unavailable for the particular formulation of the problem and, therefore, numerical methods must be employed; or it may be that the number of variables in an optimization problem is large, and finding the optimum solution from the very large set of possible solutions is just too great a task to be performed by a digital computer in a reasonable time.
Heretofore, most artisans have either suffered the limitations of general purpose digital computers, or developed special purpose digital computers to solve their particular problems more efficiently. Recently, advances have brought to the forefront a class of highly parallel computation circuits that solve a large class of complex problems in analog fashion. These circuits comprise a plurality of amplifiers having a sigmoid transfer function and a resistive feedback network that connects the output of each amplifier to the input of the other amplifiers. Each amplifier input also includes a capacitor connected to ground and a resistor connected to ground. Input currents are fed into each amplifier input, and output is obtained from the collection of output voltages of the amplifiers.
A generalized diagram of this circuit is shown in FIG. 1, depicting five amplifiers (10-14) with positive and negative outputs V, and -V, on line pair 21, V₂ and -V₂ on line pair 33, V₃ and -V₃ on line pair 23, V₄ and -V, on line pair 24, and V_N and -V_N on line pair 25. Those outputs are connected to an interconnection block 20 which has output lines 41-45 connected to the input ports of amplifiers 10-14, respectively. Within interconnection block 20, each output voltage V_i is connected to each and every output line of block 20 through a conductance (e.g., resistor). For convenience, the conductance may be identified by the specific output line (i.e., source) that is connected by the conductance to a specific voltage line. For example T
1 identifies the conductance that connects the positive output V₂ of amplifier 11 to the input of the first amplifier (line 41).
Also connected to each amplifier input port is a resistor and a capacitor whose second lead is grounded, and means for injecting a current (from some outside source) into each input port.
Applying Kirchoff's current law to the input port of each amplifier i of FIG. 1 yields the equation:
where

C; is the capacitance between the input of amplifier i and ground,
is the equivalent resistance and it equals
, where ρ_i is the resistance between the input of amplifier i and ground,
u; is the voltage at the input of amplifier i,
T
j is the a conductance between the positive output of amplifier j and the input of amplifier i,
V_i is the positive output voltage of amplifier j, and
I_iis the current driven into the input port of amplifier i by an external source.

When T
j and T
j are disjoint, T
j -T
j may for convenience be expressed as T_ij, and it is well known that a circuit satisfying Equation (1) with symmetric T_ij terms is stable. It is also well known that such a circuit responds to applied stimuli, and reaches a steady state condition after a short transition time. At steady state, du_i/dt=0 and dV_i/dt=0.
With this known stability in mind, the behavior of other functions may be studied which relate to the circuit of FIG.1 and involve the input signals of the circuit, the output signals of the circuit, and/or the circuit's internal parameters.
For example, a function was studied that has the form
It is observed that the integral of the function g ; ^I (V) approaches 0 as the gain of amplifier i approaches infinity. Also, the time derivative of the function E is negative, and that it reaches 0 when the time derivative of voltages V_i reaches 0. Since equation (1) assures the condition of dV;/dt approaching 0 for all i, the function E of equation (2) is assured of reaching a stable state. The discovery of this function E led to the use of the FIG.1 circuit in problem solving applications in associative memory applications, and in decomposition problems.
The FIG. 1 circuit can solve the above classes of problems when those problems are structured so that the minimization of a function having at most second order terms in some parameters of the problem results in the desired solution. Other problems, however, may require the minimization of equations that contain terms of order higher than two. Those may be problems that perhaps can otherwise be stated with second order terms, but the statement with higher order terms is more meaningful, or they may be problems that can only be described with the use of higher order terms.
It is the object of this invention, therefore, to obtain solutions for problems characterized by higher order terms with a highly parallel circuit not unlike the circuit of FIG. 1.

Summary of the Invention

These objects are achieved with an interconnected analog network that is constructed with inter-neurons that account for terms of order greater than two. The network comprises analog amplifiers that are connected with a resistive interconnection matrix which, like the prior art network, connects each amplifier output to the input of all other amplifiers. The connections embodied in the matrix are achieved with conductances whose values are computed in accordance with the set of problem restrictions, while the cost variables of the problem which are to be minimized are applied as input signals.

Brief Description of the Drawing

FIG. 1 describes the prior art highly interconnected analog network: and
FIG. 2 describes a network constructed in accordance with the principles of our invention.

Detailed Description

The principles of our invention may be more fully understood and appreciated when applied to a specific problem and, to that end, the following detailed description presents the best mode for constructing a highly parallel computation circuit for solving a minimization problem characterized by an equation that has terms of order greater than two.
For purposes of illustration, the problem selected is the classic routing problem, such as encountered in the airline industry. In such a problem there may be N points where stops can be made (e.g., cities), and there is a cost associated with travelling from one point to the next. The object is to find a path in conformance to the rules of the problem at hand which connects a given origin point with a specific destination point at a minimum attendant overall cost.
One way to solve this problem is to construct a cost function that describes the desired attributes of the final solution, and to select the variables of that function so that the cost is minimized. Equation (3) below is one such cost function
where V_AB represents a link from point (city) A to point (city) B, and _CAB represents the direct cost associated with taking link AB. The presence or absence of link AB in the solution is indicated by V_AB either taking on the value 1 or 0, respectively, and thus, the terms _CABV_ABcombine to represent the overall direct cost of taking a particular route. A specification that a particular link may not be present in the solution tour is accomplished by assigning a high cost factor _CAB to the impermissible link.
In a routing problem of N points, each point may have a link to all other points and, hence, at most (N) (N-1) links can exist. This number corresponds to the number of terms in Equation (3) and is equal to the number of direct cost terms in Hopfield's model. It may be noted that since it is links that are considered rather than cities, the V terms herein are characterized by two subscripts rather than one. Consequently, we might expect that terms which otherwise correspond to the T_ij terms found in Equation (2) would appear with four subscripts, e.g., T_ijkl. Also, the summations performed would be over four indices rather than two.
Although the Equation (3) cost function describes the direct cost of a tour, in itself it is not sufficient to insure that a solution would be found to the tour minimization problem. For example, Equation (3) clearly permits a tour specification of a link DE followed by a link DF, but links DE and DF emanate from the same point (D) and cannot follow each other. This is an "outgoing branch" condition. Since the "outgoing branch" condition is unacceptable in the final solution, we discourage it by adding the penalty function
to the overall cost function of Equation (3). Equation (3) says, in essence, that a traversal from A to B followed by a traversal from A to B shall be very costly (a is large).
A corollary to the "outgoing branch" condition is the "incoming branch" condition, where more than one link is chosen to reach a certain point. This unwanted condition is discouraged by adding the penalty function
to the overall cost function of Equation (3).
The terms contributed by Equations (4) and (5) are similar to the first term in Equation (2), in that the variable V appears in the second degree, and so those terms present no problem in the realization of a circuit to minimize the cost function resulting from combining Equations (3), (4), and (5). However, preventing the "outgoing branch" and "incoming branch" conditions may not be sufficient.
A further condition of Equation (3) relates to the selection of some links and the non-selection of some other possible links. When one visualizes the physical problem, it is readily apparent that having taken one link to reach a point A, some link emanating from point A must also be taken; otherwise the tour cannot properly be completed. Stated in other words, having taken a certain link and having taken one of a number of other links would not comport with a valid solution to the physical problem. Conversely, a solution where a link is taken from a point A but no link is taken to reach point A also does not comport with a physically realizable solution to the problem. This continuity requirement applied to all points of the tour, save for the starting (origin) point, α, and the end (destination) point, m. At those points we wish not to discourage the breaking of continuity, and in fact we wish to encourage it. Accordingly, an additional function is constructed and added to the overall cost function of Equation (3), which considers each link AB and imposes penalties for certain conditions at points A and B. That function (discussed in detail below) is
where the first three terms concern themselves with continuity at point B, and the last three terms concern themselves with continuity at point A.
With respect to Point B, as long as it is not the end point, ω, the desired solution must include a link from point B to some point C. Accordingly, the first term in Equation (6) imposes a penalty for not including a link from point B to some point C. Stated in other words, a penalty λ₃ is imposed when a link AB is taken AND a link BC (where C is any other point) is not taken. The product operator n performs the logic AND function and, hence, when a link BC is taken, the resulting product is zero and penalty λ₃ is not imposed. When B is the destination point, however, the first term imposes no penalties, but the second term imposes a penalty for not entering ω, and the third term imposes a penalty for exiting m.
With respect to point A, as long as it is not the starting point, a, the desired solution must include a link from some point C to point A. Accordingly, the fourth term in Equation (6) imposes a penalty for not including a link from some point C to point A. When point A is the starting point, however, the fourth term imposes no penalties, but the fifth term imposes a penalty for not exiting a, and the sixth term imposes a penalty for entering a.
There are two situations that may occur where continuity is maintained but it is undesirable. These are when a "stand still" path is taken, such as V_AA, and when a "backtrack" path is taken, such as V_AB followed by V_BA. These undesirable situations are penalized with function E₄ that has the form
Utilizing the equality
the cost function which combines Equations (3) through (7) equals to the following:
Equation (9) represents a valid and useful statement of the overall cost function of the routing problem. Unfortunately, the terms having the product operator II are approximately in the N^th degree of the variable V. The overall cost function is therefore not of the form described in the aforementioned copending applications, and it would appear that this overall cost function cannot be mapped onto the circuit of FIG. 1 as described by the prior art. We discovered a way to restructure the problem and make it solvable with a circuit akin to the circuit of FIG. 1.
In solving the minimization problem in accordance with Equation (2), the FIG. 1 circuit developes an output voltage for each V term and, when the circuit reaches steady state, these voltages assume either the value 1 or 0. Realizing that the product terms (e.g.,
V BC) are also restricted in the steady state to 0 or 1, we replace terms of the form
V_BC with single variables of the form V_Bout and the term T V_CA with the single variable ViA. This yields a cost function equation that has terms with V variables only in the first or second degree. On first blush this process of replacement appears to be merely form over substance; but that is not the case, as shown below.
We call the V_Bout and V_inA terms inter-neurons which, in their steady state, are either 1 (turned on) or 0 (turned off). Whatever state the inter-neurons assume, however, they must satisfy their definitional equality; and this imperative may be incorporated in the overall cost function by assigning a penalty for failing to satisfy the equality. Employing De Morgan's theorem offers the identity
and in our application where the final state of an inter-neuron is either 1 or 0,
is also equal to 1 -
V_xy. Employing the above, an additional cost function to be included in the overall cost function can be created which introduces the concept of a penalty for failure to satisfy the definitional requirement of inter-neurons. Specifically, the term
in Equation (9) is replaced with V_Bout and the cost term λ₁₁ (V_Bout+
V _BC -1)² is added. Similarly, the term
in Equation (9) is replaced with V_inA and the cost term λ₁₂ ( V_inA +
V_CA -1 )² is added. Finally, the term
is replaced with 1 -
VA,, and the term
is replaced with 1 -
V_aB.
Combining the above cost functions yields the final overall cost function:
Equation (10) has the general form of Equation (2) in that it has terms in V only of the first degree and of the second degree. It differs from Equation (2) only in that the terms don't all appear as summations over four indices. That can be remedied, however, in a straightforward manner. For example, the term
can be converted to
(or rewritten in a simpler form as
where
is a function whose value is 1 when k=i, and 0 otherwise. In addition to the introduction of the δ function, the above makes a simple variable transformation to reduce confusion.
The above procedure can be applied to each and every term in Equation (10), yielding the table:

which may be written as
where

and
A perusal of Equations (10) and (11) reveals that the terms corresponding to the I_ij coefficients contain the direct cost factors (C_ij) of the problem, and and δ terms. The T_ijkl coefficients comprise only a and 5 terms. The 5 and λ terms define the ever-present restrictions on valid solutions for the type of problem described, and hence the mapping of those terms onto the T_ij elements of Equation (2) leads to the advantageous result that a highly parallel computation circuit can be constructed with feedback terms T_ij being independent of the specific routing problem to be solved.
FIG. 2 depicts a circuit that attains a minimum for the cost function of Equations (10) and (11). It is similar to the FIG. 1 circuit in that there are output voltages V,, V2, ... V_N2 (obtained from corresponding amplifiers) and an interconnection block 30 that connects those output voltages to the various input ports of the amplifiers. It differs, however, in that additional amplifiers, 16, 17, 18 are provided that develop the inter-neuron outputs
and those, too, are connected to interconnection block 30. In this manner the inter-neurons affect the output voltages, and the output voltages affect the inter-neurons to insure that the inter-neurons follow their definitional equality, causing the overall cost function (10) to be minimized. FIG. 2 also includes a network 40 which implements the connections embodied in the coefficient of the I_ij term of Equation (11). Evaluation of the I_ij and T_ijkl terms of Equation (11) for a particular routing problem yields the actual conductance values in the feedback matrices of FIG. 2.
The above describes a very specific example of a system where the energy to be minimized is expressed in terms of output signal products of degree greater than two. Because of the specific nature of the illustrative example, the resulting equations (10 and 11) are rather long and somewhat complex. So as not to overlook the forest for the trees, it is reiterated here that our concept of inter-neurons is applicable whenever the energy function has a term that contains a product such as
In accordance with our invention, the first of these terms converts to V_ABV_inA and a penalty term of the form λ(V_inA +
V_CA-1)² is added to the energy function. Similarly, the second of these terms converts to V_ABV_Cout and the penalty of the form x(V_Cout +
V_CD-1)² is added to the energy function. Introduction of the V_inA and V_Cout terms corresponds to the inclusion of an input inter-neuron and an output inter-neuron, respectively; and that translates to an additional active element in the system that implements the energy minimization process. The feedback matrix that connects the output of each amplifier to the input of all amplifiers, expressed as
is augmented for each input inter-neuron with a term of the form
and is augmented for each output inter-neuron with a term of the form
The matrix that provides input currents to the amplifiers is augmented in a similar fashion as shown in Equation (11).
Of course other index patterns in the higher order product terms of the energy function would yield somewhat different augmentation terms to the V_ijklmatrix and to the I_ij matrix; but those variations are clearly within the contemplation of our invention.
Expressing the principles of our invention in even broader terms, whenever the energy function has terms of order greater than two, such as V_u•V_w •V_x•V_y •V_z .... In accordance with our invention, such terms are converted to V_u•V _m, where each V_m is a new inter-neuron term, and a penalty term of the form
is added to the energy function. Introduction of the V_m translates to an additional active element in the system that implements the energy minimization process. The feedback matrix that connects the output of each amplifier to the input of all amplifiers is augmented for each inter-neuron by the coefficients of the equation

Claims

1. A parallel circuit for developing N simultaneous output signals which minimize an energy function that is characterized by said output signals in terms of products of different ones of said output signals, including product terms of degree greater than two, comprising:

a plurality of M amplifiers where M is greater than N by the number of terms in said energy function whose order is greater than two; and

a feedback conductance matrix connecting the output of each of said amplifiers, V_jj, to the input of each of said amplifiers, forming M² connections, with each of said connections being effected through a conductance T_ijkl;

CHARACTERIZED IN THAT

said feedback matrix comprises conductances T_ijkl connecting the output of amplifier ij to the input of amplifier kl with conductance values which are linear combinations of A_x and

terms, where λ_x are predetermined penalty constants and

is a function whose value is one when y = z, and zero otherwise, where y and z belong to the set {i, j, k, I}.

2. The circuit of claim 1, further comprising an input matrix for injecting a predetermined current into each of said inputs of said amplifiers.

3. The apparatus of claim 2 wherein said input matrix is a combination of preselected input signals and a linear combination of λ_x and

terms, wherein said preselected input signals uniquely characterize the circuit's response to stimuli, λ_x are preselected penalty constants and

is a function in y and z whose value is one when y = and zero otherwise, with y and z belonging to the set {i, j, k, I}.

4. The circuit of claim 1 wherein for each term in said energy function whose degree is greater than two, said M is increased by one and said feedback matrix is augmented by the coefficients of the equation

where V_u, V_w, and V_x, are said amplifier output voltages included in that term of said energy function whose degree is greater than two, and V_m is the amplifier output voltage of an additional amplifier included in said plurality of M amplifiers.

5. The circuit of claim 1 wherein for each term in said energy function of the form V_uV _wV_x ... said M is increased by one and said feedback matrix is augmented by the coefficients of the equation

where V_u, V_w, and V_x, are said amplifier output voltages included in that term of said energy function whose degree is greater than two, and V_m is the amplifier output voltage of an an additional amplifier included in said plurality of M amplifiers.

6. The circuit of claim 1 wherein for each term in said energy function of the form

said plurality of M amplifiers is increased by one amplifier developing an output voltage VinA and said feedback matrix is augmented with a term of the form

where λ is a preselected penalty constant and 5 is a function in the variables appearing as a subscript and a superscript of δ, whose value is one when subscript is equal to the superscript and zero otherwise.

7. The circuit of claim 1 wherein for each term in said energy function of the form

said plurality of M amplifiers is increased by one amplifier developing an output voltage VCout and said feedback matrix is augmented with a term of the form

where λ is a preselected penalty constant and δ is a function in the variables appearing as a subscript and a superscript of δ, whose value is one when subscript is equal to the superscript and zero otherwise.