Classifications

• • G—PHYSICS
  • G05—CONTROLLING; REGULATING
  • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
  • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
  • G05F1/66—Regulating electric power
  • G05F1/67—Regulating electric power to the maximum power available from a generator, e.g. from solar cell

Definitions

• the present invention relates to an electronic control
• the invention has particular utility in relation to 0 photovoltaic cells when used for the purpose of charging 1 batteries but, as will become apparent hereinbelow, it is 2 not limited to this particular use.
• 3 A problem with photovoltaic cells is that they have 4 only one point on their voltage-current characteristic curve 5 where maximum power occurs. This also applies when they are 6 connected into modules for battery charging.
• Figure 1 of the 7 attached drawings shows a curve 40, of a typical 12 volt 8 module for battery charging. The maximum power point is 9 labelled Vp.Ip and occurs on the "knee" of the curve at 0 about 16 volts. Obviously the maximum power can only be 1 transferred if the battery also equals this voltage.
• a 2 nominal 12 volt lead-acid battery will vary from less than 3 11 volts when fully discharged to 15 or 16 volts when fully 4 charged. It is normal practice to limit or "float" the 5 battery at 14.4 volts. (Battery limits are labelled as X and 6 Y). The maximum power capability of the solar module is 7 therefore rarely realized. With a resistive load, unless the 8 load equals Vp/Ip, according to ohms law, then maximum power 9 is not transferred either.
• Figure 3 shows the same module 0 curve reconstructed as "power versus volts" and better 1 illustrates the effect of "clamping" the output voltage with 2 a battery - the lower the battery voltage, the lower the 3 output power.
• the output of a solar collector (thermal or electrical) is dependent upon its position relative to the sun.
• Fixed collectors will have an output which is sinusoidal throughout the period of one day due to the rotation of the earth relative to the sun. Maximum output will occur (in the middle of the day) when the sun's rays are perpendicular to the collector.
• the output of a fixed solar collector is sinusoidal with respect to time of day as will be evident from Figure 4 of the accompanying drawings.
• the area enclosed by points G,H,I, & J represents the maximum theoretical gain in power if the collector is at all times perpendicular to the sun on a clear day (No allowance is made, or attempted, for atmospheric effects).
• the theoretical maximum gain is the difference between the area under the sine, wave and the area enclosed by points G,H,I & J. This can be found from the difference between the R.M.S. and peak values of the sine wave and is a gain of approximately 41.4%.
• Present types of solar collector tracking devices do not take account of all variations in the direction of solar input such as cloud or shadows and can also be complicated and costly.
• One known method is to use light-sensitive devices fixed at each side of the collector so that they are cast in shadow by the movement of the collector.
• the collector is moved depending on the presence or absence of light on these devices.
• the obvious disadvantage is that no other shadows may be allowed to reach the sensors other than that caused by collector movement.
• the sensors may also react differently to varying solar input.
• Another known method is to position the collector during the day to where it is expected that the sun will be. This can be done using a positional feedback device, which is costly, or by a position-controllable motor such as a stepper motor. This method also cannot compensate for variations caused by shadow or cloud and cannot guarantee maximum power at all times. Both of the above methods require control circuits separate to any output regulator and neither method provides positioning of the collector which is directly related to its power output.
• the invention provides an electronic circuit for maximizing power transfer between a varying power supply (21) and an electrical load (22), characterized in that, said circuit includes power measurement circuitry (23) for successively measuring the output power from said supply (21), storage circuitry (27) for storing the latest measurement of said output power, a comparator (24) for comparing said latest measurement of said output power with the immediately preceding said measurement and providing an output signal 3 when said output power has decreased, control decision circuitry (31) for providing a first control signal 1 to cause variation by a predetermined amount in either one of opposite directions os control means (28,30) connected to said power supply to cause variation of the power transferred from said power supply to said load (22), said control circuitry (31) is connected to receive said output signal 3 and in response thereto provide a second control 2 signal to change the direction of said variation caused by said first control signal and limit detecting circuitry
• Figure 1 referred to previously is a graph of current versus voltage for a typical 12 volt solar module
• Figure 2 shows the curve 40, of Figure 1 re-drawn to illustrate efficiency versus voltage and for comparison of regulators
• Figure 3 shows the curve 40, of Figure 1 re-drawn as power versus volts
• Figure 4 is a graph for comparison of outputs between "fixed" and “tracking" solar collectors
• Figure 5 is a circuit block diagram of a solar power system using an inverter and a stepper motor with "power- maximizing" feedback and a voltage monitor for regulation according to the embodiment of the invention
• Fi g ure 6 i s a bas ic f l ow chart o f the " p ower- maximizing" f eedback techn ique used in the embodiment of Figure 5
• Figures 7A - 7D combined to provide a more detailed circuit block diagram of the solar
• the embodiment described below enables users of photovoltaic cells to extract more power from them than present techniques. Not all circuit elements are labelled in the drawings but those elements not labelled will be readily evident to persons skilled in the art by the standard symbols used. Advances in semi-conductor technology have made it possible to develop sophisticated, but efficient, control circuits at the low power levels normally associated with photovoltaic cells.
• the described circuit continuously measures and adjusts the output power of a solar module to the maximum which can be transferred to the load or battery. It also on a timed basis, re-adjusts the position of the solar module relative to the sun to that which provides maximum power. Voltage regulation is also provided.
• Three control signals represented 1 , 2 and 3 on the drawings are necessary within the feedback loop as follows:- 1 Vary the control, 2 Change the direction of variation, and 3 Decrease (in output power) detected. This is because the output power will "peak" at one point.
• a power measurement circuit 23 and comparison circuit 24 combined with a store for previous measurement.27, detect a decrease at either side of the peak point and force the control in the opposite direction. If a decrease is caused by external influences such as sunlight or load variation, the effect will be that the circuit will "track” the output power until it settles and again forces the output power to its maximum.
• the three control signal ' s within the feedback loop are also used to control a stepper motor 25 which drives the solar module 21, on its axis relative to the sun.
• a timer 26, in conjunction with main control 31 controls when the motor 25 is being used as the controlled element, within the feedback loop, instead of the inverter 20.
• Voltage regulation is achieved by the voltage monitor 33.
• the motor and inverter each have their own controls, 28 & 30 respectively. Each of these has a limit detecting circuit 43, to cause a change in direction of the control variation and prevent latch-up.
• the inverter control is fed by a clock 29 to set the operating frequency.
• a system clock 32 is used to synchronize events within the circuit. Voltage regulation is provided by the voltage monitor 33.
• Control signal 1 "vary the control" can theoretically be free to continuously vary in both directions and simply forced to change direction when necessary but it is more advantageous to control the "amount" of variation in synchronism with the measurement and comparison functions.
• the circuit of this invention uses a high frequency switch Tl followed by an averaging L/C filter (L1,C2) to provide variable D.C. output - commonly known as a "buck" (step-down) regulator.
• L1,C2 averaging L/C filter
• buck step-down
• Other types of inverter/converter can be used depending on the relationship between input voltage and desired output voltage.
• switching, diodes, inductor cores and capacitors have made it possible to develop very efficient circuits exceeding 90% efficiency.
• control circuits using C-mos and other low power techniques also offer high efficiency.
• FIG. 1 shows the curve 40 from Figure 1 re-drawn to illustrate efficiency - power out/total power . available.
• a switched series regulator indicated by curve 41 on Figure 2 and using the same F.E.T. and blocking diode as the circuit described below would have a loss of about one watt with the illustrated power levels and, combined with the inherent inefficiency of the module, would result in a regulator with an efficiency of about 72% ⁇ 11 volts (point B on graph) to 92.5% @ 14.4 volts (point E on graph).
• the power-maximizing regulator (curve 42 of Figure 2) with a selected efficiency of 90% is only beaten by the switched regulator when the output voltage exceeds 13.8V (point D on graph). The difference between them from then on is only slight as the power-maximizing regulator wil-1 be operating at close to 100% duty cycle.
• the circuit described below is capable of measuring a change of l/256th of peak output power and will only vary the duty cycle by the amount necessary to detect this change.
• the loss in output power compared to the switched series regulator (curve 41) is then approximately equal to the circuit requirements plus l/256th of peak output power. Any inefficiencies above 13.8 volts are fairly insignificant as the battery will be almost fully charged.
• FIG. 7A - 7E is a more detailed circuit diagram of the solar power system of Figure 5.
• Figures 7A - 7C the power-maximizing regulator, contains the inverter 20, the power-maximizing feedback loop elements, power measurement circuit 23, store 27, comparator 24, decision and control circuits 30 and 31, and also contains the voltage monitor circuit 33.
• Figure 7D - 7E is the power-maximizing position controller section and contains the timer 26, counters and motor drive circuits 28. It uses the feedback loop elements of Figure 7A - 7C.
• the circuit is intended for a solar power system where the voltage at peak power (Vp) of the solar module is always greater than the voltage of load 22.
• Vp voltage at peak power
• the main switching F.E.T., Tl is driven by a variable duty cycle pulse from U5 resulting in a variable width pulse at its source terminal(s). This pulse is then fed through a low-pass filter comprising LI and C2. Diode Dl returns energy stored in LI, to the load, when Tl switches off. D2 is a blocking diode to prevent reverse current from a battery at the output 52 when the circuit is off. The resulting output is a function of input voltage and duty cycle. 3.
• POWER MEASUREMENT I.C. U6 is a transconductance operational amplifier (3080). Its output current is proportional to the product of the voltage across its input terminals (pins 2 and 3) and the current into pin 5.
• the voltage across pins 2 and 3 is proportional to output current, as it is sensed by resistor R4.
• the current into pin 5 is proportional to output voltage - via RV1, RI.
• the output current of U6 is therefore proportional to output volts times output current and represents output power.
• To develop a voltage from the output current of U6 it is fed into R2.
• DIGITAL CONVERSION, STORAGE AND COMPARISON U8, U9A, U10-12 form a "tracking" analog to digital (8 bit) converter.
• Clock pulses are supplied by U35, a 555 astable multivibrator, via U36 NAND gate.
• the output from U12 (pin 16) is a voltage proportional to the state of the two up/down counters -U10 and Ull.
• Comparator U8 compares the output from U12 with the voltage across R2. The output of U8, when latched by the flip-flop U9A, determines the direction of counters U10 and Ull, in order to make the output of U12 equal the voltage across R2.
• the output of U12 will swing above and below the input voltage by an amount determined by the sensitivity of the comparator, U8 and/or the voltage steps of U12 - (ideally this will be ⁇ 1 LSB) - U12 has an output voltage range of zero to 2.56 volts in 256 steps (8 bit) so the resolution of measurement is ⁇ .01 volt.
• U9A Each time the "Q" output of U9A goes high the state of counters U10 and Ull will digitally represent the output power.
• the circuit is calibrated so that peak voltage across R2 (peak output power) is never greater than 2.56 volts.
• the power measurement resolution would be approximately 130m watts (33.6 divided by 256).
• Each measurement is subsequently stored in the 8 bit latch, U15, via data bus 53 (see control and decision section) where it is available to be compared with the present measurement by the digital comparators U13 and U14.
• the A ⁇ B output (pin 7) of U14 goes high whenever the data at the outputs of U15 exceeds the state of the counters U10 and Ull. Strobing of this output and data control is explained in the control and decision section.
• This A ⁇ B output is the equivalent of control signal 3 "decrease (in output power) detected" which is shown on Figure 5. 5.
• DIGITALLY-CONTROLLED DUTY CYCLE The duty cycle is fully variable in 256 steps (8 bit) from 0 to 100%.
• U16 - U21 are 4 bit binary counters connected in 8 bit pairs.
• U16 - U19 are high speed types and are driven by a crystal controlled oscillator U22.
• U16 and U17 divide this clock frequency by 256 and the output of U17 (pin 12) drives the clock input of a flip-flop, U23A.
• U23A output "Q" will go low and U18 and U19 will be “loaded” by the data at their inputs which is determined by the state of counters U20 and U21.
• the output of U19 (pin 12) when high, sets the output of U23A high.
• U20 and U21 Because the instant that the output of U19 going high is determined by the data loaded when U17 output goes high, the timing difference between their two outputs can be controlled by U20 and U21 and will determine the duty cycle at the output of U23A. This is used, via level-shifting transistors, T2 and T3, and U5 to drive the "gate" of Tl and control the output.
• the outputs of U20 and U21 are controlled by two inputs - pin 15 of U20 and U21 is the clock input used to step the counters, pin 10 is the up/down control via NOR gate U24. They are reset to zero on power-up by pin 1 controlled by U25 via NOR gates and inverters. They can also be reset to zero by detection of high output voltage or held at zero by the voltage regulator (see regulation section).
• the preset input of U26A is taken high after a slight delay caused by R3 and C4. This makes the "Q" output of U26A go high, U26B goes low because of this high on its clear input, and NAND gate U36 is opened ready for the next clock pulse. U27 and U28 are closed and remain so until the next measurement has been made when the output of U9A goes high again.
• the output of U23B determines, for power-maximizing feedback, the direction in which the duty cycle is to be varied and controls U20 and U21 via NOR gate U24. It can be “overridden” by the other input to U24 which is the "decrease duty cycle" control 4 and comes from the voltage regulator section.
• U23B is also controlled by NOR gates, inverters and R-C networks.
• the "carry” output (pin 7) of U21 controls two of these NOR gates and forces a change of direction if the total count of U20 and U21 is being exceeded i.e. the duty cycle cannot suddenly overflow from 100% to zero, or from zero to 100%.
• This feature of the circuit is referred to elsewhere as a limit detector and shown as 43 on Figure 5. It prevents "latch-up" when no decrease in power is detected and the control variation limits are reached. When the duty cycle is being forced down by the voltage regulator and when zero is detected the NOR gates detect this and prevent further counting, effectively holding the duty cycle at zero. 7.
• VOLTAGE REGULATION Three comparators are used to control the output voltage within desired limits - U31 A,B, & C.
• the output of U23B is forced low by two NOR gates connected to its "set” and “reset” inputs.
• the duty cycle will then decrease each time that control line 1 is pulsed by the power-measurement control circuitry.
• the duty cycle will automatically increase because U23B was forced low and both inputs of U24 are now low causing a high on the up/down control of U20 and U21.
• the duty cycle will continue to increase until either the voltage comparator U31B or the power-maximizing feedback takes control again.
• the regulator functions normally until the timer signal comes on.
• the duty cycle of the regulator is held at this point to prevent it from influencing the output power.
• a stepper motor is then driven, once per power measurement.
• a decrease in output power causes the direction of the motor to change in the same manner that the direction of change of duty cycle was controlled in the regulator. If this process was left to continue, uninhibited, then the solar collector would move constantly between the two points which cause a decrease in output power i.e. moving away from maximum solar input in either direction.
• the motor is turned off when the collector is positioned at the mean of these two points, as follows.
• the first decrease in power may mean that the collector is moving initially, in the wrong direction, the direction of movement is changed and the motor drive continues.
• counters are initiated to count the number of steps until the third "change direction” signal occurs.
• the value now held by the counters represents the number of steps between the two positions which cause a decrease in output power.
• the collector is then stepped back by half this number of steps so that the collector is positioned at the mean position of maximum power output.
• the timer is reset by the counters reaching zero and the control signals are then used by the regulator, until the timer again initiates a tracking sequence.
• pulses are fed into point L via inverter U41A and NAND gates U42A and U42C and out through connection point to U20 of Figure 7A - 7C of the regulator to control the duty cycle.
• These pulses are counted by U54 to be used as the timed signal.
• the motor used in this example is a two-phase stepper motor, having two coils 55 & 56. These coils are driven by identical transistor bridge circuits, Til - T22 which are driven by NOR gates U51A - U51D. These are used to turn off all motor current whilst the circuit is not in use, i.e. the regulator is operating and the timer has not triggered.
• NOR gates are driven by two flip-flops, each controlled by three NAND gates at its input.
• the combination of NAND gates and flip-flops determine the necessary combination of phases to drive the motor.
• U45B determines the direction of rotation and U44A combined with two NAND gates at its output generates out of ' phase alternate pulses to step the motor.
• U54 When sufficient pulses have been counted by U54 its outputs Qll and Q12 go high, causing a low at the output of U42D. This low stops further pulses being sent to the regulator by closing gate U4-2C, allows U45A and U45B flip- flops to operate by taking their preset inputs low, and opens NOR gates U51A - U51D to allow motor current.
• the "Q" output of U45A is now low and allows binary counters U46 and U47 to operate - their count direction will be upwards as determined by the output of U45B which is connected to their up/down control inputs.
• the motor now changes direction again but this time each step will be counted by U46 and U47.
• the motor -continues to step in the new direction for each power measurement until a new "change direction” pulse causes U45B to change to a low.
• Counters U46 and U47 are now set to count down.
• U45A will still be low.
• the inverted outputs of U45A and U45B will both be high and these are detected by U53A, the output of which goes low.
• U44B flip-flop This low from U53A now allows U44B flip-flop to respond to the "step" pulses arriving at its clock input from connection L.
• U44B controls NAND gate U42A so that only every second "step” pulse is allowed to reach U44A and consequently the motor only steps once for every two “step” " pulses coming from the regulator.
• the motor now steps on every second pulse, counters U46 and U47 step down for every pulse. This process will continue until counters U46 and U47 reach zero when the carry output, "CO” of U47 will go low. While it is high it causes the output of U43D to be low which combines with the low from U53A at the inputs of U43C to produce a high at the clear inputs of U45A and U45B.
• FIG. 5 is a block diagram of a solar power system using an inverter with the "power- maximizing" feedback circuitry described in detail in relation to Figures 7A - 7C and 7D - 7 ⁇ , it can be seen that a controlled inverter 20, is located in a solar system between the solar module 21 and load 22. In this way it is possible to achieve the regulation attainable by linear regulators without the disadvantages mentioned in the introductory portion of this specification. It is possible to operate several regulators in parallel and achieve “incremental" operation but with better regulation.
• the circuit shown in Figures 7A - 7C and 7D - 7E incorporates the "power-maximizing" feedback technique so - 19 - that maximum power transfer is achieved until the voltage limit is reached and then the device functions as a voltage regulator and can automatically switch between the two modes of operation.
• the embodiment of Figure 5 merely shows the unique features of the present invention used in relation to a solar system. It will be evident from the above that the "power- maximizing" feedback technique has application in many areas and not just in the generation of electrical power. It can be used to maximize any electrically measurable term whether it be power, volts, current, temperature, speed, etc.
• the device to which it is applied has a peak in its output and can be controlled by an input, or by an external device which can be controlled by the circuit.
• the characteristic peak in output power of a solar cell has already been described.
• a similar peak occurs in the output of generators and alternators, and the positioning of solar collectors and control of one of these has been shown as an example where maximum output can be realized.
• Input and output conditions of the circuit are altered to suit the application but the heart of the circuit - measure, store, adjust, compare, decision - in conjunction with the flow chart of Figure 6, remain the same.
• One further example of the uses of the present invention will be described in relation to voltage regulators.
• the regulation of a linear regulator can be equalled.
• the duty cycle is forced down.
• the duty cycle is allowed to increase.
• the difference between the two preset levels determines the regulation - this is the same as the hysterisis used on a switched regulator. The difference is that the output does not switch off but reduces only to the amount required to fall below the lower preset and then increases to the upper preset.
• the duty cycle, and therefore output voltage, dithers around the average value of the two preset limits.
• the duty cycle is forced down and, if the voltage does not fall below the lower limit, the duty cycle continues to decrease to zero and will not be allowed to increase again until the voltage has fallen below its lower preset limit.
• the other regulator(s) then has control of the output voltage and the combined regulators will then function as an incremental regulator with the possibility of either or all of them operating in the "linear" - simulating mode. The form of operation depends on the battery state, load, available charge, etc. In the provided circuit the regulator automatically functions as a "power-maximizing" regulator provided the preset voltage limit has not been exceeded and will automatically switch from one to the other depending on the output voltage.
• the photovoltaic cell thus operates in the same way as the solar panel previously described and the output therefrom is used as the varying power supply for the purpose of providing input to the circuit of the invention.
• the load is a dummy load in this case as the energy provided thereto is only used for measurement purposes and not as a useful power source.

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• 1986
  • 1986-07-11 WO PCT/AU1986/000193 patent/WO1987000312A1/fr not_active Application Discontinuation
  • 1986-07-11 EP EP19860904048 patent/EP0231211A4/fr not_active Withdrawn

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