EP0221922A1 - Cellule d'additionneur complet a mos complementaire, notamment pour ensembles de multiplicateurs - Google Patents

Cellule d'additionneur complet a mos complementaire, notamment pour ensembles de multiplicateurs

Info

Publication number
EP0221922A1
EP0221922A1 EP19860902588 EP86902588A EP0221922A1 EP 0221922 A1 EP0221922 A1 EP 0221922A1 EP 19860902588 EP19860902588 EP 19860902588 EP 86902588 A EP86902588 A EP 86902588A EP 0221922 A1 EP0221922 A1 EP 0221922A1
Authority
EP
European Patent Office
Prior art keywords
output
multiplexer
input
gate
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP19860902588
Other languages
German (de)
English (en)
Inventor
Robert L. Adair
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Analog Devices Inc
Original Assignee
Analog Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Analog Devices Inc filed Critical Analog Devices Inc
Publication of EP0221922A1 publication Critical patent/EP0221922A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
    • H03K19/215—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical using field-effect transistors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/48—Indexing scheme relating to groups G06F7/48 - G06F7/575
    • G06F2207/4802—Special implementations
    • G06F2207/4812—Multiplexers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/48—Indexing scheme relating to groups G06F7/48 - G06F7/575
    • G06F2207/4802—Special implementations
    • G06F2207/4816—Pass transistors

Definitions

  • CMOS full adder cell e.g. for multiplier array
  • This invention relates to the field of digital signal processing and, more particularly, to a fast full adder cell for use in integrated circuit multiplier arrays.
  • Digital multipliers In digital computing and signal processing applications, multiplication is an important and frequently employed operation.
  • Digital multipliers generally include certain hardware elements and an algorithm controlling their use.
  • the hardware generally comprises an array of adders, which comprise the basic operational cells of each multiplier.
  • the full adder cell is implemented with a one-bit-wide multiplexer; this multiplexer is used to select either the output of a 2-input exclusive-OR gate or the output of a 2-input exclusive-NOR gate; the multiplexer output is presented as the sum output of the adder.
  • a second one-bit-wide mutliplexer is used for generating the carry output; this multiplexer selects between the output of a 2-input OR gate and the output of a 2-input AND gate, presenting the selected gate's output as the carry output from the cell.
  • the 2-input exclusive-OR and exclusive-NOR gates also are formed from single-bit pass transistor multiplexers, while the AND and OR gates are formed from pass transistors with a pull-up or pull-down transistor on their outputs, as appropriate.
  • Fig. 1 is a schematic diagram of a sum-generating circuit according to the present invention, without showing the construction details of the exclusive-OR and exclusive-NOR gates;
  • Fig. 2 is a schematic diagram of a carry-generating circuit according to the present invention, without showing the construction details of the AND and OR gates;
  • Fig. 3 is a schematic circuit diagram of the exclusive-OR gate of Fig. 1 constructed from pass transistors;
  • Fig. 4 is a schematic circuit diagram of the exclusive- NOR gate of Fig. 1 constructed from pass transistors;
  • Fig. 5 is a schematic circuit diagram of the AND gate of Fig. 2 constructed from a pass transistor and a pull-up transistor;
  • Fig. 6 is a schematic circuit diagram of the OR gate of Fig. 2 constructed from a pass transistor and a pull-up transistor;
  • Fig. 7 is a schematic diagram showing the circuit which results when the circuits of Figs. 3 and 4 are used in the circuit of Fig. 1 to implement its exclusive-OR and exclusive-NOR.gates;
  • Fig. 8 is a schematic diagram showing the circuit which results when the circuits of Figs. 5 and 6 are used in ahe circuit of Fig. 2 to implement its AND and OR gates;
  • Fig. 9 is a part-schematic circuit/part-block diagram showing how the inputs of the full adder cell are developed.
  • Fig. 10 is a schematic-circuit diagram for a sum- generating circuit in which two of the pass transistors of Fig. 7 have been replaced by an inverter.
  • the sum circuit 10 comprises a multiplexer (enclosed in dotted lines 11) formed from a pair of pass transistors 12 and 14, an exclusive-OR gate 16 and an exclusive-NOR gate 18. Gates 16 and 18 both receive the same inputs, labelled "B" and "C".
  • the B and C signals are two of the three possible addends, the third being the S signal.
  • the B signal is the encoded multiplication factor (i.e. the multiplier), generated as described below, and the C input is the carry output from the previous adder cell.
  • exclusive-OR gate 16 is connected via line 17 to the first signal input of multiplexer 11 (i.e., the signal input of pass transistor 12) and the output of exclusive-NOR gate 18 is connected via line 19 to the second signal input of the multiplexer 11 (i.e., the signal input of pass transistor 14).
  • the outputs of both pass transistors are wired together to provide the multiplexer output on line 15.
  • the signal on line 15 is the sum output of the cell, labelled SUM.
  • the multiplexer 11 is controlled by a complementary pair of signals, S and S__BAR, applied to the control inputs of the multiplexer (i.e., the gates of pass transistors 12 and 14) in opposite phase - i.e., so that multiplexer 12 is "on” while multiplexer 14 is “off", and vice versa.
  • S and S_BAR signals are applied as indicated in Fig. 1 (i.e., the noninverted form of the S signal is applied to the gate of the P-type device in pass transistor 12 and to the gate of the N-type device in pass transistor 14, while the inverted form of the S signal is applied to the other gates of those pass transistors).
  • the S control signal represents the sum from a previous adder in the array. (The notation "__BAR" when added to a signal name herein is used to signify the logical complement, or inverted state, of that signal.)
  • the carry circuit of Fig. 2 is topologically identical to the carry circuit of Fig. 1, except that exclusive-OR gate 16 has been replaced by an AND gate 22 and exclusive-NOR gate 18 has been replaced by an OR gate 24; the outputs of AND gate 22 and OR gate 24 are supplied on line 23 and line 25, respectively, to the inputs of multiplexer 21 (i.e., pass transistors 26 and 28). The outputs of pass transistors 26 and 28 are wired together, providing the output of multiplexer 21 on line 29.
  • the signal on line 29 is the carry output of the cell and is therefore labelled CARRY.
  • Figs. 3 and 4 show, respectively, how gate 16 may be made from two pass transistors 32A and 32B, and how gate 18 may be made from two pass transistors 34A and 34B.
  • Figs. 5 and 6 show, respectively, how each of gates 22 and 24 may be made from a single pass transistor and a single field effect transistor each.
  • AND gate 22 these are, respectively, pass transistor 36 and FET 38, while in the case of OR gate 24, they are, respectively, pass transistor 42 and FET 44.
  • the carry-in signals (“C") and, for the sum output, the encoded multiplier (“B”) must be supplied in both inverted and non-inverted states; the two additional inverters which are needed are not shown.
  • a pass transistor is turned “on” when the signal applied to the top gate is a logical 1 and the signal applied to its bottom gate is a logical 0.
  • the output of gate 16 is the B_BAR signal.
  • pass transistor 32B is turned on and pass transistor 32A is turned off, the output of gate 16 is the B input signal.
  • the resulting truth table is that of an exclusive-OR function.
  • the circuit of Fig. 4 is identical to that of Fig. 3 except that its B and B_BAR inputs have been interchanged.
  • the output of the former circuit is the logical inverse of the output of the latter circuit and the Fig. 4 circuit implements an exclusive-NOR operation.
  • the output of the gate 22 is controlled by the pass transistor 36 or by the pull-down transistor (FET) 38, depending on the state of the C signal.
  • the B signal is provided to the input of pass transistor 36; the C signal is provided to its top gate and the C_BAR signal is provided to its bottom gate as well as to the gate of FET 38.
  • the output of pass transistor 36 and the drain of FET 38 are connected together to provide the ouput of gate 22.
  • the source of FET 38 is connected to ground.
  • the pass transistor 22 when the C input is 0, the pass transistor 22 is turned off (i.e., its output floats), FET 38 is turned on and it connects the output of gate circuit 22 to ground through a very low resistance, setting that output to 0 irrespective of the state of the B signal.
  • the output on line 23 is high only when both the B signal and the C signal are 1; this, of course, is the AND function.
  • the output of the gate 24 is controlled by the pass transistor 42 or by the pull-up transistor (FET) 44, depending on the state of the C signal.
  • the B signal is provided to the input of pass transistor 42; the C_BAR signal is provided to the top gate of pass transistor 42 as well as to the gate of FET 44.
  • the C signal is provided to the bottom gate of the pass transistor.
  • the output of pass transistor 42 and the drain of FET 44 are connected together to provide the output of gate 24.
  • the source of FET 44 is connected to the supply voltage, Vcc.
  • Vcc supply voltage
  • the pass transistor 42 is turned off (i.e., its putput floats), but FET 44 is turned on and connects the output on line 25 to the supply voltage through a low resistance, setting that output to a 1 irrespective of the state of the B signal.
  • the FET 44 is turned off and pass transistor 42 is turned on; this causes the output on line 25 to correspond to the B input.
  • the output on line 25 is high if at least one of the B signal or the C signal is 1; this, of course, is the OR function.
  • Figs. 7 - 9 show how these circuit blocks can be put together to provide a full adder corresponding to Figs. 1 and 2.
  • Inverters 50 and 51 have been added to drive the lines to the next full adder cell and to provide compensation for the unequal propagation times for logical 0 and logical 1, as explained more fully below.
  • the total circuit thus has 30 transistors, which compares favorably to the 28 transistors used in traditional prior art designs.
  • circuit of Fig. 10 may be substituted for the circuit of Fig. 7.
  • the stand-alone exclusive-NOR (“XNOR") circuit comprising pass transistors 34A and 34B has been replaced by an inverter 52 between the output of the exclusive-OR (“XOR”) circuit on line 17 and pass transistor 14. This is possible since the XNOR and XOR functions are complementary.
  • each full adder When used in a multiply array, each full adder receives both a sum and a carry input from full adders in the row immediately above, and a third input from so-called “Booth logic” 62, the details of which are well-known to those skilled in the art.
  • Booth logic implements the so-called “standard Booth algorithm” or, preferably, the “modified Booth Algorithm” for coding or recording the multiplier (i.e., multiplication factor).
  • Other algorithms for multiplier recording now known or hereafter to be developed, may be used, as well, as the invention is not limited for use with any particular such algorithm.
  • the standard and modified Booth algorithms are described in numerous popular texts, such as L.R. Rabiner et al, Theory and Application of Digital Signal Processing, Prentice-Hall, Inc., Englewood Cliffs, N.J. 1975, at pp. 514-524.
  • the full adder cells of the present invention be interconnected as follows: input “C” is driven by the carry-out of a preceding full adder; input “S” is driven by the sum-out of a preceding full adder; and input “B” is driven by the Booth logic.
  • input “C” is driven by the carry-out of a preceding full adder
  • input "S” is driven by the sum-out of a preceding full adder
  • input "B” is driven by the Booth logic. This preference arises from the following three considerations: (1) the characteristics of pass transistors, (2) the differences in propagation time between the sum portion and the carry portion and (3) in a multiplier array, one of the three inputs to each full adder is stable throughout the multiplication.
  • control input i.e., the signal turning the pass transistor on and off
  • the signal-passing input requires less drive capability than the signal-passing input.
  • simulation techniques demonstrate the carry portion of the full adder cell to be slightly faster than the sum portion.
  • the performance of the full adder cell is affected significantly by the amount of the capacitive load which the sum and carry signals must drive.
  • This load comprises the interconnection (metal or polysilicon) to the next row of adder cells and the gates of those cells' several pass transistors which are connected to the interconnection. Minimization of that capacitance is achieved by minimizing the interconnection length and the areas of such pass transistors.
  • a pass transistor of course, if formed of a P-type device and an N-type device; usually pass transistors are constructed such that the P-type device is twice the size of the N-type device, to allow the logic 1 and the logic 0 to propagate at equal speed.
  • both the P-type device and the N-type device may have the minimum possible width of about 4 microns. While this will cause a logical 1 to propagate relatively slowly, compensation may be provided in the inverter which follows each pair of pass transistors; that is, the inverters may be made such that their P-type and N-type devices are of approximately the same size. This allows the "slow" logical 1 out of the preceding pass transistors to be inverted about twice as fast as the faster logical 0, achieving compensation.
  • the worst case propagation delay for a 16 by 16 multiplication array according to the present invention was indicated to be about 22 nanoseconds, as compared with about 44 nanoseconds for the customary approaches.
  • real delay times may be expected to differ from these theoretical, calculated values, the ratio of the real delay times should not be much different from the ratio of the delay times in the simulation results.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Optimization (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)

Abstract

Une cellule d'additionneur complet rapide pour ensembles de multiplicateurs comprend des portes simples à 2 entrées (16, 18, 22, 24) et une paire de multiplexeurs (11, 21) formés de transistors de transfert (12, 14, 26, 28). Les portes à deux entrées (16, 18, 22, 24) peuvent elles aussi être formées de transistors de transfert et, dans le cas de portes ET et OU, d'un seul transistor additionnel à effet de champ. Dans un premier mode de réalisation, la cellule utilise un multiplexeur bit par bit (11) pour sélectionner en tant que sortie d'addition soit la sortie d'une porte OU exclusive (16) à deux entrées soit la sortie d'une porte NI exclusive (18) à deux entrées. Un deuxième multiplexeur bit par bit (21) sélectionne en tant que sortie de report de la cellule soit la sortie d'une porte OU (24) à deux entrées ou la sortie d'une porte ET (22) à deux entrées. Dans un deuxième mode de réalisation, les portes OU exclusive et NI exclusive sont elles aussi formées d'un ou deux multiplexeurs bit par bit (Fig. 3 et 4, respectivement), alors que les portes ET et OU sont formées de transistors de transfert (36, 42) ayant à leur sortie un transistor survolteur ou dévolteur (38, 44), selon le cas. Le dispositif de type P et le dispositif de type N de chaque transistor de transfert ont la moindre largeur possible. Pour compenser la propagation inégale des 1 et des 0, un inverseur suit chaque paire de transistors de transfert, les dispositifs de type P et de type N de l'inverseur étant à peu près de la même longueur.
EP19860902588 1985-05-29 1986-02-04 Cellule d'additionneur complet a mos complementaire, notamment pour ensembles de multiplicateurs Withdrawn EP0221922A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US73883085A 1985-05-29 1985-05-29
US738830 1985-05-29

Publications (1)

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EP0221922A1 true EP0221922A1 (fr) 1987-05-20

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EP (1) EP0221922A1 (fr)
WO (1) WO1986007173A1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5155387A (en) * 1989-12-28 1992-10-13 North American Philips Corp. Circuit suitable for differential multiplexers and logic gates utilizing bipolar and field-effect transistors
DE19821455C1 (de) * 1998-05-13 1999-11-25 Siemens Ag Verzögerungsoptimierter Multiplexer
US10613829B2 (en) 2018-05-17 2020-04-07 Qualcomm Incorporated Performance power optimized full adder

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4417314A (en) * 1981-07-14 1983-11-22 Rockwell International Corporation Parallel operating mode arithmetic logic unit apparatus

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO8607173A1 *

Also Published As

Publication number Publication date
WO1986007173A1 (fr) 1986-12-04

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