EP0221786B1 - Led matrix display panel - Google Patents

Abstract

LED display panel for forming a luminous journal. <??>The LEDs (11) which are arranged in a matrix are controlled via flip-flops forming a high-speed CMOS technology memory (12) able to deliver to them a current of sufficient intensity. The diodes are connected directly to the outputs of these memories and the current crossing them is determined by the supply voltage for the memories (12). <??>The memories are loaded by a shift register (13) of serial type. <IMAGE>

Description

The invention relates to a display panel with a matrix of light-emitting diodes, typically forming a luminous newspaper and it relates more particularly to such a panel which is both more economical and brighter than known analogous systems, while allowing more fast.

A conventional luminous journal consists of a matrix of light-emitting diodes, a corresponding number of memories (typically bi-stable flip-flops) interposed between said diodes and a shift register in which circulate the information representative of an image to be displayed. . This information is delivered at the rate of a clock by a control unit associated with a program memory. The control unit and the program memory are generally located in a separate box from the panel and connected to the latter by a strand of conductive wires. This arrangement is advantageous when the diode panel is intended to be placed outside and subjected to the weather. In this case, the most fragile components, contained in the control unit, can be placed in a sheltered place and more easily accessible for the modification or updating of the messages to be reproduced. Up to now, it has been quite difficult to adapt the characteristics of the memories to those of light-emitting diodes. We have therefore sought to supply the diodes through load resistors, as indicated in IEEE Electro, vol. 7, May 1982, pages 1-11, New York, US; R. Broomfield et al .: "ISO-CMOS technology in the microprocessor interface" (see page 7, figure 21), but this type of circuit has the disadvantage of power consumption in the resistors, not directly useful for the 'display. The cost price is also high, not only because of the number of resistors required, but also because of the labor cost for their wiring. Attempts have been made to supply the light-emitting diodes directly with the current delivered by the memories, but this generally results in making said memories work outside the characteristics provided by the manufacturer of these integrated circuits. Such an embodiment is, ultimately, conceivable for the display of scrolling messages, since the diodes are used only for a small part of the time. This becomes more difficult to envisage for the display of fixed messages, in particular graphics, where certain diodes can be permanently lit for relatively long time intervals, hence much more unfavorable operating conditions for the memories which supply them. .

The invention makes it possible in particular to solve this problem. The basic principle of the invention results from the search for a better adaptation between the available integrated circuits, constituting the memories and the light-emitting diodes usually used for such an application. By analyzing the characteristics of recent integrated circuits of fast CMOS technology, it has thus been found that the manufacturers of these integrated circuits designed for high-speed digital computing applications, had been led to lower the supply voltage, while admitting a higher current, so that the circuits can be driven at a higher clock frequency. One of the features of the invention is to propose a new application of this type of component, for directly supplying a light-emitting diode.

With this in mind, the invention therefore essentially relates to a display panel with a matrix of light-emitting diodes, for example of the light journal type, each diode being supplied by means of a memory, characterized in that the memories are made of fast CMOS technology, in that the diodes are directly connected to the outputs of their respective memories, and in that the supply voltage of said memories is chosen to fix the value of the current in said diodes.

Another problem solved by the invention relates to the very structure of the display panels. This involves efficiently transmitting the high-frequency clock to all circuits, despite the large dimensions of the diode array. Indeed, it is not possible to provide a clock common to all the integrated circuits. The parasitic capacities which would result therefrom would not allow the transfer of information at the chosen frequency, that is to say of the order of 2 MHz. It is therefore necessary to provide, step by step, means for amplifying or regenerating the clock signal, which can desynchronize the various circuits of the shift register. According to another aspect of the invention, means are provided for the shift register to function correctly without the clock signal being actually synchronized at all points of the register.

For this purpose, the display panel defined above is also characterized in that the stages of the shift register are arranged in groups of stages adjacent to each other, in that a means of amplification and reset in form is interposed in the clock link between any two adjacent groups and in that a delay means is interposed between the data output and the data output of these same adjacent groups.

Another particular feature of the invention consists in supplying the display panel with a clock of reduced frequency and in regenerating the high frequency clock in the display panel itself, which makes it possible to have a length of conductive cable. more important between the control unit and the high-frequency clock proper, and the display panel.

• la figure 1 illustre partiellement un schéma de principe de l'ensemble des mémoires et du registre à décalage associé aux diodes électroluminescentes;
• la figure 2 est un schéma de branchement possible entre une diode électroluminescente et sa mémoire;
• la figure 3 est une variante de branchement;
• la figure 4 présente le schéma d'un circuit réducteur de fréquence d'horloge; et
• la figure 5 représente le schéma d'un circuit multiplicateur de fréquence d'horloge

The invention will appear more clearly in the light of the description which follows, given solely by way of example and made with reference to the appended drawing, in which:

• FIG. 1 partially illustrates a block diagram of all of the memories and of the shift register associated with the light-emitting diodes;
• Figure 2 is a possible connection diagram between a light emitting diode and its memory;
• Figure 3 is an alternative connection;
• FIG. 4 shows the diagram of a clock frequency reducing circuit; and
• FIG. 5 represents the diagram of a clock frequency multiplier circuit

Referring to the drawing, there is shown a part of a display panel of light-emitting diodes 11, respectively connected to memories 12 produced in rapid CMOS technology, today marketed under the reference HCMOS by most semiconductor manufacturers. . Each memory is composed of a bi-stable flip-flop and, according to the invention, the corresponding diode 11 is directly connected to its output, that is to say in particular without series resistance. There are two possibilities of connecting the diode relative to the flip-flop, either by using the transistor of channel N, the diode being connected between the output of the memory and the mass (fig. 2), or by using the transistor of the channel P, the diode being connected, this time, to the power supply terminal (fig. 3).

Referring again to FIG. 1, we see that the memories 12 are connected to be loaded by the outputs of a shift register of the serial type, that is to say with serial data inputs and parallel outputs, the latter being connected to the inputs for loading the memories 12. The progression of the information in the register takes place at the rate of a high-frequency clock, applied by a clock link 14. The transfer of information from the inputs to the outputs of the memories 12 is controlled when the information train corresponding to a complete image has reached the last stage of the shift register 13. At this time, a control signal is applied on a loading BUS 15 common to all the memories 12. In practice, the control system for the diode array 11 will advantageously be produced by cascading a suitable number of integrated circuits of the 74 HC 4094 B type incorporating into the times of stages 13a of the shift register and a corresponding number (eight in the example) of memories 12 connected to the outputs of these stages of register. The accessible outputs of said memories 12 are connected directly to light-emitting diodes 11, respectively; according to the assembly of Figure 2 or that of Figure 3. The output of the last stage of the register of a given integrated circuit is connected to the input of the first stage of another integrated circuit of the same type, located nearby. The current of each flip-flop forming memory 12 is sufficient to optimally supply the light-emitting diode, which typically requires a current of the order of 25 mA. Indeed, this integrated circuit admits to being supplied with a lower voltage than the other MOS type circuits and this can vary within fairly wide limits. This feature is therefore used to adjust or determine the current flowing in the diodes, by choosing the supply voltage accordingly. Typically, with the type of integrated circuit mentioned above, the voltage is chosen around 4 V, to obtain a current of the order of 25 mA in each diode. For this current value, the voltage across the diode is close to 1.8 V. The power dissipated in each memory is therefore of the order of 0.062 W. As each integrated circuit contains eight memories, the maximum power dissipated by said integrated circuit (corresponding to eight lit diodes) is 0.5 W, which corresponds to the power admissible by this type of integrated circuit. If we assume a diode utilization rate of around 35%, the average power dissipated by each circuit is therefore in fact only 0.175 W.

According to another important characteristic of the invention, the stages 13a of the shift register are arranged in groups of stages adjacent to each other (that is to say topologically neighboring on the display panel) and a means d amplification and fitness 18 is interposed in the clock link between any two such adjacent groups, while a delay means 19 is interposed between the data output and data input from these same adjacent groups. Thus, the high-frequency clock signal can still be used from one end to the other of the display panel, despite the parasitic capacities distributed over the entire distance, by means 18 arranged gradually. The resulting desynchronization is inconsequential thanks to the delay brought simultaneously in the transfer of information, from group to group. The delay between two groups must be greater than the delay of the clock between these same groups. In practice, each amplifier can be produced by two cascade inverters, for example available in integrated circuits of the same category, bearing the reference 74 HCU 04. Self-timer means 19 are also available in each integrated circuit of type 74 HC 4094 B containing registers and memories. In the example of FIG. 1, an amplifier 18 and a delay means 19 associated with each integrated circuit, that is to say for eight diodes, have been represented for the sake of simplification. In fact, it will be possible to "space" them much more, the number of stages in each group possibly being between ten and forty and preferably close to thirty. Finally, as mentioned above, provision is made to transmit the clock signal at a reduced frequency in the strand of conductive wires connecting the display panel and its control unit containing the high-frequency clock generator, not shown. Thus, the device of FIG. 4 connected to the output of the high-frequency clock generator, therefore at a distance from the panel, supplies a signal whose frequency is reduced by half. It consists of a flip-flop 20 looped back to its input by an inverter 21 whose output signal is amplified in 22 before being applied to the clock line. The device in Figure 5 is a frequency multiplier designed to double the frequency of the signal it receives. It consists of an amplifier 24 distributing its output signal to two monostables 25, 26, mounted in parallel and phase shifted by an inverter 27. The outputs of the two monostables are connected to the two inputs of an OR gate 28 whose output is output the original frequency.

The system which has just been described allows the display of successive images at very high speed, up to a thousand images per second. These performances can be taken advantage of for the continuous display of a fixed image comprising lit diodes with different light levels, obtained by rapid and successive switching on and off of these diodes. For example, for a minimum frequency of twenty images per second, one can obtain up to fifty different light levels.

Claims (6)

1. An electroluminiscent diode display matrix panel (11), as for example of the light information panel type, each diode being powered through a memory (12), characterised by the fact that the memories are of the rapid CMOS technology type, that the diodes (11) are directly connected to the outputs of their respective memories and that the power supply voltage of the aforesaid memories is selected to establish the value of the current through the aforesaid diodes.
2. A display panel according to claim 1, characterised by the fact that the aforesaid memories (12) are those of HCMOS integrated circuits, preferably those of 74 HC 4094 B circuits.
3. A display panel according to claims 1 or 2, characterised by the fact that each memory (12) is connected to a corresponding stage of series type shift register (13), to be loaded thereby, said register receiving for every image a succession of data generated by a control unit operated at the rythm of a clock connected to the aforesaid register by a clock link (14), a loading link (15) being common to all the memories.
4. A display panel according to claim 3, characterised by the fact that the shift register stages (13a) are serially arranged by groups of stages, adjacent to each other, the clock link being connected to each group, the data output of a group being linked to the data input of the next adjacent group, that a restore-amplification means (18) is inserted in the clock link between any two adjacent groups, and that a delay means (19) is inserted between each data output of a group and the data input of the following adjacent group.
5. A display panel according to claim 4, characterised by the fact that the number of stages (13a) of each group is between ten and forty inclusive, and approximately thirty for preference.
6. A display panel according to claims 3 to 5, in which the aforementioned clock is located away from the register, the memory and the aforementioned matrix and linked to the register by a connection of a given length, characterised that the aforementioned clock is connected to a frequency reducing circuit (20-22) to emit a clock signal of reduced frequency on the aforementioned clock link, and that the shift register (13) is linked to a frequency multiplier (24-28) receiving the aforementioned reduced frequency clock signal and capable of regenerating a clock signal of unreduced frequency.

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