EP0216851A1 - Complementary fet delay/logic cell - Google Patents
Complementary fet delay/logic cellInfo
- Publication number
- EP0216851A1 EP0216851A1 EP86902099A EP86902099A EP0216851A1 EP 0216851 A1 EP0216851 A1 EP 0216851A1 EP 86902099 A EP86902099 A EP 86902099A EP 86902099 A EP86902099 A EP 86902099A EP 0216851 A1 EP0216851 A1 EP 0216851A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- voltage
- transistor
- integrated circuit
- inverter
- field effect
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/096—Synchronous circuits, i.e. using clock signals
- H03K19/0963—Synchronous circuits, i.e. using clock signals using transistors of complementary type
Definitions
- the present invention relates to a circuit implemented in complementary field effect transistor technology that is suitable for performing logical operations and delay functions.
- CMOS complementary field effect transistor
- a circuit comprising one or more field effect pass transistors of a single conductivity type connected to the input of a complementary inverter.
- a signal voltage of a given magnitude is applied to the gates of the transistors.
- a lower voltage is applied across the sources of the complementary transistors in the inverter.
- the lower voltage is obtained from a field effect transistor having its gate connected to its drain, thereby obtaining a threshold voltage drop.
- FIG. 1 shows a prior art NMOS logic circuit.
- FIG. 2 shows a prior art NMOS logic circuit using depletion mode transistors.
- FIG. 3 shows a prior art shift register cell.
- FIG. 4 shows a shift register cell implemented according to the present technique.
- FIG. 5 shows a transmission gate logic function implemented by one embodiment of the present technique.
- FIG. 6 shows logic function implemented by an alternate embodiment of the present technique.
- FIG. 7 shows an embodiment of the present technique utilizing p-channel pass transistors.
- FIG. 8 shows typical d-c switching characteristics of a complementary inverter at two voltage supply level.
- Shift registers that comprise a multiplicity of delay stages, or cells, are widely used for performing a variety of tasks in integrated circuits. For example, to perform a fast Fourier transform (FFT), the data is inputted into a long shift register, typically comprising over a thousand stages. The data is moved through the stages synchronously with a system clock that controls the transfer of the data from one stage to the next. Output taps can be provided at various points along the shift register. These taps provide an amount of delay of the data, as referenced to the input, that corresponds to the tap position. For example, a shift register clocked at a rate of one megahertz provides for one microsecond of delay per stage.
- FFT fast Fourier transform
- Taps spaced at 250, 500, and 750 stages from the input .then provide for delays of 250, 500, and 750 microseconds, respectively, with reference to the input.
- CMOS complementary field effect transistor
- the con iguration of FIG. 3 has been used.
- a given cell e.g., cell 1
- CMOS complementary field effect transistor
- a given cell comprise two complementary inverters M32-M33 and M36-M37. These are separated from each other, and from inverters in neighboring cells, by complementary transistors M30-M31 and M34-M35.
- the data is inputted to the input node 300 common to n-channel transistor M30 and p-channel transistor M31 , which are referred to as "pass transistors".
- a given electrode of an individual pass transistor is considered a source or a drain depends on whether a high or low voltage data signal is present on input node 300 at any given time.
- the convention used herein is that the electrode of the pass transistors connected to the input node (300) is the "source”, while the electrode connected to the inverter input node (301) is the “drain”. Normally, the sources and drains of a given field effect transistor are physically identical.
- a master clock signal, MC is applied to the gate of M30, and its complement, MC, is applied to the gate of M31.
- MC goes to a high voltage level, and MC goes low, the voltage level present at input node 300 is passed to node 301, and hence to complementary inverter transistors M32, M33. These serve to invert the data input signal, so that a high voltage input produces a low voltage output at node 302, and vice- versa.
- This inverted data signal at node 302. is applied to pass transistors M34, M35, which are clocked by a slave clock and its complement, SC and SC, respectively.
- the slave clock is delayed, typically by one-half clock period, from the master clock. Hence, the data signal appears at node 303 approximately 1 clock period later than at input node 300.
- the data signal is then again inverted by complementary inverter pair M36, M37, and applied to the next delay cell.
- this prior art technique utilizes two pass transistors, one n-channel and the other p-channel, per inverter. This is because a n-channel transistor is best for passing a low voltage level to the inverter (i.e., to node 301), and a p-channel transistor is best for passing a high voltage level. That is, there is always one of the pass transistors operating in the saturation region, which provides that the associated inverter transistors are turned hard "on” or “off", except during the transition from one level to another. This is desirable to minimize power consumption of the inverter.
- this technique requires the generation and routing around the shift register of the four clock signals, MC, MC, SC, and S ⁇ C. This is a considerable complication of the shift register design, and requires significant space on an integrated circuit for the appropriate signal generators and clock signal lines.
- One design simplification known in the art is to simply eliminate one set of pass transistors (e.g., the p-channel ones), in order to simplify the layout and eliminate the need for the complement clocks ⁇ MC, S ⁇ C " ) and associated lines.
- This presents an input "1" to the next inverter of about Vdd-Vth, where Vth is the threshold of the (NMOS) pass transistor.
- Vth is the threshold of the (NMOS) pass transistor.
- the voltage reduction across the pass transistor is even greater, due to an increase in back-gate bias on the pass transistor as its input terminal ("source") goes positive due to the data signal.
- the degraded signal leaves both the NMOS and PMOS inverter transistors turned on. Hence, this results in an increase in the power consumption of the shift register.
- CMOS complementary conductivity
- transmission gate logic Another area that utilizes field effect transistors as pass elements is so-called transmission gate logic.
- the pass transistors are configured to perform logical operations on two or more logical input signals. The logical output is then provided to the complementary inverters, as before. In this manner, a building block approach to logical system design is possible.
- An advantage of this technique over certain other logic circuit techniques is a reduction in power consumption.
- CMOS complementary metal-oxide-semiconductor
- a clocked logic circuit might then be implemented as indicated in FIG. 1 , wherein three power supply voltages, 0, +5, and +12 volts were typically present. All of the transistors for the circuit shown are of the enhancement type, wherein a positive gate-to-source voltage, VGS, was required to allow conduction between the source and drain.
- VGS positive gate-to-source voltage
- the transistors were typically either diode connected (M11) or biased with a gate voltage more positive than the drain voltag.e (M14).
- An input clock signal having 5 and 0 volt levels is shown applied to the gate of M10.
- this inverter assumes the levels of about 0 to 11 volts, assuming that M11 has a threshold of 1 volt, which subtracts this amount from the 12 volt power supply level.
- This clock signal is then applied to the gate of pass transistor M12, which has a 0 to 5 volt data signal applied to its source.
- a clocked data signal having a 0 to 5 volt level appears at the drain of M12, and the gate of inverter M13.
- the output of this inverter is then 5 to 0 volts.
- FIG. 2 an illustrative circuit logically equivalent to that of FIG.1 is shown. Since load devices M21 and M24 are essentially resistive between source and drain when connected as shown, the full 5 volt power supply voltage is available to pull up the drain of inverter transistors M20 and M23. That is, there is no threshold voltage drop to subtract from the power supply voltage.
- CMOS technology essentially solved the problems noted for the prior NMOS technologies, in that a two voltage power supply could be used, and static power consumption substantially reduced.
- the freedom to chose a desired switching threshold for an inverter by simply choosing the size ratio between load and switching transistors was lost. This is because in a CMOS inverter, the conduction of both transistors is then determined primarily by their threshold voltages, since both the n-channel and p-channel devices are typically enhancement mode types. Normally, it is desired that the magnitude of the thresholds be approximately equal. However, equal threshold voltages imply that the switching threshold of complementary inverter is at one-half the power supply voltage, or about 2.5 volts for a 5 volt supply.
- CMOS complementary metal-oxide-semiconductor
- the following detailed description relates to a technique for implementing delay and/or logic functions using field effect pass transistors.
- a reduced voltage is applied across a - 1 -
- the complementary inverter as compared to the gate voltage applied to the one or more pass transistors connected to the input thereof.
- the relative reduction in the switching threshold of the inverter allows for more complete switching, and consequently a reduction in the power consumption, even with pass transistors of only a single conductivity type.
- a delay state is shown implemented according to one embodiment of the invention.
- a binary data signal havig a given voltage swing between logic levels is applied to pass transistor M40.
- a clock signal CK having a first voltage swing (e.g., 0 to 5 volts) is applied to the gate of M40.
- the data signal passes through M40 when the channel conducts in response to CK, and is applied to the input node 401 of a complementary inverter comprising p-channel transistor M42 and n-channel transistor M41.
- a n-channel transistor M43 having its gate and drains connected together provides a threshold of voltage reduction across the inverter, as compared to the voltage between the positive and negative power potentials, Vdd and Vss respectively.
- switching threshold refers to the input voltage on the complementary inverter at which the output voltage assumes one-half of the voltage across the complementary transistor pair. This latter voltage is measured at the source of the p-channel inverter transistor with reference to the source of the n-channel inverter transistor; e.g., Vdd-Vss (FIG. 3), or from node 403 to Vss (FIG. 4).
- the switching threshold then changes from 2.5 volts (curve 30) to 1.75 volts (curve 81).
- This lowering of switching threshold then provides for improved switching of the inverter when only n-type pass transistors are connected to the input.
- the input-output characteristic curves are somewhat different under actual switching conditions, due primarily to capacitive loading on the various nodes that are undergoing voltage transitions. The net effect is usually to increase the input voltage change necessary to produce a given change in the output voltage.
- a further effect relates to the difference in threshold voltages for the p- and n-channel transistors of the inverter.
- the amount of back- gate bias can also effect the threshold of a given device.
- M43 is located in a p-tub at Vss potential, then the positive voltage of its source relative to the tub causes an increase in the threshold.
- the threshold of M41 is 1.2 volts, then that of otherwise identical M43 will be higher, perhaps about 1.8 volts.
- the pass transistor (e.g., an n-channel type) may have the same threshold as the inverter transistor of the corresponding conductivity type (n-channel) for simplified processing. This threshold may be the same magnitude as that of the other conductivity type (p-channel) inverter transistor if desired. Note that when the input logic signal goes lo (0 volts), then M40 passes this level substantially unchanged to node 401, so that 41 is turned hard off, and M42 hard on. Hence, a high (3.5 volt) signal appears at output node 402.
- the 0 to 3.5 volt output voltage swing at node 402 is passed through pass transistor M44 when the CK: signal is high. If CK is at least a threshold voltage drop (of M44) greater than this 3.5 volt high signal level, then the high signal at node 402 will be passed substantially unchanged to node 404 of the second complementary inverter pair, M45-M46.
- the operation of this inverter often referred to as the "slave" portion, is then identical to that of the "master” portion previously described. Hence, the data is passed from node 400 to node 405 in synchronism with one cycle of the clock.
- the logic signal may be regenerated to the full power supply level, e.g., 0 to 5 volts, if desired. This may be accomplished by various techniques known in the art, including the signal to a complementary operating at the full (5 volt) power supply level.
- the logical signals X and X are applied to the gates of M51 and M52, respectively. These logic signals need not be in synchronism with a clock signal, but may be if desired.
- the logic signal Y is applied to the source of M51, and Y is applied to the source of M52. The result is that the logic function X exclusive or Y is generated at node 52, and hence its complement, X exclusive nor Y, appears at node 53, the output of the complementary inverter.
- an alternate embodiment of the present technique utilizes the voltage differences that ace commonly available, or proposed, in various integrated circuit operating environments.
- ECL emitter coupled logic
- the voltages are 0, -2, 0, and -5.2 volts. Note that these differences may be referenced to any level, and thus can be equivalently expressed as +2.0, 0, and -3.2 volts, etc.
- a pass transistor M60 has applied to its gate a signal X that has the binary values of 0 and -5.2 volts.
- a signal Y that typically has the values of -2 and -5.2 volts.
- the voltage on the source of p-channel transistor M62 is -2 volts, and that on the source of n-channel transistor M61 is -5.2 volts.
- the voltage across the complementary inverter pair M61-M62 is 3.2 volts, whereas the voltage swing applied to the gate of the pass transistor M60 is 5.2 volts.
- the lowering of the voltage thusly provides an even greater reduction in the switching threshold of the complementary inverter that is typically obtained with a threshold drop transistor.
- the output swing of the inverter is -2 to -5.2 volts. This output signal may be applied to succeeding logic stages, as before.
- Another suitable set of voltages for practicing the present technique uses the 0 and 5 volt levels, as discussed above, for supplying the 0 to 5 volt swing on the gates of the pass transistors. Then, a power supply voltage of about 3.3 volts, which is proposed as a new standard for M.OS integrated circuits, is applied across the complementary inverter.
- a further advantage of the foregoing voltage levels is that the logic signal may be easily regenerated to 0-5 volt levels, or 0 to -5.2 volt levels, for interfacing with circuits that operate with these standard levels. Still other voltage levels are possible.
- the voltage applied across the sources of the complementary inverter transistors is at least 10 percent less than the magnitude (voltage difference between 0 and 1 levels) of the signal applied to the gate of the pass transistor.
- p-channel pass transistor M70 has a clock signal applied to its gate, which allows it to pass a logic signal therethrough when the clock is in a low voltage state.
- the clock levels are typically 0 to 5 volts as before.
- the logic signal is thus passed to complementary inverter pair M73-M72, which has a reduced voltage thereacross due to p-channel dropping transistor M71. Note that a threshold voltage drop is obtained across M71 , producing a level of Vss + Vth at the source of M72.
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Power Engineering (AREA)
- Logic Circuits (AREA)
Abstract
Un circuit intégré comprend un transistor de transmission (M40) relié à l'entrée d'une pair d'inverseurs complémentaires. Des organes (403) délivrent à l'inverseur complémentaire une tension réduite, par rapport à la tension du signal délivré à la porte du transistor de transmission. Le seuil de commutation de l'inverseur est ainsi réduit, ce qui permet d'utiliser avantageusement un transistor de transmission du type à conductivité simple. Dans un mode de réalisation, la tension réduite est obtenue à l'aide d'un transistor à effet de champ du type à amélioration relié par une diode, ce qui produit une chute de tension de seuil. Dans une variante, on utilise des organes délivrant trois tensions d'alimentation. Un étage de retard pour un registre à décalage peut être implémenté avantageusement par la présente technique, de même que des circuits logiques à porte de transmission.An integrated circuit includes a transmission transistor (M40) connected to the input of a pair of complementary inverters. Organs (403) deliver a reduced voltage to the inverter compared to the voltage of the signal delivered to the gate of the transmission transistor. The switching threshold of the inverter is thus reduced, which advantageously makes it possible to use a transmission transistor of the simple conductivity type. In one embodiment, the reduced voltage is obtained using an enhancement type field effect transistor connected by a diode, which produces a threshold voltage drop. In a variant, organs are used delivering three supply voltages. A delay stage for a shift register can be advantageously implemented by the present technique, as well as logic circuits with transmission gate.
Description
Claims
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US71635785A | 1985-03-26 | 1985-03-26 | |
US716357 | 1985-03-26 |
Publications (1)
Publication Number | Publication Date |
---|---|
EP0216851A1 true EP0216851A1 (en) | 1987-04-08 |
Family
ID=24877700
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP86902099A Withdrawn EP0216851A1 (en) | 1985-03-26 | 1986-02-25 | Complementary fet delay/logic cell |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP0216851A1 (en) |
JP (1) | JPS62502370A (en) |
KR (1) | KR880700547A (en) |
WO (1) | WO1986005935A1 (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
NL8801119A (en) * | 1988-04-29 | 1989-11-16 | Philips Nv | LOGIC INTEGRATED SWITCHING WITH LOW THRESHOLD TRANSMISSION GATES. |
US6744082B1 (en) | 2000-05-30 | 2004-06-01 | Micron Technology, Inc. | Static pass transistor logic with transistors with multiple vertical gates |
JP2013084333A (en) | 2011-09-28 | 2013-05-09 | Semiconductor Energy Lab Co Ltd | Shift register circuit |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3675144A (en) * | 1969-09-04 | 1972-07-04 | Rca Corp | Transmission gate and biasing circuits |
JPS5738996B2 (en) * | 1973-03-20 | 1982-08-18 | ||
JPS5318377A (en) * | 1976-08-03 | 1978-02-20 | Toshiba Corp | Logical operation circuit |
-
1986
- 1986-02-25 JP JP61501656A patent/JPS62502370A/en active Pending
- 1986-02-25 WO PCT/US1986/000412 patent/WO1986005935A1/en not_active Application Discontinuation
- 1986-02-25 EP EP86902099A patent/EP0216851A1/en not_active Withdrawn
- 1986-02-25 KR KR860700834A patent/KR880700547A/en not_active Application Discontinuation
Non-Patent Citations (1)
Title |
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See references of WO8605935A1 * |
Also Published As
Publication number | Publication date |
---|---|
JPS62502370A (en) | 1987-09-10 |
KR880700547A (en) | 1988-03-15 |
WO1986005935A1 (en) | 1986-10-09 |
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Inventor name: KRAKOW, WILLIAM, TOMPKINS Inventor name: JOSEPH, SAUL, JOSHUA Inventor name: PEDERSEN, RICHARD, ALAN Inventor name: DIMYAN, MAGID, YOUSRI |