EP0202536A2 - Signal processing circuit for a color video printer - Google Patents
Signal processing circuit for a color video printer Download PDFInfo
- Publication number
- EP0202536A2 EP0202536A2 EP86106191A EP86106191A EP0202536A2 EP 0202536 A2 EP0202536 A2 EP 0202536A2 EP 86106191 A EP86106191 A EP 86106191A EP 86106191 A EP86106191 A EP 86106191A EP 0202536 A2 EP0202536 A2 EP 0202536A2
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- European Patent Office
- Prior art keywords
- data
- signal
- color
- line
- memory
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
- H04N1/46—Colour picture communication systems
- H04N1/56—Processing of colour picture signals
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
- H04N1/46—Colour picture communication systems
- H04N1/64—Systems for the transmission or the storage of the colour picture signal; Details therefor, e.g. coding or decoding means therefor
Definitions
- the present invention relates to a signal processing circuit for a color video printer which depicts a color print close in quality to a photograph on a printing paper on the basis of a color video signal.
- a video signal of one frame is disjoined into R (red), G (green) and B (blue) signals which are the components of a color signal or into Cy (cyan), Ye (yellow) and Mg (magenta) signals which correspond to the color components of a coating material.
- the resulting signals are respectively converted into digital signals, which are once stored in dedicated semiconductor frame memories.
- the respective color signals are read out and printed in a predetermined order.
- the frame memories and analog-to-digital converters (hereinbelow, termed A/D converters) for converting the color signals are driven at an identical clock frequency. Therefore, all the video signals can be uniformly stored in the frame memories within the frame period thereof (33 msec, in the NTSC format, and 40 msec. in the PAL format).
- each of the prior-art video printers requires the A/D converters and the frame memories for the respective color signals, the circuit arrangement thereof becomes complicated. It also has a problem in the aspect of cost because a . large number of RAMs (random access memories) are needed as the frame memories, and the A/D converters are needed in the number of three.
- An object of the present invention is to reduce the memory capacity of memory means for storing video signals.
- Another object of the present invention is to provide a signal processing circuit for a video printer which has a simple circuit arrangement.
- the color video printer of the present invention comprises a first memory for storing the first color signal which requires the largest amount of information among the three color signals of a color video signal, and a second memory for storing the remaining second and third color signals.
- the color signal to be stored in the second memory is input at a sampling rate lower than that of the color signal to be stored in the first memory.
- the color video printer further comprises an interpolation circuit by which the color signal stored in the second memory is interpolated to reproduce data.
- Fig. la is a block diagram showing an embodiment of a signal processing circuit for a video printer according to the present invention.
- the signal processing circuit of the video printer in this embodiment is constructed of a signal input portion 1 which is supplied with R, G and B signals, an A/D conversion portion 2 which digitizes the color signals, a memory portion 3 which stores the respective digital color signals, a digital processing portion 4 which processes and selects respective signals read out of the memory portion 3, a signal conversion portion 5 which converts color signals from the digital - processing portion 4 into signals required for printing and supplies the latter to a head assembly 6, and a system controller 7 which controls the above blocks.
- the signal input portion 1 consists of an R-signal input terminal 101 to which the R signal is input, a G-signal input terminal 102 to which the G signal is input, and a B-signal input terminal 103 to which the B signal is input.
- the A/D conversion portion 2 is constructed of A/D converters 201, 202 and 203.
- the memory portion 3 consists of a frame memory 302 which stores the G signal, a frame memory 303 which stores the R signal and the B signal, a synthesis switch 301 by which the signals to be stored in the frame memory 303 are switched, and a memory controller 304 which controls the synthesis switch 301, the frame memories 302, 303, the A/D converters 201, 202, 203, and a digital interpolation circuit 401.
- the digital processing portion 4 is constructed of the digital data interpolation circuit (hereinbelow, termed "digital interpolation circuit) 401 which synthesizes the R signal and B signal on the basis of the signals from the frame memory 303 of the memory portion 3, and a signal selector 402 by which the R signal or B signal from the digital interpolation circuit 401 and the G signal from the frame memory 302 are output in the order of printing.
- digital interpolation circuit hereinbelow, termed "digital interpolation circuit” 401 which synthesizes the R signal and B signal on the basis of the signals from the frame memory 303 of the memory portion 3, and a signal selector 402 by which the R signal or B signal from the digital interpolation circuit 401 and the G signal from the frame memory 302 are output in the order of printing.
- the signal conversion portion 5 consists of a one-line memory 501, a pulse generator 502 and a half-tone controller 503.
- the pulse generator 502 converts data stored in the one-line memory 501, into a signal of pulse width corresponding to a half-tone control signal from the half-tone controller 503 and supplies the latter to the head assembly 6.
- the G signal, R signal and B signal are respectively input to the input terminals 101, 102 and 103 of the signal input portion 1, and they are supplied to the A/D conversion portion 2.
- these color signals are converted into the digital signals of, e.g., 6 bits at the same timing by the A/D converters 201, 202 and 203 which are controlled by the memory controller 304 of the memory portion 3, whereupon the digital signals are supplied to the memory portion 3.
- the G signal digitized by the A/D converter 201 hereinbelow, termed "digital G-signal E DG " is immediately written into the frame memory 302.
- the R signal digitized by the A/D converter 202 (hereinbelow, termed “digital R-signal E DR ”) and the B signal digitized by the A/D converter 203 (hereinbelow, termed “digital B-signal E DB ”) are written into the common frame memory 303 through the synthesis switch 301.
- E Y denote the intensity of a luminance signal
- E R' EG and E B denote the intensities of the R, G and B color signals respectively
- the luminance signal E is obtained by mixing 30% of the R color signal E R , 59% of the G color signal and 11% of the B color signal.
- the amount of information of the G color signal EG necessary for reproducing the luminance signal Ey is expressed by 1 (one)
- the amount of information of the R color signal E R may be about 1/2
- that of the B color signal E B may be as small as about 1/5.
- the G color signal EG is A/D-converted at a sampling frequency f G so as to store the digital signal in the memory 302
- the R or B color signal E R or E B is A/D-converted at a sampling frequency 1 ⁇ 2 of f G so as to store the digital signal in the frame memory 303.
- the A/D converters 201, 202 and 203 A/D-converts the G, R and B color signals E G , E R and E B supplied from the corresponding terminals 101, 102 and 103 at the identical frequency fG, respectively. Since the resulting digital R signal E DR and digital B signal E DB are alternately sampled by the synthesis switch 301 and are then written into the frame memory 303, the R and B color signals are, in effect, A/D-converted at the frequency 1 ⁇ 2 f G .
- analog R color signal E R and B signal E B may well be alternately input to a common A/D converter as shown in Fig. lb.
- the input terminals 102 and 103 are connected to the input terminals of a synthesis switch 305.
- the output end of the synthesis switch 305 is connected to the input end of the common A/D converter 204, the output end of which is connected to the frame memory 303.
- the digital R signal E DR and digital B signal E DB are alternately stored in the frame memory 303. Also in the circuit shown in . Fig. lb, the R color signal E R of B color signal E B is sampled at the frequency equal to half of that of the G color signal E G as in the circuit shown in Fig. lA.
- Fig. 2a shows data items which are to be stored in the frame memory 303.
- ® indicates the digital R signal E DR
- B the digital B signal E DB .
- the digital R signal E DR and the digital B signal E DB are stored dot-sequentially.
- the signal in which the digital R signal E DR and the digital B signal E DB appear dot-sequentially is called "R/B signal”.
- the amount of information of each of the digital R and B signals E DR , E DB which constitute the R/B signal is 1 ⁇ 2 of that of the digital G signal E DG . Since, however, the sampling points of the R/B signal and those of the digital G signal are equal in number, the memory capacity of the frame memory 303 for storing the R/B signal is equal to that of the frame memory 302 for storing the digital G signal EDGe
- the embodiment reduces the memory capacity of the memory portion to 2/3 times as compared with the prior art in which the frame memories are provided for the respective digital color signals.
- Either of the digital R and B signals is extracted from the R/B signal supplied to the digital interpolation circuit 401.
- the digital R signal E DR extracted from the R/B by the digital interpolation circuit 401 is shown in Fig. 2b, and the digital B signal E DB is shown in F ig. 2c.
- the signals (hereinbelow, termed "picture elements") of sampling points (hereinbelow, termed “dots”) are denoted by ® and B, and the dots (hereinbelow, termed "lacking parts") where the picture elements are missed by the synthesis switch 301 are denoted . by marks x.
- the digital R and G signals E DR and E DB extracted from the R/B signal are respectively such that the picture elements ® and the lacking parts x are alternately arrayed and that the picture elements B and the lacking parts x are alternately arrayed.
- the digital interpolation circuit 401 interpolates the signals of the lacking parts x by the use of the signals of the dots of the actually existing picture elements ® and B, thereby to form the digital R and B signals E DR and E DB whose information quantities are increased.
- the signal selector 402 selects the digital G signal EDG from the frame memory 302 and the digital R signal E DR or B signal E DB from the digital interpolation circuit 401 in succession in the order of printing and supplies them to the signal conversion portion 5.
- the digital G signal E DG is selected, and the signals thereof corresponding to one frame are supplied to the signal conversion portion 5.
- the output signal of the digital interpolation circuit 401 is selected..
- this circuit 401 extracts the digital R signal E DR from the R/B signal in order to first print red.
- the digital R signal E DR extracted and subjected to the interpolation processing is supplied to the signal conversion portion 5 by the signal selector 402.
- the digital interpolation circuit 401 extracts the digital B signal E DB from the R/B signal.
- the extracted and interpolated digital R signal E DR is supplied to the signal conversion portion 5.
- Such selecting operations of the signal selector 402 are performed under the control of the system controller 7.
- the signals of one line from the digital color signal E DG , E DG or E DB input from the signal selector 402 are held in the line memory 501.
- all the picture elements held in the line memory 501 are simultaneously converted into gradation pulses conforming to the respective information contents by means of the pulse generator 502.
- the gradation pulses are supplied to the head assembly 6 to effect the printing.
- the signals corresponding to one line consist of signals which correspond to a column of picture elements arrayed in a direction perpendicular to the horizontal scanning direction of a television screen.
- the gradation pulses obtained by converting the signals of the picture elements of a line signal are simultaneously applied to the respective heads 6a, 6b, Vietnamese of the head assembly 6 which are arranged in the vertical direction (as viewed on the drawing) of printing paper P, whereby the information is printed on the printing paper P.
- the moving direction of the head assembly 6 relative to the printing paper P is as indicated by an arrow.
- the digital color signals of one line are held in the line memory 501 every frame of the applied digital color signal E DG' E DR or E DB .
- the head assembly 6 prints line by line rightwards from the left end of the printing paper P as it moves relative to the printing paper P.
- the head assembly 6 first prints the green image over the whole area of the printing paper P on the basis of the G signal E DG , subsequently prints the red image on the basis of the R signal E DR and further prints . the blue image on the basis of the B signal E DB , thereby to print one video image on the printing paper P.
- the above printing order is appointed by the half-tone controller 503 under the control of the system controller 7 shown in Fig. la and Fig. lb.
- color signals which are actually supplied for the printing are cyan (Cy), yellow (Ye) and magenta (Mg) signals
- the R, G and B signals have been used for the description.
- the Cy, Ye and Mg signals are obtained by converting the R, G and B signals, and the conversion may be executed in the digital processing portion 4 by way of example.
- color signals to be applied to the input portion 1 may be the Cy, Ye and Mg signals.
- the digital R signal E DR and the digital B signal E DB are stored in the identical memory.303, the memory capacity of the memory portion 3 is reduced. Although the amounts of information of the digital R signal E DR and B signal E DB decrease on account of the synthesis switch 301, the lacking information contents are supplemented by the digital interpolation circuit 401. Therefore, the degration of the picture quality of a printed picture can be prevented.
- Fig. 4 is a block diagram showing one practicable example of the digital interpolation circuit 401.
- This digital interpolation circuit 401 consists of a signal discriminator 8, a line memory 9, a shift register group 10 which is constructed of shift registers 110 and 111, a mean value circuit 11, a latch circuit 12, switches 13, 14 and 15, an address counter 16, and a pulse generator 17.
- the R/B signal from the frame memory 303 (Fig. la or 1b) is supplied to the signal discriminator 8, and either digital color signal E DR or E DB is extracted.
- E DR digital color signal
- signals corresponding to one line of the digital R signal E DR are stored in the line memory 9.
- This digital R signal for one line (namely, the line signal) E DR is stored in the line memory 9 in such a manner that, as shown in Fig. 5a, data items corresponding to picture elements ® and data items corresponding to lacking parts are alternately arrayed in the order of , , , ' , ......
- one line be composed of 512 picture elements and that be the picture element at the uppermost part of a frame, while be the part where the picture element at the lowermost part is missing.
- This digital interpolation circuit 401 carries out the data interpolation on the basis of an interpolating method to be stated below.
- the mean value of the picture element data of the upper and lower picture elements is used as the interpolation data of the lacking part x 2n .
- the interpolation based on this operation is executed for all the lacking parts x: This interpolation is not applicable to the last lacking part .
- the interpolation data C 512 therefor the picture element- data R 511 of the picture element located above is used. That is, the following operation is executed:
- the digital R signal E DR for one line becomes as shown in Fig. 5b.
- the picture element data R 2n+1 and the data C 2n of the lacking part x 2n are read out from the line memory 9 successively in a downward sequence shown in F ig. 5a, in accordance with address signals from the address counter 16 which is operated by the clock of the memory controller 304 (Fig. la or lb).
- the address signals produced from the address counter 16 are also supplied to the pulse generator 17.
- the pulse generator 17 generates switching pulses for switching the switches 13, 14 and 15 in accordance with the address values of the address signals from the address counter 16.
- the switch 13 When transferring data to the shift register 110, the switch 13 is thrown to the contact c side thereof, so that the picture element data R 2n+1 and the lacking part data x 2n from the line memory 9 are transferred toward the shift registers 110 and 111 through the switch 13 in synchronism with the clock from the memory controller 304.
- the switch 14 When the output M 1 of the shift register 111 is the picture element data owing to the transfer, the switch 14 is thrown to the contact a side thereof by the switching pulse from the pulse generator 17, and this picture element data item R 2n+1 is supplied to the signal selector 402 (Fig. la or lb) through the switch 14.
- This interpolation data item C 2n is formed as follows:
- the latch circuit 12 latches data D 2n-2 one clock time before the mean value circuit 11 delivers the data D 2n-1 . Accordingly, the data of the output M A of the latch circuit 12 is:
- the data of the output M 1 of the shift register 111 be D 2n-1' while the output M 2 and input M 3 of the shift register 110 be D 2n and D 2n+l respectively.
- the odd-numbered data D 2n-1 of the output M 1 of the shift register 111 is the picture element data and therefore requires no interpolation.
- the swtich 14 is thrown to the contact a side, and this data item D 2n-1 passes through the switch 14 to be fed into the signal selector 402 (Fig. la or lb).
- the latch circuit 12 is continually supplied with the output M B of the mean value circuit 11 for the picture element data items: through the switch 15 which is thrown on the contact e side thereof.
- the latch circuit 12 latches the aforementioned data D 2n of the output M B of the mean value circuit 11. Subsequently, when the shift register 111 is fed with the data D 2n of the output M 2 of the shift register 110 and this shift register 110 is fed with the data D 2n-1 at the input M 3 thereof, the output M 1 of the shift register 111 is the lacking part data x 2n , and hence, the switch 14 is changed-over to the contact b side. Therefore, the data D 2n of the output M A of the latch circuit 12 is fed into the signal selector 402 through the switch 14.
- this latch cir- cu it 12 latches the aforementioned data D 2n+1 of the output M B of the mean value circuit 11.
- the shift register 111 is fed with the data D 2n+1 of the output M 2 of the shift register 110, and this shift register l10 is fed with the data D 2n+2 of its input M 3 .
- the input M 3 of the shift register l10 becomes data D2n+3, and the switch 14 is thrown to the contact a side.
- the odd-numbered dots in one line have been the picture elements, and the even-numbered dots have been the lacking parts as shown in Fig. 5a.
- the switch 14 is thrown to the a side when the output M 1 of the shift register 111 is any of even-numbered data items D 2m-2' D 2m' Vietnamese, and it is thrown to the b side when the output M 1 is any of odd-numbered data items D 2m-1 , D 2m+1 , «
- the other operations are similar to those in the foregoing.
- the data of the output M 1 of the shift register 111 is D 509' and this is supplied to the signal selector 402 (Fig. la or 1b) through the switch 14. Simultaneously, the data D 510 of the output M B of the mean value circuit 11 is latched in the latch circuit 12.
- the data D 510 is:
- the data of the output M B of the mean value circuit 11 becomes the mean value between the data D 511 of the input M 3 of the shift register 110 and the data D 511 of the output M 1 of the shift register 111, that is, the data D 511 itself, and this is latched in the latch circuit 12.
- the data D 1 of the first input M 3 of the shift register 110 is lacking part data.
- this data item D 1 is stored in the shift register 110, the output M 2 thereof becomes data D 1 and the input M 3 thereof becomes data D 2 .
- the switch 15 is thrown to the f side thereof, the latch circuit 12 lacthes the data D 2 of the input M 3 of the shift register 110.
- This data item D 2 is the first picture element data R 1 in the line.
- the shift register 111 holds indefinite data, and the signal selector 402 is not fed with the output of the digital interpolation circuit 401.
- the shift register 111 is fed with the data D 1 of the output M 2 of the shift register 110, and the shift register 110 is fed with the data D 2 of the input M 3 thereof. Accordingly, the output M 1 of the shift register 111 becomes the data D 1 , and that M 2 of the shift register 110 becomes the data D 2 . Besides, the input M 3 of the shift register 110 becomes data D 3 . At this time, the data D 2 of the output M B of the mean value circuit 11 becomes: and the output M A of the latch circuit 12 is the data D 2 . Further, the switch 15 is changed-over to the e side thereof, but the latch circuit 12 continues to hold the data D 2 .
- the output M 1 of the shift register 111 is the lacking part data D 1 , the switch 14 is thrown to the b side, and the data D 2 of the output M A of the latch circuit 12 is fed into the signal selector 402 through the switch 14 as the first output data of the digital interpolation circuit 401.
- Fig. 8 shows another practicable example of the digital interpolation circuit 401.
- This digital interpolation circuit 401 is provided anew with a switch 18 and a data generator 19.
- the same portions as in the circuit shown in Fig. 4 are assigned identical symbols, and shall not be repeatedly explained.
- the first or last dot of each line (in Fig. 5a, the parts of the picture element or the lacking part ) is interpolated with a predetermined data item, for example, white level data whose bits are all "1".
- a predetermined data item for example, white level data whose bits are all "1".
- the switch 18 is thrown to the contact g side thereof as to the second to 511th parts of the line.
- the switch 14 when the output M 1 of the shift register 111 is picture element data R 2n , the switch 14 is thrown to the contact a side, and this data item is fed into the signal selector 402 (Fig. la or lb( through the switches 14 and 18.
- the switch 14 When the output M 1 of the shift register 111 is lacking part data x 2n+1 , the switch 14 is thrown to the contact b side, and the output M A of the latch circuit 12 is fed into the signal selector 402 through the switches 14 and - 18 as interpolation data C 2n+1 .
- the switch 18 When the output M 1 of the shift register 111 is data R 1 or R 512 expressive of the first of last part of the line, the switch 18 is changed-over to the h side thereof by a switching pulse from the pulse generator 17, and the data of a predetermined value provided by the data generator 19 is fed into the signal selector 402 through the switch 18 as interpolation data C 1 or C 512 .
- the data of the predetermined value is assumed the data in which all bits are "1", it is not printed on a printing paper. Accordingly, the uppermost part and lowermost part of each line on a printed frame become a white state when this processing is performed for the digital G, R and B signals.
- the switches 13 and 15 in Fig. 4 are dispensed with to simplify the circuit arrangement, and to simplify the interpolation processing.
- the edges of the printed frame have undesired colors and are conspicuous, whereas with the practicable example of Fig. 8, white edges are formed and are not problematic.
- the number of the heads in the head assembly 6 (Fig. la or lb) has- been equal to the number of picture elements per line (the number of 512).
- the number of heads may well be reduced by two into 510 so as to print the second to 511th picture element data in the line by means of the 510 heads.
- the first and last dots of the line need not be interpolated, and effects similar to those of the practicable example shown in Fig. 8 are attained.
- Fig. 9 shows still another practicable example of the digital interpolation circuit 401 in Fig. 1.
- a line memory portion 9' including line memories 901, 902 and 903, and a latch portion 20 including latch circuits 201, 202 and 203 are added anew to the practicable example of Fig. 4.
- the same parts as in Fig. 4 are assigned identical symbols, and shall not be repeatedly explained.
- the line memory portion 9' consists of the three line memories 901, 902 and 903, in which the digital color signals of corresponding lines in a time-sequential order are respectively stored.
- a line which is stored in the line memory 902 is the line to be fed into the signal selector 402 after the data interpolation.
- the immediately preceding line is stored in the line memory 903, and the immediately succeeding line in the line memory 901.
- data items stored at the same addresses of the line memories 901, 902 and 903 are the data items of those sampling points of the lines stored in the respective memories which are arrayed in the horizontal direction of a frame. Accordingly, when data stored at a certain address of the line memory 902 is the picture element data of the corresponding line, data items stored at the same addresses of the line memories 901 and 903 are the lacking part data items of the corresponding lines.
- the picture element data D 2l, 2n when the picture element data D 2l, 2n is read out from the line memory 902, it is supplied to the signal selector 402, and when the lacking part data D 2l, 2n+1 is read out, the mean data of the picture element data items D 2l+1, 2n+l and D 2l-1, 2n-1 read out from the line memories 901 and 903 is supplied to the signal selector 402 as the interpolation data D 2l, 2n+1 .
- the line L 2l is transferred from the line memory 902 to the line memory 903, and the line L 2l+1 is transferred from the line memory 901 to the line memory 902. Simultaneously therewith, the line L 2l+2 is supplied from the signal discriminator 8 to the line memory 901. Thus, the line L 2l+1 is similarly processed.
- Fig. 11 shows still another practicable example of the digital interpolation circuit 401 in Fig. la or lb.
- this example differs in a latch circuit 10' and a mean value circuit 11'. Portions corresponding to those in Fig. 4 and Fig. 9 are assigned the same symbols.
- interpolation data D 2l, 2n+1 is formed using the picture element data items R n-1 and R n+1 along the line in the practicable example shown in Fig. 4 and the picture element data items D 2l-1, 2n+1 , D 2l+1, 2n+1 and D 2l, 2n+l of the adjoining lines in the practicable example shown in Fig. 9.
- the lines L 2l+1 , L 2l and L 2l-1 be respectively stored in the line memories 901, 902 and 903.
- the data items of the (2n - l)-th addresses of the line memories 901, 902 and 903 appointed by the address counter 16 be respectively latched in the latch circuits 201, 202 and 203
- the data latched in the latch circuit 201 is D 2l+1, 2n-1
- the data latched in the latch circuit 203 is D 2l-1, 2n-1
- the data latched in the latch circuit 202 is the lacking part data X.
- data latched in the latch circuit 10' is data D 2l, 2n-2 stored at an address [the (2n - 2)-th address] immediately preceding the address in the line memory 902, of the data latched in the latch circuit 202.
- the mean value circuit 11' creates the mean data D 2l, 2n-1 among the data D 2l, 2n from the line memory 902 and the data items D 2l+1, 2n-1 , D 2l-1, 2n-1 and D 2l, 2n-2 respectively produced by the latch circuits 201, 203 and 10' and provides it as its output M B .
- This mean data item D 2l, 2n-1 is expressed as follows:
- the switch 14 is thrown to the b side, and the data D 2l, 2n-1 of the output M B of the mean value circuit 11' is fed into the signal selector 402 (Fig. la or 1b) through the switch 14 as the interpolation data for the lacking part data X of the output M A of the latch circuit 202.
- the latch circuits 201, 202, 203 and 10' latch their inputs respectively, and simultaneously, the switch 14 is changed-over to the a side.
- the lacking part data items X are respectively latched in the latch circuits 201, 203 and 10', but picture element data D 2l, 2n is latched in the latch circuit 202.
- the data D 2l, 2n of the output M A of the latch circuit 202 is fed into the signal selector 402 through the switch 14.
- the first and last lacking parts of each line and the first and last line lacking parts cannot be subjected to the data interpolation described above. However, they may be subjected to the data interpolation by the method explained in the embodiment of Fig. 4 or Fig. 9. Alternatively, the first and last lines and the first and last parts of each line may be rendered white on printing paper as explained before.
- Fig. 12 shows still another practicable example of the digital interpolation circuit 401 in Fig. la or lb.
- a mean value circuit portion 11" including mean value circuits 115, 116 and 117; a level comparison portion 21 including comparator circuits 210 and 211; data selectors 22 and 23; a shift register portion 24 including shift registers 241, 242 and 243; a latch portion 25 including latch circuits 252 and 253; a latch circuit 26; and a level comparison portion 27 including comparator circuits 270 and 271.
- the other portions corresponding to those in Fig. la or lb and Fig. 11 are assigned the same symbols.
- This practicable example usually performs the data interpolation of lacking parts likewise to the practicable example shown in Fig. 11 and further performs the data interpolation of lacking parts as regards the contour parts of picture elements and so as not to deteriorate them.
- the contour parts of picture elements and detected with the digital G signal the information content of which is not decreased.
- the level comparison portion 11" consists of the mean value circuit 115 which creates the mean data between data read out from the line memory 902 and the output data of the latch circuit 10', the mean value circuit 116 which creates the mean value data between the output data items of the latch circuits 201 and 203, and the mean value circuit 117 which creates the mean value data between the outputs of the mean value circuits 115 and 116.
- the outputs A V , A H and AS of these mean value circuits 115, 116 and 117 are supplied to the data selector 22 as inputs D 1 , D 2 and D 0 respectively.
- the output A S of the mean value circuit 117 is the same as the output M B of the mean value circuit 11' in Fig. ll.
- the output data of the latch circuit 10' is supplied to the data selector 23 as an input D 0 ', and the read-out data of the line memory 902 as an input D 1 ', and the output data of the latch circuit 201 is supplied thereto as inputs D 2 ' and D 3 '.
- the inputs are selected according to the outputs of the level comparison portion 27, and the selected data is supplied to the data selector 22 as an input D 3 .
- the output data of the latch circuit 10' and the read-out data of the line memory 902 are compared by the comparator circuit 210, and the output data items of the latch Circuits 201 and 203 are compared by the comparator circuit 211.
- the data selector 22 selects any of the inputs DO - D 3 .
- the signal discriminator 8 extract the digital R signal from the R/B signal delivered from the frame memory 303, and that the lines L 2l+1 , L 2l and L 2l-1 thereof be respectively stored in the line memories 901, 902 and 903.
- the picture element data of these lines be R i, j (where i denotes line No., and j denotes dot No.), as shown in Fig. 13, at the (n - l)-th addresses, the line memories 901 and 903 store the lacking part data X and the line memory 902 stores picture element data R l, n-1 .
- the line memories 901 and 903 store picture element data R l+1, n and R l-1, n , and the line memory 902 stores lacking part data X (which is especially expressed as .
- the line memories 901 and 903 store the lacking part data X
- the line memory 902 stores picture element data R l, n-1 .
- the switch 14 is thrown to the a side, and this picture element data item R l, n-1 is fed into the signal selector 402 through the switch 14.
- the line memories 901, 902 and 903 have the next n-th addresses appointed, so that the picture element data items R l+1, n and R l-1, n are respectively read out from the line memories 901 and 903 and that the lacking part data is read out from the line memory 902.
- the latch circuits 201 - 203 and 10' latch their input data respectively, and the switch 14 is changed-over to the b side. Accordingly, the output of the line memory 902 becomes R l, n+1 , and the outputs of the latch circuits 201, 203 and 10' become R l+1, n , R k-1, n and R l, n-1 respectively.
- the line memories 901, 902 and 903 have the next (n + l)-th addresses appointed, so that the lacking part data items X are read out from the line memories 901 and 903 and that the picture element data R l, n+1 is read out from the line memory 902.
- the output data items A V , A H and A S of the mean value circuits 115, 116 and 117 become as follows respectively:
- the data selector 22 selects the inputs D 0 - D 3 as an output Z R in accordance with select signals S 0 and S 1 as indicated in the following table 1, and the output Z R is fed into the signal selector 402 through the switch 14 as the interpolation data of the lacking part .
- the select signals S 0 and S 1 of the data selector 22 are formed by the level comparison portion 21.
- the comparator circuit 210 compares the output data R l, n-1 of the latch circuit 10' and the read-out data R l, n+1 of the line memory 902 and obtains the difference data ⁇ R V : which is compared with preset reference data D S .
- the reference data D is set at about 1 ⁇ 2 of the maximum value of ⁇ R V .
- the comparator circuit 211 obtains the difference data ⁇ R H between the output data items of the latch circuits 201 and 203, namely: which is compared with the reference data D S .
- the select signals S 0 and S 1 are determined as listed in the following table:
- This data item forms a vertical contour along the line L as to red.
- the change between the picture element data items R l, n-1 and R l, n+1 of the same line L l holding the lacking part X l, n therebetween is great, and the change between the picture element data items R l-1, n and R l+1, n of the respective lines L l-1 and L l+1 is small.
- the output . data Z 23 of the data selector 23 will be explained below.
- the digital G signal is a wideband signal and does not lack any picture element data, so that it has a very large amount of information.
- a contour exist obliquely on a frame thereby to give rise to the oblique contour concerning red as explained before, a similar oblique contour will exist concerning also the green color.
- the output data A, A or AS of the mean value circuit 115, 116 or 117 is used as the interpolation data of the lacking part X l , n in this contour, the digital R signal changes gently in this contour part as indicated by a broken line in Fig.
- the value of the picture data G l, n of the digital G signal is greater as compared with the values of the interpolation data items, and hence, the contour in the oblique direction becomes greenish on the printed frame.
- the contour it is more preferable to be fringed in black rather than to be colored in green in this manner.
- the digital R signal should better be changed as indicated by a solid line, not by a dotted line.
- the picture element data R l, n+1 is employed as the interpolation data of the lacking part Xe nof the digital R signal.
- the interpolation data items of the lacking parts of the digital R and G signals are determined according to the change of the digital G signal.
- the data selector 23 selects one of the picture element data R l, n-1 from the latch circuit 10 1 , the picture element data R l, n+1 from the line memory 902 and the picture element data R l+1 n from the latch circuit 201 through select signals S 0 ' and S 1 ' in accordance with the change of the digital G signal.
- the digital G signal read out from the frame memory 302 is supplied to the shift register portion 24, and one picture element data item is stored in each of the shift registers 241, 242 and 243.
- the shift registers 241, 242 and 243 store the picture element data items of the digital G signal at the same picture element positions as those of data items which are being read out from the line memories 901, 902 and 903. Assuming that the read-out data from the line memory 902 be the picture element data R l, n+1 , the picture element data G l, +1 is being stored in the shift register 242.
- the latch circuit 252 latches the picture element data G l, n on the same line L l as that of the picture element data G l, n+1 and preceding by one dot, and the latch circuit 26 latches the picture element data G l, n-1 preceding by one more dot.
- the shift register 243 stores the picture element data G l-1, n+1 of the line L l-1
- the latch circuit 253 latches the picture element data G l-1, n preceding by one dot.
- the positional relations of these picture element data items and the storing circuits are shown in Fig. 15 in correspondence with Fig. 13. The storing circuits are indicated by suffixes.
- the level comparison portion 27 subjects the output data items of the latch circuits 252, 253 and - 26 to comparison processes similar to those of the level comparison portion 21.
- the comparator circuit 270 compares the output data items G l , n and G l, n-1 of the respective latch circuits 252 and 26 and obtains difference data ⁇ G V : so as to decide the relation of magnitudes with the reference data D S .
- the result of this decision is the S 0 ' input of the data selector 23.
- the comparator circuit 271 compares the output data items G l,n and G l-1, n of the respective latch circuits 252 and 253 and obtains difference data ⁇ G H : so as to decide the relation of magnitudes with the reference data D S .
- the result of this decision is the S 1 ' input of the data selector 23. According to such S 0 ' and S 1 ' inputs, the data selector 23 selects any one of its inputs D 0 ' - D 3 , as indicated in Table 3 below.
- ⁇ G V denotes the change of picture element data items in the vertical direction (along the line)
- ⁇ G H the change of picture element data items in the horizontal direction.
- the data selector 23 selects the input D 0 ', namely, the picture element data R l , n-1 delivered by the latch circuit 10' and supplies it to the D 3 input end of the data selector 22.
- the data selector 22 uses as the interpolation data of the lacking part X l , n the picture element data R l, n-1 on the same line L l and directly preceding the lacking part X l , n and delivers it as an output Z R . This corresponds to pre-holding in which the picture element data R l , n-1 is held and is supplemented to the lacking part X l , n
- the picture element data R l, n-1 may well be replaced with picture element data R l-1, n as the interpolation data. This measure signifies pre-holding in the direction orthogonal to the line (namely, in the horizontal direction).
- the data selector 23 selects the picture element data R l, n+1 (D 1 ' input) along the line L l of the lacking part X l, n of the digital R signal and directly succeeding the lacking part and delivers it to the data selector 22.
- the data selector 22 delivers the picture element data R l, n+1 supplied from said data selector 23, as interpolation data for the lacking part X n,l .
- the contour concerning the digital R signal and the contour concerning the digital G signal are registered on the printed image, and they are made abrupt to equal extents so as to clarify the contours of the colors on the printed image. That is, the contours are not colored in green by way of example but become rather blackish.
- the data selector 23 selects the picture element data R l+1, n of the line L l+1 directly succeeding the line L l where the lacking part X l , n exists, and it supplies the selected data to the data selector 22:
- the data selector 22 delivers the picture element data R l+1, n supplied from the data selector 23, as interpolation data for the lacking part x n .
- the mode H is a case where the oblique contour exists concerning the digital G signal.
- the picture element data R l+1 , n (the D 3 1 input of the data selector 23) as the interpolation data of the lacking part X l, n of the digital R signal.
- the picture element data R l+1 , n may well be replaced with the picture element data R l, n+1 directly succeeding the lacking part X l, n of the line L l .
- the interpolation data of this lacking part X l is set according to the change of the digital G signal which has the large amount of information with no data omitted, whereby the contour in the printed image becomes clear without being colored. Besides, contours in the horizontal and vertical directions concerning the digital R signal can be clearly reproduced. Needless to say, the data interpolation processing stated above is similarly executed for the digital B signal.
- the items of reference data D S have been equalized and have been set at 1 ⁇ 2 of the dynamic range. Needless to say, however, the reference data D S can be set at will, in accordance with a printing function or for each of the level comparison portions 21 and 27 or the comparator circuits 210, 211, 270 and 271,
- first and last lacking parts of each line may be supplemented or that the first and last dots of each line and the first and last lines may be similarly made white on the printing paper.
- the R and B signals are multiplexed and stored in the identical frame memory, they may well be stored in individual memories, and if necessary, the sampling rate may well be lowered for only the B signal by way of example so as to reduce the capacity of the memory.
Abstract
Description
- The present invention relates to a signal processing circuit for a color video printer which depicts a color print close in quality to a photograph on a printing paper on the basis of a color video signal.
- Regarding prior-art color video printers, 'IEEE Transactions on Consumer Electronics, Vol. CE-28, No. 3, August 1982' contains a paper entitled "Color Video Picture Printer" by Sohei Masuda, and 'IEEE Transactions on Consumer Electronics, Vol. CE-31, No. 3, August 1985' contains a paper entitled "A COLOR VIDEO PRINTER WITH SUBLIMITATION DYE TRANSFER METHOD". by Yasunori Kobori et al. who are the inventors of the present invention.
- As stated in the papers, with the prior-art video printers, a video signal of one frame is disjoined into R (red), G (green) and B (blue) signals which are the components of a color signal or into Cy (cyan), Ye (yellow) and Mg (magenta) signals which correspond to the color components of a coating material. The resulting signals are respectively converted into digital signals, which are once stored in dedicated semiconductor frame memories.
- The respective color signals are read out and printed in a predetermined order. In this case, the frame memories and analog-to-digital converters (hereinbelow, termed A/D converters) for converting the color signals are driven at an identical clock frequency. Therefore, all the video signals can be uniformly stored in the frame memories within the frame period thereof (33 msec, in the NTSC format, and 40 msec. in the PAL format).
- Since, however, each of the prior-art video printers requires the A/D converters and the frame memories for the respective color signals, the circuit arrangement thereof becomes complicated. It also has a problem in the aspect of cost because a . large number of RAMs (random access memories) are needed as the frame memories, and the A/D converters are needed in the number of three.
- An object of the present invention is to reduce the memory capacity of memory means for storing video signals.
- Another object of the present invention is to provide a signal processing circuit for a video printer which has a simple circuit arrangement.
- The color video printer of the present invention comprises a first memory for storing the first color signal which requires the largest amount of information among the three color signals of a color video signal, and a second memory for storing the remaining second and third color signals. The color signal to be stored in the second memory is input at a sampling rate lower than that of the color signal to be stored in the first memory.
- The color video printer further comprises an interpolation circuit by which the color signal stored in the second memory is interpolated to reproduce data.
-
- Figs. la and lb are block diagrams each showing an embodiment of a signal processing circuit for a video printer according to the present invention;
- Fig. 2a is an explanatory diagram of-an output singal from a synthesis switch in Fig. la or lb, while Figs. 2b and 2c are explanatory diagrams of digital color signals respectively separated from the signal shown in Fig. 2a;
- Fig. 3 is an explanatory diagram showing a printing operation in fig. la or-lb;
- Fig. 4 is a block diagram showing a practicable example of a digital interpolation cirucit in Fig. la or Ib;
- Figs. 5a and 5b are schematic diagrams showing digital color signals before and after the data interpolation of the practicable example respectively;
- Figs. 6a and 6b and Figs. 7a and 7b are explanatory diagrams showing the data interpolation operations in Fig. 4 respectively;
- Fig. 8 and Fig. 9 are block diagrams each showing another practicable example of the digital interpolation circuit in Fig. la or lb;
- Fig. 10 is an explanatory diagram showing the operation of the practicable example shown in Fig. 9;
- Figs. 11 and 12 are block diagrams each showing still another practicable example of the digital interpolation circuit in Fig. la or lb;
- Fig. 13 is an explanatory diagram showing the positional relations between lacking parts and picture element parts in the practicable example of Fig. 12;
- Fig. 14 is an explanatory diagram showing a contour correction effect in the practicable example of Fig. 12; and
- Fig. 15 is an explanatory diagram showing a method of detecting the change of a digital G-signal in the practicable example of Fig. 12.
- Now, embodiments of the present invention will be described with reference to the drawings.
- Fig. la is a block diagram showing an embodiment of a signal processing circuit for a video printer according to the present invention.
- The signal processing circuit of the video printer in this embodiment is constructed of a
signal input portion 1 which is supplied with R, G and B signals, an A/D conversion portion 2 which digitizes the color signals, amemory portion 3 which stores the respective digital color signals, adigital processing portion 4 which processes and selects respective signals read out of thememory portion 3, asignal conversion portion 5 which converts color signals from the digital -processing portion 4 into signals required for printing and supplies the latter to ahead assembly 6, and asystem controller 7 which controls the above blocks. - The
signal input portion 1 consists of an R-signal input terminal 101 to which the R signal is input, a G-signal input terminal 102 to which the G signal is input, and a B-signal input terminal 103 to which the B signal is input. - The A/
D conversion portion 2 is constructed of A/D converters - The
memory portion 3 consists of aframe memory 302 which stores the G signal, aframe memory 303 which stores the R signal and the B signal, asynthesis switch 301 by which the signals to be stored in theframe memory 303 are switched, and amemory controller 304 which controls thesynthesis switch 301, theframe memories D converters digital interpolation circuit 401. - The
digital processing portion 4 is constructed of the digital data interpolation circuit (hereinbelow, termed "digital interpolation circuit) 401 which synthesizes the R signal and B signal on the basis of the signals from theframe memory 303 of thememory portion 3, and asignal selector 402 by which the R signal or B signal from thedigital interpolation circuit 401 and the G signal from theframe memory 302 are output in the order of printing. - The
signal conversion portion 5 consists of a one-line memory 501, apulse generator 502 and a half-tone controller 503. Thepulse generator 502 converts data stored in the one-line memory 501, into a signal of pulse width corresponding to a half-tone control signal from the half-tone controller 503 and supplies the latter to thehead assembly 6. - Next, the operation of this embodiment will be described.
- The G signal, R signal and B signal are respectively input to the
input terminals signal input portion 1, and they are supplied to the A/D conversion portion 2. In the A/D conversion portion 2, these color signals are converted into the digital signals of, e.g., 6 bits at the same timing by the A/D converters memory controller 304 of thememory portion 3, whereupon the digital signals are supplied to thememory portion 3. In thememory portion 3, the G signal digitized by the A/D converter 201 (hereinbelow, termed "digital G-signal EDG") is immediately written into theframe memory 302. On the other hand, the R signal digitized by the A/D converter 202 (hereinbelow, termed "digital R-signal EDR") and the B signal digitized by the A/D converter 203 (hereinbelow, termed "digital B-signal EDB") are written into thecommon frame memory 303 through thesynthesis switch 301. -
- This indicates that the luminance signal E is obtained by mixing 30% of the R color signal ER, 59% of the G color signal and 11% of the B color signal.
- Accordingly, when the amount of information of the G color signal EG necessary for reproducing the luminance signal Ey is expressed by 1 (one), the amount of information of the R color signal ER may be about 1/2, and that of the B color signal EB may be as small as about 1/5.
- In the present invention, therefore, the G color signal EG is A/D-converted at a sampling frequency fG so as to store the digital signal in the
memory 302, whereas the R or B color signal ER or EB is A/D-converted at a sampling frequency ½ of fG so as to store the digital signal in theframe memory 303. - Concretely, the A/
D converters terminals synthesis switch 301 and are then written into theframe memory 303, the R and B color signals are, in effect, A/D-converted at the frequency ½f G. - Alternatively, the analog R color signal ER and B signal EB may well be alternately input to a common A/D converter as shown in Fig. lb.
- Referring to Fig. lB, the
input terminals synthesis switch 305. The output end of thesynthesis switch 305 is connected to the input end of the common A/D converter 204, the output end of which is connected to theframe memory 303. - Since the R color signal ER and B color signal EB applied to the
respective input terminals D converter 204 by thesynthesis switch 305, the digital R signal EDR and digital B signal EDB are alternately stored in theframe memory 303. Also in the circuit shown in . Fig. lb, the R color signal ER of B color signal EB is sampled at the frequency equal to half of that of the G color signal EG as in the circuit shown in Fig. lA. - Fig. 2a shows data items which are to be stored in the
frame memory 303. ® indicates the digital R signal EDR, and Ⓑ the digital B signal EDB. The digital R signal EDR and the digital B signal EDB are stored dot-sequentially. (The signal in which the digital R signal EDR and the digital B signal EDB appear dot-sequentially is called "R/B signal".) - At this time, the amount of information of each of the digital R and B signals EDR, EDB which constitute the R/B signal is ½ of that of the digital G signal EDG. Since, however, the sampling points of the R/B signal and those of the digital G signal are equal in number, the memory capacity of the
frame memory 303 for storing the R/B signal is equal to that of theframe memory 302 for storing the digital G signal EDGe - On the basis of this fact, the embodiment reduces the memory capacity of the memory portion to 2/3 times as compared with the prior art in which the frame memories are provided for the respective digital color signals.
- When the digital G, R and B signals EDG, E DR' EDB for the video signal of one frame have been stored in the
frame memories frame memory 302, and the R/B signal is read out from theframe memory 303, to be supplied to thedigital processing portion 4. - Either of the digital R and B signals is extracted from the R/B signal supplied to the
digital interpolation circuit 401. - Since the extracted digital R signal EDR or digital B signal EDB has been sampled at the sampling frequency
equal to1 2 of that of the digital G signal EDG, the amount of information thereof is insufficient. - The digital R signal EDR extracted from the R/B by the
digital interpolation circuit 401 is shown in Fig. 2b, and the digital B signal EDB is shown in Fig. 2c. In these digital color signals E DR and E DB, the signals (hereinbelow, termed "picture elements") of sampling points (hereinbelow, termed "dots") are denoted by ® and Ⓑ, and the dots (hereinbelow, termed "lacking parts") where the picture elements are missed by thesynthesis switch 301 are denoted . by marks x. Regarding one frame, as shown in Figs. 2b and 2c, the digital R and G signals EDR and EDB extracted from the R/B signal are respectively such that the picture elements ® and the lacking parts x are alternately arrayed and that the picture elements Ⓑ and the lacking parts x are alternately arrayed. - The
digital interpolation circuit 401 interpolates the signals of the lacking parts x by the use of the signals of the dots of the actually existing picture elements ® and Ⓑ, thereby to form the digital R and B signals EDR and EDB whose information quantities are increased. - The
signal selector 402 selects the digital G signal EDG from theframe memory 302 and the digital R signal EDR or B signal EDB from thedigital interpolation circuit 401 in succession in the order of printing and supplies them to thesignal conversion portion 5. - First, in order to print a green image, the digital G signal EDG is selected, and the signals thereof corresponding to one frame are supplied to the
signal conversion portion 5. Subsequently, in order to print a red or blue image, the output signal of thedigital interpolation circuit 401 is selected.. In thedigital processing portion 4, in the period during which thedigital interpolation circuit 401 is selected, thiscircuit 401 extracts the digital R signal EDR from the R/B signal in order to first print red. The digital R signal EDR extracted and subjected to the interpolation processing is supplied to thesignal conversion portion 5 by thesignal selector 402. In order to subsequently print blue, thedigital interpolation circuit 401 extracts the digital B signal EDB from the R/B signal. The extracted and interpolated digital R signal EDR is supplied to thesignal conversion portion 5. Such selecting operations of thesignal selector 402 are performed under the control of thesystem controller 7. - In the
signal conversion portion 5, the signals of one line from the digital color signal EDG, EDG or EDB input from thesignal selector 402 are held in theline memory 501. Under the control of the half-tone controller 503, all the picture elements held in theline memory 501 are simultaneously converted into gradation pulses conforming to the respective information contents by means of thepulse generator 502. At the same time, the gradation pulses are supplied to thehead assembly 6 to effect the printing. - Here, the signals corresponding to one line consist of signals which correspond to a column of picture elements arrayed in a direction perpendicular to the horizontal scanning direction of a television screen. As illustrated in Fig. 3, the gradation pulses obtained by converting the signals of the picture elements of a line signal are simultaneously applied to the
respective heads head assembly 6 which are arranged in the vertical direction (as viewed on the drawing) of printing paper P, whereby the information is printed on the printing paper P. - In Fig. 3, the moving direction of the
head assembly 6 relative to the printing paper P is as indicated by an arrow. In thesignal conversion portion 5, the digital color signals of one line are held in theline memory 501 every frame of the applied digital color signal EDG' E DR or E DB. Accordingly, thehead assembly 6 prints line by line rightwards from the left end of the printing paper P as it moves relative to the printing paper P. In addition, thehead assembly 6 first prints the green image over the whole area of the printing paper P on the basis of the G signal EDG, subsequently prints the red image on the basis of the R signal EDR and further prints . the blue image on the basis of the B signal EDB, thereby to print one video image on the printing paper P. The above printing order is appointed by the half-tone controller 503 under the control of thesystem controller 7 shown in Fig. la and Fig. lb. - Although color signals which are actually supplied for the printing are cyan (Cy), yellow (Ye) and magenta (Mg) signals, the R, G and B signals have been used for the description. The Cy, Ye and Mg signals are obtained by converting the R, G and B signals, and the conversion may be executed in the
digital processing portion 4 by way of example. Alternatively, color signals to be applied to theinput portion 1 may be the Cy, Ye and Mg signals. - As described above, since the digital R signal EDR and the digital B signal EDB are stored in the identical memory.303, the memory capacity of the
memory portion 3 is reduced. Although the amounts of information of the digital R signal EDR and B signal EDB decrease on account of thesynthesis switch 301, the lacking information contents are supplemented by thedigital interpolation circuit 401. Therefore, the degration of the picture quality of a printed picture can be prevented. - Next, practicable examples of the digital inter-'
polation circuit 401 in Fig. la or lb will be described. - Fig. 4 is a block diagram showing one practicable example of the
digital interpolation circuit 401. Thisdigital interpolation circuit 401 consists of asignal discriminator 8, aline memory 9, ashift register group 10 which is constructed ofshift registers mean value circuit 11, alatch circuit 12, switches 13, 14 and 15, anaddress counter 16, and apulse generator 17. - Referring to the figure, the R/B signal from the frame memory 303 (Fig. la or 1b) is supplied to the
signal discriminator 8, and either digital color signal EDR or EDB is extracted. For the sake of explanation, it is assumed here that the digital R signal EDR be extracted. Then, signals corresponding to one line of the digital R signal EDR are stored in theline memory 9. This digital R signal for one line (namely, the line signal) EDR is stored in theline memory 9 in such a manner that, as shown in Fig. 5a, data items corresponding to picture elements ® and data items corresponding to lacking parts are alternately arrayed in the order of , , , ' , ...... -
- This
digital interpolation circuit 401 carries out the data interpolation on the basis of an interpolating method to be stated below. - As illustrated in Fig. 5a, odd-numbered dots have the data of the picture elements, whereas even-numbered dots are the lacking parts and have no data. Now, letting R2n-1 and R2n+1 denote the data items (hereinbelow, termed "picture element data") of the respective picture elements and , and C2n denote a data item (hereinbelow, termed "interpolation data") to be interpolated in the lacking part between them, the following operation is executed:
- That is, the mean value of the picture element data of the upper and lower picture elements is used as the interpolation data of the lacking part x2n. The interpolation based on this operation is executed for all the lacking parts x: This interpolation is not applicable to the last lacking part . As the interpolation data C512 therefor, the picture element- data R511 of the picture element located above is used. That is, the following operation is executed:
- Owing to the execution of such interpolation, the digital R signal EDR for one line becomes as shown in Fig. 5b.
- Hereunder, the operation of the practicable example of the digital interpolation circuit 401 (as shown in Fig. 1) in Fig. 4 as based on the above-stated interpolation method will be explained.
- The picture element data R2n+1 and the data C2n of the lacking part x2n are read out from the
line memory 9 successively in a downward sequence shown in Fig. 5a, in accordance with address signals from theaddress counter 16 which is operated by the clock of the memory controller 304 (Fig. la or lb). The address signals produced from theaddress counter 16 are also supplied to thepulse generator 17. Thepulse generator 17 generates switching pulses for switching theswitches address counter 16. When transferring data to theshift register 110, theswitch 13 is thrown to the contact c side thereof, so that the picture element data R2n+1 and the lacking part data x2n from theline memory 9 are transferred toward the shift registers 110 and 111 through theswitch 13 in synchronism with the clock from thememory controller 304. When the output M1 of theshift register 111 is the picture element data owing to the transfer, theswitch 14 is thrown to the contact a side thereof by the switching pulse from thepulse generator 17, and this picture element data item R2n+1 is supplied to the signal selector 402 (Fig. la or lb) through theswitch 14. In contrast, when the output M1 of theshift register 111 is the lacking part data x2n, theswitch 14 is thrown to the contact b side, and the output MA of thelatch circuit 12 is supplied as the interpolation data C2n to thesignal selector 402 through theswitch 14. - This interpolation data item C2n is formed as follows:
- Assuming now that the data of the output M3 of the
line memory 9 be D2n, the data items of the outputs M2 and M1 of the shift registers 110 and 111 are D 2n-1 and D2n-2 respectively. The output M3 of theline memory 9 and that M1 of theshift register 111 are supplied to themean value circuit 11, to calculate the mean value of them. Accordingly, the data D2n-1 of the output MB of themean value circuit 11 becomes: -
-
- It is now assumed that, as shown in Fig. 5a, the odd-numbered dots in a certain line be the picture elements , , , ....., while the even-numbered dots be the lacking parts , , ...... In addition, picture element data for such picture elements is assumed data D2i-1 with suffixes of odd numbers, and picture element data for such lacking parts is assumed data D2i with suffixes of even numbers.
- It is assumed that, at a certain point of time, the data of the output M1 of the
shift register 111 be D2n-1' while the output M2 and input M3 of theshift register 110 be D2n and D2n+l respectively. Then, the odd-numbered data D2n-1 of the output M1 of theshift register 111 is the picture element data and therefore requires no interpolation. Theswtich 14 is thrown to the contact a side, and this data item D2n-1 passes through theswitch 14 to be fed into the signal selector 402 (Fig. la or lb). On this occasion, thelatch circuit 12 is continually supplied with the output MB of themean value circuit 11 for the picture element data items:switch 15 which is thrown on the contact e side thereof. Thelatch circuit 12, however, still holds the data D2n-2 [= (D2n-2 + D2n)/2] of the preceding output MB of themean value circuit 11. - When the
signal selector 402 has received the data D2n-1 of the output M1 of theshift register 111, thelatch circuit 12 latches the aforementioned data D2n of the output MB of themean value circuit 11. Subsequently, when theshift register 111 is fed with the data D2n of the output M2 of theshift register 110 and thisshift register 110 is fed with the data D2n-1 at the input M3 thereof, the output M1 of theshift register 111 is the lacking part data x2n, and hence, theswitch 14 is changed-over to the contact b side. Therefore, the data D2n of the output MA of thelatch circuit 12 is fed into thesignal selector 402 through theswitch 14. -
- This is the mean of the two lacking part data items D2n and D2n+1.
- When the
signal selector 402 has received the data D2n from thelatch circuit 12, this latch cir- cuit 12 latches the aforementioned data D2n+1 of the output MB of themean value circuit 11. Subsequently, theshift register 111 is fed with the data D2n+1 of the output M2 of theshift register 110, and this shift register l10 is fed with the data D2n+2 of its input M3. Simultaneously therewith, the input M3 of the shift register l10 becomesdata D2n+ 3, and theswitch 14 is thrown to the contact a side. - In this way, when the output M1 of the
shift register 111 is the odd-numbered data and the picture element data R2n+1, this data item is fed into thesignal selector 402, and when it is the even-numbered data and the lacking part data x2n, the mean value of the picture element data items R2n and R2n+1 before and after the lacking part data is fed into thesignal selector 402 as the interpolation data C2n. - In the above, the odd-numbered dots in one line have been the picture elements, and the even-numbered dots have been the lacking parts as shown in Fig. 5a. In the reverse case, as illustrated in Fig. 6b, the
switch 14 is thrown to the a side when the output M1 of theshift register 111 is any of even-numbered data items D2m-2' D2m' ....., and it is thrown to the b side when the output M1 is any of odd-numbered data items D2m-1, D2m+1, ...... The other operations are similar to those in the foregoing. - Although the above interpolation is valid for the lacking parts ~ in Fig. 5a, such interpolation data C512 cannot be created for the lacking part . As explained before, the interpolation of this lacking part is to put the picture element data R511 of the picture element as the interpolation data C512. Next, this interpolation operation will be described with reference to Fig. 7a.
- Assuming in Fig. 4 that the input M3 of the
shift register 110 be the picture element data D511 of the final picture element , the data of the output M1 of theshift register 111 is D509' and this is supplied to the signal selector 402 (Fig. la or 1b) through theswitch 14. Simultaneously, the data D510 of the output MB of themean value circuit 11 is latched in thelatch circuit 12. Here, the data D510 is: - Subsequently, when the input M3 is stored in the
shift register 110 and the output M2 (data D510) of thisshift register 110 is.stored in theshift register 111, theswitch 13 is thrown to the d side thereof. Thus, the data items of the input M3 and output M2 of the shift register l10 become equal and D511' On this occasion, theswitch 14 is thrown to the b side, and the output MA of thelatch circuit 12 is supplied to thesignal selector 402 as the interpolation data of the lacking part . - Further, when the output M2 of the data D511 from the
shift register 110 is stored in theshift register 111 and the input M3 of the data D511 is stored in theshift register 110, all the data items of the input M3 and output M2 of theshift register 110 and the output M1 of theshift register 111 become D511. Theswitch 14 is thrown to the a side thereof, and the data D511 of the output M1 of theshift register 111 is supplied to thesignal selector 402. Simultaneously therewith, the data of the output MB of themean value circuit 11 becomes the mean value between the data D511 of the input M3 of theshift register 110 and the data D511 of the output M1 of theshift register 111, that is, the data D511 itself, and this is latched in thelatch circuit 12. - Further, when the output M2 of the
shift register 110 is stored in theshift register 111 and the input M3 of thisshift register 110 is stored therein, theswitch 14 is changed-over to the b side thereof, and the output MA of the data D511 from thelatch circuit 12 is supplied to thesignal selector 402 through theswitch 14. This is the interpolation data of the lacking part in Fig. 5a. - Next, a case where the first dot of a line is a lacking part unlike the arrayal of Fig. 5a will be described with reference to Fig. 7b.
- When the readout of the
line memory 9 is started with theswitch 13 thrown to the c side thereof, the data D1 of the first input M3 of theshift register 110 is lacking part data. When this data item D1 is stored in theshift register 110, the output M2 thereof becomes data D1 and the input M3 thereof becomes data D2. At this time, theswitch 15 is thrown to the f side thereof, thelatch circuit 12 lacthes the data D2 of the input M3 of theshift register 110. This data item D2 is the first picture element data R1 in the line. Thus far, theshift register 111 holds indefinite data, and thesignal selector 402 is not fed with the output of thedigital interpolation circuit 401. - Subsequently, the
shift register 111 is fed with the data D1 of the output M2 of theshift register 110, and theshift register 110 is fed with the data D2 of the input M3 thereof. Accordingly, the output M1 of theshift register 111 becomes the data D1, and that M2 of theshift register 110 becomes the data D2. Besides, the input M3 of theshift register 110 becomes data D3. At this time, the data D2 of the output MB of themean value circuit 11 becomes:latch circuit 12 is the data D2. Further, theswitch 15 is changed-over to the e side thereof, but thelatch circuit 12 continues to hold the data D2. - Therefore, the output M1 of the
shift register 111 is the lacking part data D1, theswitch 14 is thrown to the b side, and the data D2 of the output MA of thelatch circuit 12 is fed into thesignal selector 402 through theswitch 14 as the first output data of thedigital interpolation circuit 401. - Subsequently, when the
shift register 111 is fed with the data D2 of the output M2 of theshift register 110 and theshift register 110 is fed with the data D3 of the input M3 thereof, theswitch 14 is changed-over to the a side, and the data D2 of the output M1 of theshift register 111 is fed into thesignal selector 402 through theswitch 14. Simultaneously therewith, the data D3' of the output MB of themean value circuit 11 becomes: - This is latched in the
latch circuit 12, but is interrupted by the switch 14: - Thenceforth, operations are similar to those in the foregoing. In this way, the first lacking part - of the line is supplemented by the succeeding picture element.
- To sum up the above operations, in the line which consists of, for example, 512 data items held in the
line memory 9, intermediate lacking parts (second to 511th data items) are interpolated using the mean values (mean data) of the picture element data items before and after them, and when lacking parts at both the ends of the line (first and 512th data items) need to be interpolated, the second picture element data R2 is substituted for the first lacking part x1 and the 511th picture element data R511 is substituted for the 512th lacking part x512. This method of data interpolation is performed in the direction of the line to be printed, namely, in the vertical direction of the surface of the monitor in Fig. 3. - Fig. 8 shows another practicable example of the
digital interpolation circuit 401. Thisdigital interpolation circuit 401 is provided anew with aswitch 18 and adata generator 19. The same portions as in the circuit shown in Fig. 4 are assigned identical symbols, and shall not be repeatedly explained. - In the foregoing practicable example shown in Fig. 4, the first or last lacking part of each line has been interpolated with the directly succeeding or directly preceding picture element data respectively. In this practicable example shown in Fig.
- 8, the first or last dot of each line (in Fig. 5a, the parts of the picture element or the lacking part ) is interpolated with a predetermined data item, for example, white level data whose bits are all "1". As a result, in the case of the interpolation with the white level data, the number of picture elements per line of a printed image becomes 510 which is about 0.4% smaller than the number of 512, but quite no problem is posed in vision.
- Next, the operation of this practicable example will be explained.
- Referring to Fig. 8, the
switch 18 is thrown to the contact g side thereof as to the second to 511th parts of the line. As in the practicable example shown in Fig. 4, when the output M1 of theshift register 111 is picture element data R2n, theswitch 14 is thrown to the contact a side, and this data item is fed into the signal selector 402 (Fig. la or lb( through theswitches shift register 111 is lacking part data x2n+1, theswitch 14 is thrown to the contact b side, and the output MA of thelatch circuit 12 is fed into thesignal selector 402 through theswitches 14 and - 18 as interpolation data C2n+1. - When the output M1 of the
shift register 111 is data R1 or R512 expressive of the first of last part of the line, theswitch 18 is changed-over to the h side thereof by a switching pulse from thepulse generator 17, and the data of a predetermined value provided by thedata generator 19 is fed into thesignal selector 402 through theswitch 18 as interpolation data C1 or C512. When the data of the predetermined value is assumed the data in which all bits are "1", it is not printed on a printing paper. Accordingly, the uppermost part and lowermost part of each line on a printed frame become a white state when this processing is performed for the digital G, R and B signals. - Thus, with this practicable example, the
switches - In the above practicable examples, the number of the heads in the head assembly 6 (Fig. la or lb) has- been equal to the number of picture elements per line (the number of 512). However, the number of heads may well be reduced by two into 510 so as to print the second to 511th picture element data in the line by means of the 510 heads. In this case, the first and last dots of the line need not be interpolated, and effects similar to those of the practicable example shown in Fig. 8 are attained. In addition, similar effects are attained when the number of picture elements of one line has two increased into 514 in which the sixth to 513th picture elements are used as data R6 - R513, and the first to 512th parts are subjected to the data interpolation based on the mean values, only these parts being printed.
- Fig. 9 shows still another practicable example of the
digital interpolation circuit 401 in Fig. 1. - In this practicable example, a line memory portion 9' including
line memories latch portion 20 includinglatch circuits - Each of the foregoing practicable examples has interpolated the lacking part in the line with the mean value of the picture element data items R2n-1 and R2n+1 of the same line, whereas this practicable example interpolates it with the mean value of the picture element data R2ℓ-1, 2n and R2ℓ+1, 2n of both the adjacent lines.
- Next, the operation of this practicable example will be described with reference to Fig. 10.
- Now, a line where a lacking part is to be interpolated is assumed the 2k-th line, which is expressed by L2ℓ. Then, the (2ℓ - l)-th line directly preceding the line L2ℓ is denoted as L2ℓ-1, and the (2ℓ + l)-th line directly succeeding the same is denoted as L2ℓ+1.
- In Fig. 9, digital color signals from the
signal discriminator 8 are supplied to the line memory portion 9'. In this regard, the line memory portion 9' consists of the threeline memories line memory 902 is the line to be fed into thesignal selector 402 after the data interpolation. The immediately preceding line is stored in theline memory 903, and the immediately succeeding line in theline memory 901. - Assuming now that the digital color signals of the line L21 be stored in the
line memory 902, those of the line L2ℓ-1 are stored in theline memory 903, and those of the line L2ℓ+1 are stored in theline memory 901. In addition, data items stored at the same addresses of theline memories line memory 902 is the picture element data of the corresponding line, data items stored at the same addresses of theline memories - Now, let's consider a case where the line L2ℓ is stored in the
line memory 902, the 2n-th address of which stores data D2ℓ, 2n. Then, the same addresses of theline memories - When the (2n - 2)-th addresses of the
line memories address counter 16 and data D2ℓ, 2n-2 being picture element data is read out from theline memory 902 and latched in thelatch circuit 202, lacking part data items Ⓧ are read out from theline memories latch circuits switch 14 is thrown to the a side thereof, and the data D2ℓ, 2n-2 of the output M of thelatch circuit 202 is fed into the signal selector 402 (Fig. la or lb) through theswitch 14. Besides, the output MB of themean value circuit 11 is the mean value between the lacking part data items of the outputs of thelatch circuits - Subsequently, when the
address counter 16 appoints the next (2n - l)-th address, lacking part data Ⓧ is read out from theline memory 902 and is latched in thelatch circuit 202, and data items D2ℓ+1, 2n-1 and D2ℓ-1, 2n-l being picture element data items are respectively read out from theline memories latch circuits switch 14 is changed-over to the b side thereof, and the mean data of the data items D2ℓ+1, 2n-1 and D2ℓ-1, 2n-1 delivered as the output MB of themean value circuit 11 is fed into thesignal selector 402 through theswitch 14 as interpolation data D2ℓ, 2n-1. - Subsequently, when the
address counter 16 appoints the 2n-th address, data D2ℓ, 2n being picture element data is read out from theline memory 902 and latched in thelatch circuit 202, and lacking data items Ⓧ are read out from theline memories switch 14 is thrown to the a side, and the data D2ℓ, 2n of the output MA of thelatch circuit 202 is fed into thesignal selector 402 through theswitch 14. - In this way, when the picture element data D2ℓ, 2n is read out from the
line memory 902, it is supplied to thesignal selector 402, and when the lacking part data D2ℓ, 2n+1 is read out, the mean data of the picture element data items D2ℓ+1, 2n+l and D2ℓ-1, 2n-1 read out from theline memories signal selector 402 as the interpolation data D2ℓ, 2n+1. - When such processing operations for the line L21 have been completed, the line L2ℓ is transferred from the
line memory 902 to theline memory 903, and the line L2ℓ+1 is transferred from theline memory 901 to theline memory 902. Simultaneously therewith, the line L2ℓ+2 is supplied from thesignal discriminator 8 to theline memory 901. Thus, the line L2ℓ+1 is similarly processed. - In this manner, the respective lines are successively subjected to the interpolation of the lacking parts and supplied to the signal selector. It is impossible, however, to subject the first line and the last line to such data interpolation of lacking parts. Regarding these lines, therefore, such processing may be performed as the data interpolation along the line as in the embodiment shown in Fig. 4, the substitution of the data expressive of white as in the embodiment shown in Fig. 8, or the check of the printing of these lines as explained before.
- Fig. 11 shows still another practicable example of the
digital interpolation circuit 401 in Fig. la or lb. - As compared with the practicable example of Fig. 9, this example differs in a latch circuit 10' and a mean value circuit 11'. Portions corresponding to those in Fig. 4 and Fig. 9 are assigned the same symbols.
- In this practicable example, interpolation data D2ℓ, 2n+1 is formed using the picture element data items Rn-1 and Rn+1 along the line in the practicable example shown in Fig. 4 and the picture element data items D2ℓ-1, 2n+1, D2ℓ+1, 2n+1 and D2ℓ, 2n+l of the adjoining lines in the practicable example shown in Fig. 9.
- The operation of this practicable example will be described with reference to Fig. 10.
- It is now assumed that the lines L2ℓ+1, L2ℓ and L2ℓ-1 be respectively stored in the
line memories line memories address counter 16 be respectively latched in thelatch circuits latch circuit 203 is D2ℓ-1, 2n-1, but the data latched in thelatch circuit 202 is the lacking part data Ⓧ. Besides, data latched in the latch circuit 10' is data D2ℓ, 2n-2 stored at an address [the (2n - 2)-th address] immediately preceding the address in theline memory 902, of the data latched in thelatch circuit 202. - When, under such a state, the
address counter 16 appoints the next 2n-th address, the data D2ℓ, 2n is read out from theline memory 902. In addition, the lacking part data items Ⓧ are read out from theline memories line memory 902 and the data items D2ℓ+1, 2n-1, D2ℓ-1, 2n-1 and D2ℓ, 2n-2 respectively produced by thelatch circuits - At this time, the
switch 14 is thrown to the b side, and the data D2ℓ, 2n-1 of the output MB of the mean value circuit 11' is fed into the signal selector 402 (Fig. la or 1b) through theswitch 14 as the interpolation data for the lacking part data Ⓧ of the output MA of thelatch circuit 202. - When the interpolation data has been fed, the
latch circuits switch 14 is changed-over to the a side. Thus, the lacking part data items Ⓧ are respectively latched in thelatch circuits latch circuit 202. - The data D2ℓ, 2n of the output MA of the
latch circuit 202 is fed into thesignal selector 402 through theswitch 14. - Thenceforth, in a similar manner, when the output MA of the
latch circuit 202 is the picture element data, it is fed into thesignal selector 402 through theswitch 14, and when the output MA is the lacking part data, the mean data among the picture element data from theline memory 902 and the picture element data items from thelatch circuits signal selector 402 as the interpolation data. - In this practicable example, the first and last lacking parts of each line and the first and last line lacking parts cannot be subjected to the data interpolation described above. However, they may be subjected to the data interpolation by the method explained in the embodiment of Fig. 4 or Fig. 9. Alternatively, the first and last lines and the first and last parts of each line may be rendered white on printing paper as explained before.
- Fig. 12 shows still another practicable example of the
digital interpolation circuit 401 in Fig. la or lb. Added anew are a meanvalue circuit portion 11" includingmean value circuits level comparison portion 21 includingcomparator circuits data selectors 22 and 23; ashift register portion 24 includingshift registers latch portion 25 includinglatch circuits latch circuit 26; and alevel comparison portion 27 includingcomparator circuits - This practicable example usually performs the data interpolation of lacking parts likewise to the practicable example shown in Fig. 11 and further performs the data interpolation of lacking parts as regards the contour parts of picture elements and so as not to deteriorate them. The contour parts of picture elements and detected with the digital G signal the information content of which is not decreased.
- In the example of Fig. 12, the line memory portion 9', the
latch portion 20 and the latch circuit 10' operate similarly to those in Fig. ll. - The
level comparison portion 11" consists of themean value circuit 115 which creates the mean data between data read out from theline memory 902 and the output data of the latch circuit 10', themean value circuit 116 which creates the mean value data between the output data items of thelatch circuits mean value circuit 117 which creates the mean value data between the outputs of themean value circuits mean value circuits data selector 22 as inputs D1, D2 and D0 respectively. Here, the output AS of themean value circuit 117 is the same as the output MB of the mean value circuit 11' in Fig. ll. - In addition, the output data of the latch circuit 10' is supplied to the data selector 23 as an input D0', and the read-out data of the
line memory 902 as an input D1', and the output data of thelatch circuit 201 is supplied thereto as inputs D2' and D3'. The inputs are selected according to the outputs of thelevel comparison portion 27, and the selected data is supplied to thedata selector 22 as an input D 3. - Further, in the
level comparison portion 21, the output data of the latch circuit 10' and the read-out data of theline memory 902 are compared by thecomparator circuit 210, and the output data items of thelatch Circuits comparator circuit 211. On the basis of the results of the comparisons, thedata selector 22 selects any of the inputs DO - D 3. - Next, the operation of this practicable example will be described with reference to Fig. 13.
- It is now assumed that the
signal discriminator 8 extract the digital R signal from the R/B signal delivered from theframe memory 303, and that the lines L2ℓ+1, L2ℓ and L2ℓ-1 thereof be respectively stored in theline memories line memories line memory 902 stores picture element data Rℓ, n-1. When note is taken of the n-th addresses, theline memories line memory 902 stores lacking part data X (which is especially expressed as . When the (n +1)-th addresses are considered, theline memories line memory 902 stores picture element data Rℓ, n-1. - First, when the output MA of the
latch circuit 202 is the picture element data (assumed to be Rℓ, n-1), theswitch 14 is thrown to the a side, and this picture element data item Rℓ, n-1 is fed into thesignal selector 402 through theswitch 14. This is the same as in the embodiment shown in Fig. ll. At this time, theline memories line memories line memory 902. - When the
signal selector 402 has been fed with -the picture data R n-1, the latch circuits 201 - 203 and 10' latch their input data respectively, and theswitch 14 is changed-over to the b side. Accordingly, the output of theline memory 902 becomes Rℓ, n+1, and the outputs of thelatch circuits line memories line memories line memory 902. Thus, the output data items AV, AH and AS of themean value circuits - These are respectively supplied to the
data selector 22 as the inputs D1, D2 and D0. Besides, the output Z23 of the data selector 23 is supplied to thedata selector 22 as the input D3. -
- The select signals S0 and S1 of the
data selector 22 are formed by thelevel comparison portion 21. - More specifically, the
comparator circuit 210 compares the output data Rℓ, n-1 of the latch circuit 10' and the read-out data Rℓ, n+1 of theline memory 902 and obtains the difference data ΔRV:comparator circuit 211 obtains the difference data ΔRH between the output data items of thelatch circuits -
- As understood from Table 2, when the difference data items ΔRH and ΔRV in the mode A are smaller than the reference data DS, the level differences of the picture element data items around the lacking part Xℓ, n are small, and accordingly, the red color hardly changes near this lacking part Xℓ, n. In this case, the interpolation data D0 similar to that of the embodiment in Fig. 11 is used. In the case of the mode B, it is expressed that the change between the picture element data items Rℓ+1, n and Rℓ-1, n of the two lines adjoining the lacking part Xℓ, n is great and that the change between the picture element data items Rℓ, n-1 and Rℓ, n+1 holding the lacking part Xℓ, n therebetween along the line Lℓ is small. Accordingly, picture element data for this lacking part Xℓ, n ought to be nearly equal to the two picture element data items Rℓ, n-1 and Rℓ, n+1 along the line Lℓ. Therefore, the
data selector 22 selects the output data AV (= input D1) of themean value circuit 115, which is used as the interpolation data. This data item forms a vertical contour along the line L as to red. In the case of the mode C, the change between the picture element data items Rℓ, n-1 and Rℓ, n+1 of the same line Lℓ holding the lacking part Xℓ, n therebetween is great, and the change between the picture element data items Rℓ-1, n and Rℓ+1, n of the respective lines Lℓ-1 and Lℓ+1 is small. This signifies a horizontal contour concerning red, which is orthogonal to the line and passes through the picture element Rℓ, n. In this case, thedata selector 22 selects the mean value of the picture element data items Rℓ-1, n and Rℓ+1, n of small change, namely, the output data AH (= D 2) of themean value circuit 116, and this data item is used as the interpolation data. - In the case of the mode D, great changes are involved between the picture element data items Rℓ, n-1 and R n+1 of the same line Lℓ holding the lacking part Xℓ, n therebetween and between the picture element data items Rℓ+1, n and Rℓ-1, n of the respective lines Lℓ+1 and Lℓ-1 holding the lacking part Xℓ, n therebetween. This corresponds to a case where a contour concerning red exist in a direction oblique to the line. In this case, the
data selector 22 selects the output data Z23 (= D3) of the data selector 23 and supplies it to thesignal selector 402 as the interpolation data. The output . data Z23 of the data selector 23 will be explained below. - The reason why, in the preceding B and C modes, the mean value of the picture data items Rℓ+1, n and Rℓ-1, n and the mean value of the picture data items Rℓ, n-1 and Rℓ, n+1 of great change are not used as the interpolation data items, is that the digital R signal is of narrow band and has a small amount of information, so these mean values cannot always approximate the data items which ought to exist in the lacking parts Xℓ n, namely, the picture element data items which have been missed by the
synthesis switch 301 in Fig. la or 305 in Fig. lb. It is accordingly impossible also in the D mode that the mean value of the picture element data items Rℓ, n-1, Rℓ+1, n' Rℓ, n+1 and Rℓ-1, n surrounding the lacking part Xℓ, n be used as the interpolation data of this lacking part Xℓ, n - On the other hand, the digital G signal is a wideband signal and does not lack any picture element data, so that it has a very large amount of information. Meanwhile, assuming that a contour exist obliquely on a frame thereby to give rise to the oblique contour concerning red as explained before, a similar oblique contour will exist concerning also the green color. Herein, when as to the digital R signal, the output data A, A or AS of the
mean value circuit - 14. This fact holds true for the digital B signal. In contrast, let it be assumed that, as illustrated in the figure, the digital G signal changes abruptly in this contour part, between the picture element data Gℓ, n-1 of the digital G signal corresponding to the picture element in which the digital R signal has the picture element data Rℓ, n-1 (hereinbelow, the same suffixes shall be assigned to the picture element data items of the respective digital color signals of an identical picture element) and the picture element data Gℓ, n. Then, in the case where the aforementioned mean values are used as the interpolation data items for the lacking parts Xℓ, n of the digital R and G signals as described above, the value of the picture data Gℓ, n of the digital G signal is greater as compared with the values of the interpolation data items, and hence, the contour in the oblique direction becomes greenish on the printed frame.
- As the contour, it is more preferable to be fringed in black rather than to be colored in green in this manner. To this end, in the case where the digital G signal changes as shown in Fig. 14, also the digital R signal should better be changed as indicated by a solid line, not by a dotted line. In this case, the picture element data Rℓ, n+1 is employed as the interpolation data of the lacking part Xe nof the digital R signal.
- In this way, in the case of the mode D in Table 2 mentioned above, the interpolation data items of the lacking parts of the digital R and G signals are determined according to the change of the digital G signal. As this interpolation data item, the data selector 23 selects one of the picture element data Rℓ, n-1 from the
latch circuit 101, the picture element data Rℓ, n+1 from theline memory 902 and the picture element data Rℓ+1 n from thelatch circuit 201 through select signals S0' and S1' in accordance with the change of the digital G signal. - There will now be explained the detection of the change of the digital G signal and the selecting operation of the data selector.23 responsive to this change.
- The digital G signal read out from the
frame memory 302 is supplied to theshift register portion 24, and one picture element data item is stored in each of the shift registers 241, 242 and 243. Here, the shift registers 241, 242 and 243 store the picture element data items of the digital G signal at the same picture element positions as those of data items which are being read out from theline memories line memory 902 be the picture element data Rℓ, n+1, the picture element data Gℓ, +1 is being stored in theshift register 242. On this occasion, thelatch circuit 252 latches the picture element data Gℓ, n on the same line Lℓ as that of the picture element data Gℓ, n+1 and preceding by one dot, and thelatch circuit 26 latches the picture element data Gℓ, n-1 preceding by one more dot. In addition, theshift register 243 stores the picture element data Gℓ-1, n+1 of the line Lℓ-1, and thelatch circuit 253 latches the picture element data Gℓ-1, n preceding by one dot. The positional relations of these picture element data items and the storing circuits are shown in Fig. 15 in correspondence with Fig. 13. The storing circuits are indicated by suffixes. - The
level comparison portion 27 subjects the output data items of thelatch circuits level comparison portion 21. - More specifically, the
comparator circuit 270 compares the output data items Gℓ, n and Gℓ, n-1 of therespective latch circuits comparator circuit 271 compares the output data items Gℓ,n and Gℓ-1, n of therespective latch circuits - As seen from Fig. 15, ΔGV denotes the change of picture element data items in the vertical direction (along the line), and ΔGH the change of picture element data items in the horizontal direction.
- In Table 3, in the case of the mode E, the horizontal and vertical changes of the picture element data items of the digital G signal are small in relation to the lacking part Xℓ, n of the digital R signal. In this case, the digital G signal changes little and no contour exists as to this signal.
- The data selector 23 selects the input D0', namely, the picture element data Rℓ, n-1 delivered by the latch circuit 10' and supplies it to the D3 input end of the
data selector 22. When both the inputs So and S1 of thedata selector 22 are "1", that is, when the digital R signal has the oblique contour, thedata selector 22 uses as the interpolation data of the lacking part Xℓ, n the picture element data Rℓ, n-1 on the same line Lℓ and directly preceding the lacking part Xℓ, n and delivers it as an output ZR. This corresponds to pre-holding in which the picture element data Rℓ, n-1 is held and is supplemented to the lacking part Xℓ, n - The picture element data Rℓ, n-1 may well be replaced with picture element data Rℓ-1, n as the interpolation data. This measure signifies pre-holding in the direction orthogonal to the line (namely, in the horizontal direction).
- When the lacking part of the digital R signal is subjected to the data interpolation in this manner, the color change on the printed frame becomes abrupt to clarify the contour of the color.
- In the mode F, the change of picture element data in the line direction (vertical direction) as to the digital G signal is great. In this case, the data selector 23 selects the picture element data Rℓ, n+1 (D1' input) along the line Lℓ of the lacking part Xℓ, n of the digital R signal and directly succeeding the lacking part and delivers it to the
data selector 22.. When both the inputs S0 and S1 are "1", thedata selector 22 delivers the picture element data Rℓ, n+1 supplied from said data selector 23, as interpolation data for the lacking part Xn,ℓ. Thus, the contour concerning the digital R signal and the contour concerning the digital G signal are registered on the printed image, and they are made abrupt to equal extents so as to clarify the contours of the colors on the printed image. That is, the contours are not colored in green by way of example but become rather blackish. - In the mode G, picture element data items change greatly in the direction of adjacent lines (in the horizontal direction) as to the digital G signal. In this case, the data selector 23 selects the picture element data Rℓ+1, n of the line Lℓ+1 directly succeeding the line Lℓ where the lacking part Xℓ, n exists, and it supplies the selected data to the data selector 22: When both the inputs S0 and S1 are "1", the
data selector 22 delivers the picture element data Rℓ+1, n supplied from the data selector 23, as interpolation data for the lacking part x n. Thus, the same effects as in the mode F are attained. - The mode H is a case where the oblique contour exists concerning the digital G signal. In this case, as in the case of the mode G, the picture element data Rℓ+1, n (the D3 1 input of the data selector 23) as the interpolation data of the lacking part Xℓ, n of the digital R signal. This is intended to attain the same effects as in the mode F, and the picture element data Rℓ+1, n may well be replaced with the picture element data Rℓ, n+1 directly succeeding the lacking part Xℓ, n of the line Lℓ.
- As described above, in the case where the lacking part Xℓ n of the digital R signal registers with the oblique contour, the interpolation data of this lacking part Xℓ, is set according to the change of the digital G signal which has the large amount of information with no data omitted, whereby the contour in the printed image becomes clear without being colored. Besides, contours in the horizontal and vertical directions concerning the digital R signal can be clearly reproduced. Needless to say, the data interpolation processing stated above is similarly executed for the digital B signal.
- Although, in this practicable example, the processes of holding and operating various data items and the function of selecting data have been realized with hardware, they may well be realized with software by the use of a microcomputer or the like.
- In the
level comparison portions level comparison portions comparator circuits - Further, it is a matter of course that, as in the preceding practicable examples, the first and last lacking parts of each line may be supplemented or that the first and last dots of each line and the first and last lines may be similarly made white on the printing paper.
- Although, in the embodiments, the R and B signals are multiplexed and stored in the identical frame memory, they may well be stored in individual memories, and if necessary, the sampling rate may well be lowered for only the B signal by way of example so as to reduce the capacity of the memory.
Claims (23)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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JP60096601A JPS61256886A (en) | 1985-05-09 | 1985-05-09 | Video printer |
JP96601/85 | 1985-05-09 |
Publications (2)
Publication Number | Publication Date |
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EP0202536A2 true EP0202536A2 (en) | 1986-11-26 |
EP0202536A3 EP0202536A3 (en) | 1989-05-24 |
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Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP86106191A Withdrawn EP0202536A3 (en) | 1985-05-09 | 1986-05-06 | Signal processing circuit for a color video printer |
Country Status (3)
Country | Link |
---|---|
US (1) | US4734759A (en) |
EP (1) | EP0202536A3 (en) |
JP (1) | JPS61256886A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0316946A2 (en) * | 1987-11-19 | 1989-05-24 | Shinko Electric Co. Ltd. | Video signal hard copying apparatus |
DE3910035A1 (en) * | 1988-03-29 | 1989-10-12 | Mitsubishi Electric Corp | COLOR IMAGE SENSOR |
DE3919726A1 (en) * | 1988-06-16 | 1989-12-21 | Hallmark Cards | METHOD AND ARRANGEMENT FOR PRODUCING COLOR IMAGE REPRODUCTIONS |
DE3943762C2 (en) * | 1988-03-29 | 1997-03-06 | Mitsubishi Electric Corp | Image scanner for colour original |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2573925B2 (en) * | 1985-07-16 | 1997-01-22 | 富士写真フイルム株式会社 | Image hard copy making device |
US5220418A (en) * | 1986-05-21 | 1993-06-15 | Canon Kabushiki Kaisha | Image processing apparatus which thins out predetermined color signals |
JPS631276A (en) * | 1986-06-20 | 1988-01-06 | Olympus Optical Co Ltd | Color image pickup device |
US4837614A (en) * | 1986-08-20 | 1989-06-06 | Ricoh Company, Ltd. | Color image processing method |
US4905079A (en) * | 1986-10-28 | 1990-02-27 | Canon Kabushiki Kaisha | Color image processing apparatus for processing separated color signals |
US4985760A (en) * | 1987-10-09 | 1991-01-15 | Canon Kabushiki Kaisha | Color imager having varying filter aperture sizes to compensate for luminance differences between colors |
US4958218A (en) * | 1987-12-16 | 1990-09-18 | Canon Kabushiki Kaisha | Image processing method and apparatus with dot-processing |
US4876590A (en) * | 1988-06-17 | 1989-10-24 | Eastman Kodak Company | Low resolution verifier for a still video image |
JPH03153193A (en) * | 1989-11-10 | 1991-07-01 | Fuji Photo Film Co Ltd | Solid-state image pickup device |
JP2942903B2 (en) * | 1990-11-05 | 1999-08-30 | キヤノン株式会社 | Digital camera signal processor |
US5479534A (en) * | 1990-11-29 | 1995-12-26 | Konica Corporation | Image reading apparatus |
US5157517A (en) * | 1991-04-29 | 1992-10-20 | E. I. Du Pont De Nemours And Company | Parallel interpolator for high speed digital image enlargement |
US5742409A (en) * | 1995-10-18 | 1998-04-21 | Umax Data System Inc. | Apparatus for pixel insertion in optical scanners |
US5828349A (en) * | 1996-09-06 | 1998-10-27 | International Business Machines Corporation | Method and system for multiplexing and demultiplexing video signals for graphic display monitors in computer systems |
JPH1093762A (en) * | 1996-09-18 | 1998-04-10 | Fuji Photo Film Co Ltd | Image data storing method and device therefor |
US6904169B2 (en) * | 2001-11-13 | 2005-06-07 | Nokia Corporation | Method and system for improving color images |
Citations (3)
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GB2026811A (en) * | 1978-08-04 | 1980-02-06 | Dainippon Screen Mfg | Colour facsimile system employing reduced capacity memory |
US4356555A (en) * | 1978-03-24 | 1982-10-26 | Ricoh Co., Ltd. | Method of restoring a picture cell by estimation with high density |
GB2114853A (en) * | 1982-02-09 | 1983-08-24 | Dainippon Screen Mfg | A method for scanning simultaneously a plurality of adjacent scanning lines of an original |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
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US4176373A (en) * | 1977-07-06 | 1979-11-27 | Eastman Kodak Company | Signal processing for discrete-sample-type-color-video signal |
JPS5664884A (en) * | 1979-11-02 | 1981-06-02 | Sony Corp | Color hard copying apparatus |
JPS581391A (en) * | 1981-06-26 | 1983-01-06 | Sony Corp | Color image pickup device |
JPS5846908B2 (en) * | 1981-08-11 | 1983-10-19 | 株式会社富士通ゼネラル | Television imaging method |
JPS5848591A (en) * | 1981-09-18 | 1983-03-22 | Matsushita Electric Ind Co Ltd | Picture memory controller |
JPS58181385A (en) * | 1982-05-17 | 1983-10-24 | Victor Co Of Japan Ltd | Digital video signal recording system |
JPS5937792A (en) * | 1982-08-25 | 1984-03-01 | Sony Corp | Digitizing device of component video signal |
US4605956A (en) * | 1984-09-10 | 1986-08-12 | Eastman Kodak Company | Single-chip electronic color camera with color-dependent birefringent optical spatial frequency filter and red and blue signal interpolating circuit |
US4642678A (en) * | 1984-09-10 | 1987-02-10 | Eastman Kodak Company | Signal processing method and apparatus for producing interpolated chrominance values in a sampled color image signal |
-
1985
- 1985-05-09 JP JP60096601A patent/JPS61256886A/en active Pending
-
1986
- 1986-05-05 US US06/859,808 patent/US4734759A/en not_active Expired - Lifetime
- 1986-05-06 EP EP86106191A patent/EP0202536A3/en not_active Withdrawn
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4356555A (en) * | 1978-03-24 | 1982-10-26 | Ricoh Co., Ltd. | Method of restoring a picture cell by estimation with high density |
GB2026811A (en) * | 1978-08-04 | 1980-02-06 | Dainippon Screen Mfg | Colour facsimile system employing reduced capacity memory |
GB2114853A (en) * | 1982-02-09 | 1983-08-24 | Dainippon Screen Mfg | A method for scanning simultaneously a plurality of adjacent scanning lines of an original |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0316946A2 (en) * | 1987-11-19 | 1989-05-24 | Shinko Electric Co. Ltd. | Video signal hard copying apparatus |
EP0316946A3 (en) * | 1987-11-19 | 1990-03-21 | Shinko Electric Co. Ltd. | Video signal hard copying apparatus |
DE3910035A1 (en) * | 1988-03-29 | 1989-10-12 | Mitsubishi Electric Corp | COLOR IMAGE SENSOR |
DE3943762C2 (en) * | 1988-03-29 | 1997-03-06 | Mitsubishi Electric Corp | Image scanner for colour original |
DE3919726A1 (en) * | 1988-06-16 | 1989-12-21 | Hallmark Cards | METHOD AND ARRANGEMENT FOR PRODUCING COLOR IMAGE REPRODUCTIONS |
US5018085A (en) * | 1988-06-16 | 1991-05-21 | Hallmark Cards, Inc. | Color printing system usable for reproduction of computer-generated images |
Also Published As
Publication number | Publication date |
---|---|
EP0202536A3 (en) | 1989-05-24 |
JPS61256886A (en) | 1986-11-14 |
US4734759A (en) | 1988-03-29 |
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