EP0195998A2 - Anzeigesteuergerät - Google Patents

Anzeigesteuergerät Download PDF

Info

Publication number
EP0195998A2
EP0195998A2 EP86103631A EP86103631A EP0195998A2 EP 0195998 A2 EP0195998 A2 EP 0195998A2 EP 86103631 A EP86103631 A EP 86103631A EP 86103631 A EP86103631 A EP 86103631A EP 0195998 A2 EP0195998 A2 EP 0195998A2
Authority
EP
European Patent Office
Prior art keywords
address data
address
display
signal
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP86103631A
Other languages
English (en)
French (fr)
Other versions
EP0195998B1 (de
EP0195998A3 (en
Inventor
Takatoshi Okumura
Shigemitsu Yamaoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yamaha Corp
Original Assignee
Yamaha Corp
Nippon Gakki Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP60056603A external-priority patent/JPS61214878A/ja
Priority claimed from JP60056604A external-priority patent/JPH0727358B2/ja
Application filed by Yamaha Corp, Nippon Gakki Co Ltd filed Critical Yamaha Corp
Publication of EP0195998A2 publication Critical patent/EP0195998A2/de
Publication of EP0195998A3 publication Critical patent/EP0195998A3/en
Application granted granted Critical
Publication of EP0195998B1 publication Critical patent/EP0195998B1/de
Expired legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/391—Resolution modifying circuits, e.g. variable screen formats
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/18—Timing circuits for raster scan displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0442—Handling or displaying different aspect ratios, or changing the aspect ratio

Definitions

  • This invention relates generally to a display controller for displaying an image on a screen of a scanning-type display unit such as a CRT display unit, and in particular to such a display controller in which an aspect ratio of the displayed image can be changed.
  • a display controller adapted to be connected to a central processing unit and a color television set or a display unit to display an image representative of a variety of information.
  • the color television set connected to such a display controller may be one of those manufactured in accordance with NTSC, PAL and SECAM standards.
  • a display of image according to NTSC standard uses 262 or 525 horizontal scanning lines, while a display of image according to either of PAL and SECAM standards uses 313 or 625 horizontal scanning lines.
  • the NTSC image is converted into a PAL image in such a manner that the number of horizontal scanning lines is simply increased to "625", leaving the width of the image in the horizontal direction unchanged.
  • a display area F N on the screen provided in accordance with NTSC standard shown in Fig. 1 and a display area on the screen provided in accordance with PAL standard shown in Fig. 2 differ in aspect ratio from each other. More specifically, even if a horizontal width H N of the NTSC display area F N is rendered equal to a horizontal width Hp of the PAL display display area Fp, a vertical width Vp of the PAL display area Fp is 0.84 times shorter than a vertical width V of the NTSC display area FN. As a result, when an NTSC image is converted into a PAL image in accordance with the aforesaid conversion method, the vertical width of the resultant PAL image is decreased.
  • Fig. 3 when an NTSC image representative of a circle shown in Fig. 3 is converted into a PAL image in the conventional method, an ellipse shown in Fig. 4 is displayed.
  • reference characters P represent intensified dots on the screen.
  • the converted image is thus deformed is that the NTSC image and the PAL image differ in aspect ratio from each other.
  • the vertical width of a display area containing 190 horizontal scanning lines is 163 mm
  • the width of a display area containing 190 horizontal scanning lines is 142 mm.
  • the vertical width of an image displayed on the PAL-type display unit is 0.871 (or 142/163) times shorter than that of an image displayed on the NTSC-type display unit.
  • the vertical compaction ratio of the image converted from NTSC to PAL is 0.871.
  • the conventional display controller is also disadvantageous in that when an image, of which data is provided for a specific display unit, is displayed on another display unit different in screen size or display characteristic from the specific display unit, the image is liable to be deformed. And in particular, when the image contains characters and when the screen is smaller, the displayed characters are not easy to see because of the small spaces between the characters.
  • a display controller provided in accordance with a first embodiment of the invention will now be described.
  • the display controller 10 is connected to a video memory (hereinafter referred to as "V-RAM") 11 and a CRT display unit 12 of a PAL-type.
  • V-RAM 11 is written, by an extemal control unit such as a central processing unit (not shown), with image data provided in accordance with NTSC standard and representative of, for example, characters or graphic image.
  • the image data are sequentially read from the V-RAM 11 on an eight-bit basis in accordance with seven-bit column or horizontal address data A 0 to A 6 and eight-bit row or vertical address data A, to A 14
  • the column address data A o to A 6 and the row address data A, to A 14 are generated by a horizontal counter 13 and a vertical counter 14, respectively.
  • the horizontal counter 13 is arranged so as to have a count range of between "0" and "3 4 1" (decimal) and the vertical counter 14 is arranged so as to selectively have a count range of between "0" and "26 1 " (decimal) and a count range of between "0" and "312".
  • the horizontal counter 13 counts clock pulses CP applied to a clock terminal CK thereof, of which period corresponds to a time interval required to display each of dots constituting an image on the display unit 12, to output a nine-bit count output HQ 0 to HQ 8 .
  • the seven bits HQ, to HQ, of the count output of the horizontal counter 13 are supplied to the V-RAM 11 as the column address data A 0 to A 6 , and an eight-bit count output VQ 0 to VQ, of the vertical counter 14 is supplied to the V-RAM 11 as the row address data A, to A
  • All the bits HQ o to Has of the count output of the horizontal counter 13 are supplied to a decoder 15 which outputs a "1" signal to a delay circuit 16 when the supplied count output is equal to "340" in decimal, that is to say, one clock pulse CP before the horizontal counter 13 outputs the final count output equal to "341".
  • the "1" signal outputted from the decoder 15 is delayed at the delay circuit 1 6 by a time interval equal to one cycle of the clock pulse CP, and thence supplied to a reset terminal R of the horizontal counter 13 and to a correction circuit 17.
  • the correction circuit 17 is arranged such that an additional horizontal scanning lines are provided on the screen of the display unit 12 at a predetermined interval in the vertical direction and that an appropriate portion of the image data is read from the V-RAM 11 for each additional horizontal scanning line.
  • the correction circuit 17 will now be more fully described.
  • the lower three bits VQ 0 to VQ z of the count output of the vertical counter 14 are supplied to input terminals of a three-input AND gate 18, and the bits VQ, and VQ 2 and an inversion of the lowermost bit VQ 0 by an inverter 19 are supplied to input terminals of another three-input AND gate 20.
  • the AND gate 18 outputs a "1" signal when the lower three bits VQ 0 to VQ 2 are “1", "1" and “1", respectively
  • the AND gate 20 outputs a "1” signal when the lower three bits VQ 0 to VQ 2 are "0", "1” and “1", respectively.
  • the output signals of the AND gate 18 and the delay circuit 16 are supplied to input terminals of a two-input AND gate 21.
  • An output of this AND gate 21 is supplied to a reset terminal R of an RS flip-flop (hereinafter referred to as "FF") 22. Also, the output of the AND gate 20 and the output of the delay circuit 16 are supplied to an AND gate 24 to form a logical product thereof which is supplied to a set terminal S of the FF 22. A non-inverted output Q of the FF 22 is delayed at a delay circuit 26 by a time interval equal to one cycle of the clock pulse CP and thence supplied to a first input terminal of a three-input AND gate 28.
  • FF RS flip-flop
  • Second and third input terminals of the AND gate 28 are supplied respectively with an output signal NV, of a decoder 30, which decodes the count output VQ 0 to VQ, of the vertical counter 14, and an aspect ratio selection signal Ac applied to a control input terminal 32 of this display controller 10.
  • the signal NV is rendered “1" when the value of the count output of the vertical counter 14 is between "0" and "191", that is to say, when the actual display area on the screen is scanned.
  • a logical product of the output of the delay circuit 26 and the signals NV, and Ac formed by the AND gate 28 is inverted by an inverter 34, and thence supplied together with the output of the delay circuit 16 to input terminals of an AND gate 36.
  • An output of this AND gate 36 is supplied to a clock input terminal CK of the vertical counter 14.
  • the decoder 30 is arranged so as to output to input terminals I A and I B of a selector 38 two change-over signals PA and NT which correspond respectively to PAL and NTSC standards.
  • the signal PA is rendered “1” when the count output of the vertical counter 14 represents “288” in decimal, while the signal NT is rendered “1” when "261".
  • the selector 38 outputs the change-over signal PA when the signal Sa in the state of "1" is supplied to a selection terminal S A thereof, and outputs the change-over signal NT when the signal Sa is in the state of "0".
  • the decoder 30 also outputs a signal NV 2 , which corresponds to NTSC standard and is rendered “1” when the value of the count output of the vertical counter 14 is between “219” and “221” in decimal, and a signal NV, which corresponds to PAL standard and is rendered “1” when the value of the count output of the vertical counter 14 is between "244" and "246".
  • the signals NV 2 and NV 3 outputted from the decoder 30 are supplied to input terminals I B and I A of a selector 40.
  • the selector 40 outputs the signal NV 3 as a vertical synchronization signal V when the signal Ac is in a "1" state, and outputs the signal NV 2 as the vertical synchronization signal V when the signal Ac is in a "0" state.
  • the count output of the horizontal counter 13 is decoded by a decoder 42 which outputs a signal NH, for use as a horizontal synchronization signal H when the count output is between "277” and "301”, and outputs a signal NH 2 when the count output is between "0" and "255”.
  • the vertical synchronization signal V is combined by an exclusive-OR (EXOR) gate 44 with the horizontal synchronization signal H to form a composite synchronization signal CSYNC which is supplied to the CRT display unit 12.
  • EXOR exclusive-OR
  • each eight-bit image data, which contains two color codes, read from the video memory 11 is loaded into a register 48.
  • Upper half (four bits) of the loaded image data (or one of the two color codes) is supplied to an input terminal I A of a selector 50, and lower half thereof (the other of the two color codes) is supplied to another input terminal I B of the selector 50.
  • the selector 50 alternately outputs the two color codes in accordance with a signal S1 produced based on the bit HQ 0
  • Each of the color codes thus outputted from the selector 50 is supplied to a color palette 52 which in turn generates therefrom three color data RD, GD and BD representative of intensity levels of red, green and blue, respectively.
  • the color data RD, GD and BD are supplied respec- tivety to gate circuits 54, 56 and 58 which open when a logical product of the signals NHZ and NV, formed by an AND gate 60 is "1".
  • the color data RD, GD and BD passed respectively through the gate circuits 54, 56 and 58 are supplied to a digital-to-analog converter (hereinafter referred to as "DAC") 62.
  • the DAC 62 converts the color data RD, GD and BD into corresponding analog color signals R, G and B which are supplied to the CRT display unit 12.
  • the decoder 15 When the count output HQ 0 to HQ, applied to the decoder 15 becomes equal to "340", which is one count less than the last count "341", the decoder 15 outputs a "1" signal as shown in Fig. 6-(B).
  • the "1" signal is delayed by one clock time at the delay circuit 16, as shown in Fig. 6-(C), and supplied to the AND gates 21 and 24.
  • the AND gate 20 outputs a "1" signal.
  • the delay circuit 16 outputs the delayed "1" signal corresponding to the count output "340" of the horizontal counter 1 3
  • the AND gates 24 outputs a "1" signal to the set terminal S of the FF 22 (Fig. 6-(F)).
  • the FF 22 is brought into a set state, whereby the non-inverted output Q thereof is rendered “1", as shown in Fig. 6-(G).
  • the non-inverted output Q of the FF 22 is delayed at the delay circuit 26 by one clock time, as shown in Fig.
  • the AND gate 28 When the AND gate 28 is supplied at the first input terminal thereof with the "1" signal outputted from the delay circuit 26, the AND gate 28 outputs a "1" signal, since the signal Ac is in the “1” state, as described above, and the signal NV, is “1" in the actual display period.
  • the "1" signal outputted from the AND gate 28 is inverted by the inverter 34 and supplied to the AND gate 36 to disable the AND gate 36.
  • the delay circuit 16 When the value of the count output of the horizontal counter 13 again becomes equal to "340" during the scanning of the eighth horizontal line (Fig. 6-(B)), the delay circuit 16 outputs a "1" signal, so that the AND gate 21 opens to reset the FF 22, as shown in Fig. 6-(G). fn the normal condition, the "1" signal outputted from the delay circuit 1 6 is supplied to the clock terminal CK of the vertical counter 14 through the AND gate 36. However, the AND gate 36 is closed at present as described above, so that the "1" signal outputted from the delay circuit 16 is prevented from being supplied to the vertical counter 14. As a result the count output of the vertical counter 14 or the row address of the V-RAM 11 remains unchanged.
  • the same image data as read for the eighth horizontal scanning line will be again sequentially read from the V-RAM 11 in accordance with the count of the clock pulses CP by the horizontal counter 13.
  • the image data thus read from the V-RAM 11 are supplied through-the register 48, selector 50, color palette 52 and the DAC 62 to the CRT display unit 12.
  • the AND gate 36 opens (Fig. 6-(K)) since the output of the inverter 34 is in the state of "1" at this time. And therefore, the vertical counter 14 is triggered to increment the row address of the V-RAM 11 so that the image data for the next horizontal scanning line are read from the V-RAM 11. Thus, one horizontal scanning line is added every eight horizontal scanning lines on the screen.
  • Table 1 shows the relation between the count output of the vertical counter 14 and the variation of the row address of the V-RAM 11 . And, when the least significant three bits of the row address become equal to "1", "1" and "1", the count operation of the vertical counter 14 is interrupted and one horizontal scanning line is added.
  • Fig. 7 shows the actual display area BD on the screen of the CRT display unit 1 2.
  • H represents a lefthand horizontal retrace-line period
  • H 2 a horizontal actual display period
  • H 3 a right-hand horizontal retrace-line period
  • H4 a horizontal synchronization signal period
  • V 1 an upper vertical retrace-line period
  • V 2 a vertical actual display period
  • V 3 a lower vertical retrace-line period
  • V 4 a vertical synchronization signal period.
  • the actual display area BD is thus defined by the horizontal actual display period H 2 and the vertical actual display period V 23 and horizontal scanning lines are added in the actual display area BD at the predetermined positions, for example, next to the eighth horizontal scanning line, next to the sixteenth scanning line and so on, as indicated by broken lines in Fig. 8, wherein solid lines indicate normal horizontal scanning lines.
  • the signal Ac is held in the "0" state.
  • the selector 38 outputs the signal NT to the vertical counter 14, so that the maximum count of the vertical counter 14 becomes equal to "262" in decimal.
  • the signal Ac in the state of "0” closes the AND gate 28, and therefore the count output of the vertical counter 14 is incremented by one each time the count output of the horizontal counter 13 reaches "340" in deci- maf, so that no addition of horizontal scanning lines is performed.
  • the selector 40 outputs the signal NV 2 , so that the composite synchronization signal CSYNC produced in this case conforms to NTSC standard.
  • image data based on NTSC standard can be converted into image data based on PAL standard without the aid of processing by a complicated and troublesome software.
  • display controller 10 twenty four horizontal scanning lines are added in the actual display area of the screen, so that the bottom portion of the displayed image can be disposed outside of the bottom edge of the screen.
  • this can be easily corrected.
  • the characters in the case of displaying 8 x 8 dot-matrix characters such as those ("P", "A” and so on) shown in Fi g. 10, the characters can be displayed in an easy-to-see manner by adding one horizontal scanning line to each of those horizontal scanning lines which correspond to the bottom rows of dots of the characters (every eight scanning lines in this case), as shown in Fig. 11. In this case, deterioration of shape of each character can also be prevented.
  • the above embodiment can easily be modified so that horizontal scanning lines are added at any desired positions on the screen and that the number of additional scanning lines can be set to any desired value.
  • an image represented by the same data can be displayed on the screen at any desired aspect ratio.
  • a display controller 10a which differs from the display controller 10 of Fig. 5 in the following respects.
  • a horizontal counter 13 is arranged so as to selectively have count ranges of between “0” and “341” and between “0” and “313", while a vertical counter 14 has a count range of between “0” and “261 ".
  • All bits HQ 0 to HQ 8 of the count output of the horizontal counter 13 are supplied to a decoder 15a which outputs "1" signals when the supplied count output becomes equal to "312" and "340", respectively.
  • the two signals representative respectively of the counts "312” and "340” are supplied to input terminals I A and I B of a selector 70.
  • the selector 70 output one of the two input signals in accordance with a signal Acc supplied through a terminal 32a to a selection terminal S A thereof.
  • the output signal from the selector 70 is delayed at a delay circuit 16a by a time interval equal to one cycle of the clock pulses CP, and thence supplied to a reset terminal R of the horizontal counter 13 and a clock terminal CK of the vertical counter 14.
  • the count range of the horizontal counter 13 is set to "314" when the signal Acc is in the state of "1", while the count range is set to "342" when the signal Acc is in the state of "0".
  • the count output HQ 0 to HQ 8 of the horizontal counter 13 is also supplied to a decoder 42a which decodes the supplied count output and outputs four signals HN,, HN 2 HN z and HN 4 .
  • the signal HN becomes “1” when the count output HQ 0 to HQ, is between “0” and “255”, and the signal HN 2 becomes “1” when the count output is between “0” and “277”.
  • the signal HN 3 becomes “1” when the count output HQ 0 to HQ 8 is between “261” and “286”, and the signal HN 2 becomes “1” when the count output is between "289” and "314".
  • the count output VQ 0 to VQ is supplied to a decoder 30a which decodes the supplied count output to produce signals VN,, VN z and VN m .
  • the signal VN becomes “1” when the count output VQ 0 to VQ, is between “0” and “191”, and the signal VN 2 becomes “1” when the count output is between “219” and “221”.
  • the signal VN m becomes “1” when the count output VQ 0 to VQ, is equal to "262".
  • the signal VN m is supplied to a reset terminal R of the vertical counter 14, so that the count range of this counter 14 is "264".
  • the signals HN, and HN 2 are supplied respectively to input terminals I A and 1 B of a selector 71.
  • the selector 71 outputs the signal HN, when the signal Acc applied to a selection terminal S A thereof is in the state of "1", and outputs the signal HN 2 when the signal Acc is in the state of "0".
  • the output of the selector 71 is supplied to a first input terminal of an AND gate 60 of which second input terminal is supplied with the signal VN,.
  • the signals HN 3 and HN 4 are supplied respectively to input terminals I A and I B of a selector 72.
  • the selector 72 outputs the signal HN 2 when the signal Acc applied to a selection terminal S A thereof is in the state of "1", and outputs the signal HN 4 when the signal Ace is in the state of "0".
  • the output from the selector 72 is supplied as a horizontal synchronization signal H to a first input terminal of an EXOR gate 44 whose second input terminal is supplied with the signal VH 2 or a vertical synchronization signal V.
  • the output of the EXOR gate 44 is supplied to a CRT display unit 12a as a composite synchronization signal CSYNC.
  • the bits HQ, and HQ z of the count output of the horizontal counter 13 and an inversion of the least significant bit HQ 0 by an inverter 19a are supplied to input terminals of an AND gate 73 provided in a correction circuit 74.
  • the AND gate 73 outputs a "1" signal which is delayed at a delay circuit 74 by a time interval equal to one clock cycle of the clock pulses CP.
  • the signal outputted from the delay circuit 74 is supplied to a first input terminal of a three-input AND gate 75 whose second and third input terminals are supplied respectively with the output signal of the selector 71 and the signal Acc.
  • An output of the AND gate 75 is inverted by an inverter 76 and thence supplied to a first input terminal of an AND gate 77 whose second input terminal is supplied with the clock pulses CP.
  • a selector 50 is supplied at a selection terminal S A thereof with a selection signal S 2 . and selectively outputs two color codes fed from a register 48 in accordance with the selection signal S 2 .
  • the selection signal S 2 is derived from, for example, the output of the inverter 19a.
  • the signal Acc is now in the state of "1" in order that additional display dots are provided in each horizontal scanning line at a predetermined interval (every eight display dots, in this case).
  • the AND gate 73 outputs a "0" signal, and therefore, the AND gate 75 is closed, so that the AND gate 77 is enabled to open.
  • the horizontal counter 13 is triggered by the clock pulses CP.
  • the AND gate 73 When the least significant three bits HO., HQ, and H0 2 become equal respectively to "0", "1” and "1”, that is to say, if the dot currently displayed is one of those dots in a horizontal scanning line which correspond to the seventh dot, fourteenth dot and so on, the AND gate 73 outputs a "1" signal which is supplied to the first input terminal of the AND gate 75 one clock time later.
  • the AND gate 75 opens to output a "1" signal when the least significant three bits HO., HQ, and HQ 2 are equal respectively to “ 1 ", " 1 " and “1”, that is to say, when one of those dots in a horizontal scanning line which correspond to the eighth dot, sixteenth dot and so on, is displayed.
  • the "1" signal outputted from the AND gate 75 is inverted by the inverter 76 and supplied to the AND gate 77 to close it. And therefore, the clock pulse CP is prevented from being supplied to the clock terminal CK of the vertical counter 13, so that the contents of the vertical counter 13 will not be incremented when one of those dots in a horizontal scanning line which correspond to the eighth dot, sixteenth dot and so on is displayed. Consequently, when the next dot or an additional dot is displayed, the same color codes as those presently stored in the register 48 will be read from the V-RAM 11. And therefore, the additional dot, that is, one of those dots which come next to the eighth dot, sixteenth dot and so on, will be displayed in the same color as the dot presently displayed on the screen. When the additional dot is displayed, the output of the delay circuit 7 4 is "0", so that the AND gate 77 is enabled to open. And therefore, the horizontal counter 1 3 is triggered by the clock pulse CP.
  • the horizontal counter 13 When the count output of the horizontal counter 13 reaches "312", the horizontal counter 13 is reset to "0" to display dots on the next horizontal scanning line.
  • the AND gate 75 When the signal Acc is held in the "0" state, the AND gate 75 is closed, so that the horizontal counter 13 is triggered each time the clock pulse CP is generated. When the count output of the horizontal counter 13 reaches "340", the selector 70 outputs a "1" signal to reset the horizontal counter 13. Thus, no display dot is added in this case.
  • the characters in the case of displaying 8 x 8 dot-matrix characters such as those ("P", "A” and so on) shown in Fig. 1 0, the characters can be displayed in an easy-to-see manner by providing additional display dots in each horizontal scanning line next to those dots which correspond to the right-hand end dots of the characters (or every eight dots in the horizontal scanning line), as shown in Fig. 13.
  • the above embodiment can easily be modified so that display dots are added at any desired positions in each horizontal scanning line and that the number of additional dots can be set to any desired value.
  • an image represented by the same data can be displayed on the screen at any desired aspect ratio.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Multimedia (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Controls And Circuits For Display Device (AREA)
EP19860103631 1985-03-20 1986-03-18 Anzeigesteuergerät Expired EP0195998B1 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP56603/85 1985-03-20
JP60056603A JPS61214878A (ja) 1985-03-20 1985-03-20 画像表示装置
JP60056604A JPH0727358B2 (ja) 1985-03-20 1985-03-20 画像表示装置
JP56604/85 1985-03-20

Publications (3)

Publication Number Publication Date
EP0195998A2 true EP0195998A2 (de) 1986-10-01
EP0195998A3 EP0195998A3 (en) 1988-10-05
EP0195998B1 EP0195998B1 (de) 1991-08-07

Family

ID=26397556

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19860103631 Expired EP0195998B1 (de) 1985-03-20 1986-03-18 Anzeigesteuergerät

Country Status (2)

Country Link
EP (1) EP0195998B1 (de)
DE (1) DE3680693D1 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0465063A2 (de) * 1990-06-22 1992-01-08 Mitsubishi Denki Kabushiki Kaisha Fernsehbildverarbeitungsvorrichtung

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4303986A (en) * 1979-01-09 1981-12-01 Hakan Lans Data processing system and apparatus for color graphics display
EP0043703A2 (de) * 1980-07-03 1982-01-13 General Electric Company Einrichtung zum Steuern eines nach dem Zeilentasterverfahren arbeitenden Sichtgeräts
GB2087696A (en) * 1980-09-22 1982-05-26 Nippon Electric Co Display controlling apparatus
EP0082746A2 (de) * 1981-12-17 1983-06-29 AlliedSignal Inc. Adressengenerator
GB2145308A (en) * 1983-08-16 1985-03-20 Ibm Display selection in a raster scan display system

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4303986A (en) * 1979-01-09 1981-12-01 Hakan Lans Data processing system and apparatus for color graphics display
EP0043703A2 (de) * 1980-07-03 1982-01-13 General Electric Company Einrichtung zum Steuern eines nach dem Zeilentasterverfahren arbeitenden Sichtgeräts
GB2087696A (en) * 1980-09-22 1982-05-26 Nippon Electric Co Display controlling apparatus
EP0082746A2 (de) * 1981-12-17 1983-06-29 AlliedSignal Inc. Adressengenerator
GB2145308A (en) * 1983-08-16 1985-03-20 Ibm Display selection in a raster scan display system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0465063A2 (de) * 1990-06-22 1992-01-08 Mitsubishi Denki Kabushiki Kaisha Fernsehbildverarbeitungsvorrichtung
EP0465063A3 (en) * 1990-06-22 1992-10-28 Mitsubishi Denki Kabushiki Kaisha Television image processing apparatus
US5633655A (en) * 1990-06-22 1997-05-27 Mitsubishi Denki Kabushiki Kaisha Television image processing apparatus

Also Published As

Publication number Publication date
EP0195998B1 (de) 1991-08-07
DE3680693D1 (de) 1991-09-12
EP0195998A3 (en) 1988-10-05

Similar Documents

Publication Publication Date Title
US4760387A (en) Display controller
US4751502A (en) Display controller for displaying a cursor on either of a CRT display device or a liquid crystal display device
US4278972A (en) Digitally-controlled color signal generation means for use with display
US4628467A (en) Video display control system
EP0139932B1 (de) Einrichtung zur Abbildung eines Cursors
US4635048A (en) Video display controller
US5319446A (en) Test pattern signal generator
US4673930A (en) Improved memory control for a scanning CRT visual display system
CA1243138A (en) High speed memory access circuit of crt display unit
JPH08163457A (ja) オンスクリ−ン表示装置及びオンスクリ−ン表示方法
US4684942A (en) Video display controller
US5086295A (en) Apparatus for increasing color and spatial resolutions of a raster graphics system
EP0178897B1 (de) Anzeigegerät
EP0537881A2 (de) Graphischer Dekodierer
US4853681A (en) Image frame composing circuit utilizing color look-up table
US4868554A (en) Display apparatus
US4727423A (en) Video data processing circuit employing plural parallel-to-serial converters and look-up tables
US4720803A (en) Display control apparatus for performing multicolor display by tiling display
US4081799A (en) Character generation system for a visual display terminal
US5140312A (en) Display apparatus
US5068651A (en) Image display apparatus
US4231032A (en) Variable accuracy trend graph display apparatus
EP0195998A2 (de) Anzeigesteuergerät
US4554536A (en) Logic timing diagram display apparatus
US4853876A (en) Picture producing apparatus

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): DE GB NL

17P Request for examination filed

Effective date: 19870209

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: YAMAHA CORPORATION

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

AK Designated contracting states

Kind code of ref document: A3

Designated state(s): DE GB NL

17Q First examination report despatched

Effective date: 19900806

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE GB NL

REF Corresponds to:

Ref document number: 3680693

Country of ref document: DE

Date of ref document: 19910912

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed
REG Reference to a national code

Ref country code: GB

Ref legal event code: IF02

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: NL

Payment date: 20050303

Year of fee payment: 20

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20050310

Year of fee payment: 20

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20050316

Year of fee payment: 20

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF EXPIRATION OF PROTECTION

Effective date: 20060317

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: NL

Free format text: LAPSE BECAUSE OF EXPIRATION OF PROTECTION

Effective date: 20060318

REG Reference to a national code

Ref country code: GB

Ref legal event code: PE20

NLV7 Nl: ceased due to reaching the maximum lifetime of a patent

Effective date: 20060318