EP0194092A3 - Display system and method - Google Patents

Display system and method Download PDF

Info

Publication number
EP0194092A3
EP0194092A3 EP86301351A EP86301351A EP0194092A3 EP 0194092 A3 EP0194092 A3 EP 0194092A3 EP 86301351 A EP86301351 A EP 86301351A EP 86301351 A EP86301351 A EP 86301351A EP 0194092 A3 EP0194092 A3 EP 0194092A3
Authority
EP
European Patent Office
Prior art keywords
memory
data
display
pattern
object elements
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP86301351A
Other languages
German (de)
French (fr)
Other versions
EP0194092A2 (en
Inventor
Duncan Harrower
Stephen Maine
Abraham Mammen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Computer Graphics Laboratories Inc
Original Assignee
Computer Graphics Laboratories Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US06/705,367 priority Critical patent/US4760390A/en
Priority to US74083285A priority
Application filed by Computer Graphics Laboratories Inc filed Critical Computer Graphics Laboratories Inc
Publication of EP0194092A2 publication Critical patent/EP0194092A2/en
Publication of EP0194092A3 publication Critical patent/EP0194092A3/en
Priority to US705367 priority
Priority to US740832 priority
Application status is Withdrawn legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/399—Control of the bit-mapped memory using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/42—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of patterns using a display memory without fixed position correspondence between the display memory contents and the display position on the screen

Abstract

A graphic display system and method in which a large number of object elements can be stored in a pattern memory and called up for display in real time is described. The system comprises
A. a pattern memory (A) for storing data representing a plurality of object elements;
B. a system memory (B) for storing data identifying the plurality of object elements and data comprising instructions defining the nature and location of representations of the ob­ ject elements or parts thereof;
C. a third memory (C) for storing instructions as to the identity, nature and location of display of desired ones of the preselected object elements;
D. a buffer memory (F) for storing data corresponding to the desired representation of at least a portion of the scene;
E. first data processing means (D) operatively connected between said system memory (B), the pattern memory (A) and the third memory for transferring data therebetween;
F. second data processing means (E) operatively connect­ ed between the third memory (B), the pattern memory (A) and the buffer memory (F) for depositing in the buffer memory data from the pattern memory in response to instructions from the third memory; and
G. display means for causing the data in the buffer memory (F) to produce a display on the screen corresponding to the desired representation.
EP86301351A 1985-02-25 1986-02-25 Display system and method Withdrawn EP0194092A3 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US06/705,367 US4760390A (en) 1985-02-25 1985-02-25 Graphics display system and method with enhanced instruction data and processing
US74083285A true 1985-06-03 1985-06-03
US705367 2000-11-03
US740832 2003-12-22

Publications (2)

Publication Number Publication Date
EP0194092A2 EP0194092A2 (en) 1986-09-10
EP0194092A3 true EP0194092A3 (en) 1990-02-07

Family

ID=27107495

Family Applications (1)

Application Number Title Priority Date Filing Date
EP86301351A Withdrawn EP0194092A3 (en) 1985-02-25 1986-02-25 Display system and method

Country Status (2)

Country Link
EP (1) EP0194092A3 (en)
CA (1) CA1257719A (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4905168A (en) * 1986-10-15 1990-02-27 Atari Games Corporation Object processing for video system using slips and linked list
US4894774A (en) * 1986-10-15 1990-01-16 Mccarthy Patrick J Lookahead pipeline for processing object records in a video system
EP0312720A3 (en) * 1987-10-20 1990-06-13 Tektronix Inc. Double buffered graphics design system
US4862155A (en) * 1987-10-26 1989-08-29 Tektronix, Inc. Graphic display system with secondary pixel image storage
US5202672A (en) * 1987-12-30 1993-04-13 Namco Ltd. Object display system
JPH0670742B2 (en) * 1987-12-30 1994-09-07 株式会社ナムコ Target of the display device
JPH07134672A (en) * 1993-11-09 1995-05-23 Toshiba Corp Display data readout circuit
JPH11510620A (en) * 1995-08-08 1999-09-14 シーラス ロジック，インコーポレイテッド Integrated system / frame buffer memory and a system, and methods of use thereof
WO2001001386A1 (en) * 1999-06-30 2001-01-04 Aurora Systems Multistandard liquid crystal display with automatic adjustment of timing signals
JP2001103392A (en) 1999-09-29 2001-04-13 Nec Ic Microcomput Syst Ltd Image frame generating circuit and digital television system using it

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3996585A (en) * 1974-06-11 1976-12-07 International Business Machines Corporation Video generator circuit for a dynamic digital television display
US4317114A (en) * 1980-05-12 1982-02-23 Cromemco Inc. Composite display device for combining image data and method
GB2137856A (en) * 1983-04-06 1984-10-10 Quantel Ltd Image processing system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3996585A (en) * 1974-06-11 1976-12-07 International Business Machines Corporation Video generator circuit for a dynamic digital television display
US4317114A (en) * 1980-05-12 1982-02-23 Cromemco Inc. Composite display device for combining image data and method
GB2137856A (en) * 1983-04-06 1984-10-10 Quantel Ltd Image processing system

Also Published As

Publication number Publication date
CA1257719A (en) 1989-07-18
EP0194092A2 (en) 1986-09-10
CA1257719A1 (en)

Similar Documents

Publication Publication Date Title
GB2247549B (en) Method and system for storing and retrieving collaboratively processed information
TW373152B (en) Method to process posts in an automatic address-reading system
KR880004392A (en) It shapes database input device and the input method
EA199700367A1 (en) System and method of setting personality
MY116707A (en) Coprocessor data access control
JPH04215158A (en) Data transfer control method and interface system
JPS6324419A (en) Composite document processor
JPS6158083A (en) Fast memory system, data processing method and memory segment
CA2130336A1 (en) Method and apparatus for rapidly processing data sequences
EP0042442A4 (en) Information processing system.
JPH04297934A (en) Data processing system
JPS57101957A (en) Storage control device
KR920013133A (en) vram array of access methods and apparatus for providing a record of the vertical lines on the output display speed
CA2284250A1 (en) Computer method for implementing a get instruction
CA2130690A1 (en) Card Issue System
EP0597794A3 (en) Method and system for graphic interaction between data and applications within a data processing system.
EP0282711A3 (en) Method of processing data in a decentralized processing system
EP0947918A3 (en) System and method for performing a shuffle instruction
CA2090198A1 (en) Teamwork cad system and process for teamwork designing
JPH02162475A (en) Picture contour correcting method
NZ195062A (en) Multiprogramming data processing system capture and description of process information in a process dump stack on process suspension
EP0369702A3 (en) Image processing apparatus and method
AU1332883A (en) Automated instruction, game and data retrieval system
EP0288672A3 (en) Method and device for image manipulation
JPH01256088A (en) Picture information reproducing processing unit

Legal Events

Date Code Title Description
AK Designated contracting states:

Kind code of ref document: A2

Designated state(s): DE FR GB NL SE

AK Designated contracting states:

Kind code of ref document: A3

Designated state(s): DE FR GB NL SE

17P Request for examination filed

Effective date: 19900803

18D Deemed to be withdrawn

Effective date: 19910819

RIN1 Inventor (correction)

Inventor name: MAINE, STEPHEN

Inventor name: MAMMEN, ABRAHAM

Inventor name: HARROWER, DUNCAN