EP0186668A1 - Pipeline d'instructions a trois mots - Google Patents

Pipeline d'instructions a trois mots

Info

Publication number
EP0186668A1
EP0186668A1 EP19850902321 EP85902321A EP0186668A1 EP 0186668 A1 EP0186668 A1 EP 0186668A1 EP 19850902321 EP19850902321 EP 19850902321 EP 85902321 A EP85902321 A EP 85902321A EP 0186668 A1 EP0186668 A1 EP 0186668A1
Authority
EP
European Patent Office
Prior art keywords
instruction
register
words
word
control means
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP19850902321
Other languages
German (de)
English (en)
Inventor
Douglas B. Macgregor
Robert R. Thompson
David S. Mothersole
Mark W. Bluhm
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of EP0186668A1 publication Critical patent/EP0186668A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding

Definitions

  • a data processor performs a series of operations upon digital information in an execution unit according to a stored program of instructions. These instructions are often termed
  • macroinstructions in order to avoid confusion with the microinstructions contained in the control store of the data processor.
  • Each of the macroinstructions indicates to the data processor a particular operation to be performed.
  • most macroinstructions specify the address of one or more operands upon which the operation will be performed.
  • these operands may be specified. In some cases, the operand is already contained by a register within the data processor execution unit. In other cases, however, the operand is stored in memory external to the data processor. Occasionally, the operand is located in a memory location immediately following the memory location from which the current macroinstruction was obtained (so called immediate addressing). In other cases, the operand is stored at a location in memory which is referenced by one of the data processor registers (so called effective addressing).
  • the data processor in order to execute a macroinstruction, the data processor must typically perform a series of microinstructions for computing the address and acquiring each of the operands and perform another series of microinstructions for performing the operation specified by the macroinstruction upon the acquired operands.
  • Each macroinstruction is accessed from memory and decoded to derive the control signals which select the microinstruction sequence or sequences to perform the operation required by the macroinstruction.
  • Some of the microinstruction sequences are directed to calculation of effective addresses of operands if the operands are not immediately accessible in a register.
  • a pipelined architecture may be employed in which one macroinstruction (or a segment of a long macroinstruction) may be executing while another macroinstruction (or a second segment of the macroinstruction) is being decoded.
  • a pipelined architecture is disclosed in U.S. Pa ten t No. 4,342,078, Tredennick et al.
  • Tredennick patent a 16-bit instruction path was provided and a series of registers IR, IRC and IRD were employed to store, decode, and execute successive macroinstructions (or segments of the same macroinstruction).
  • the Tredennick patent moreover, discussed the use of macroinstruction calls at various levels to perform register to register instructions or to perform the necessary calculations (through microinstruction routines) to derive effective addresses from certain macroinstruction fields.
  • the processor therein had a 16-bit bus as well as a 16-bit data path, so each instruction fetch produced one 16-bit macroinstruction or segment thereof.
  • changes in the instruction flow for example on a branch instruction, can be costly since the pipe must be refilled.
  • refilling the pipe required two successive bus accesses. If a three-deep pipe were used, three bus accesses would be required before execution could resume. This penalty is severe in that approximately twenty-five percent of executed instructions result in a change in the instruction flow. The still earlier decoding opportunity of a three-deep pipe would be overshadowed by the penalties of an instruction flow change.
  • a data processor with a pipe n-words deep and wherein the n-word pipe may be filled in n-1 bus accesses. This is accomplished by providing a bus 2n words wide coupled between the memory and the pipe for carrying instructions to the execution unit, and a means for recognizing whether the first word to be fetched is on an even or an odd boundary in memory.
  • Figure 1 shows a block diagram of the execution unit of a data processor according to the invention.
  • Figure 2 shows a more detailed block diagram of a portion of the execution unit of Figure 1.
  • Figure 3 shows a block diagram of the essential elements of a three-level instruction pipeline with control elements in accordance with the instant invention.
  • Figure 1 shows a block diagram of the execution unit of a data processor according to the invention, with its associated control mechanisms.
  • the execution unit is shown at 10, and has a P section, an A section, and a D section.
  • An external address bus and data bus are shown connected to the execution unit, as are a plurality of control lines emanating from a nano store 12.
  • the nano store and a micro store 14 are both addressed by the sequence controller 16.
  • the sequence controller is provided information from a plurality of decoders, 18, 20, 22, 24 and 26 and from a branch control 28.
  • the instructions to be executed by the execution unit are stored in data ram 30, which is an internal instruction cache, or in external memory as will be discussed.
  • the tag ram 31 provides addresses to the cache as a function of the real address generated by the execution unit.
  • the instructions are fetched from data ram 30 to a register IRB 32 which comprises the first register of the instruction pipeline. From IRB the instruction flows to register IRC and IRC2, 34 and 36, respectively. From IRC, the instructions flow to IR 38 and IRD 40. While in IRC, IRC2, and IRD the instructions are decoded and executed. The decoding takes place in the decoders 18, 20, 22, 24, and 26.
  • Instructions specify operand locations in one of three ways.
  • the first way is by register specification. If the operand location is a register, the number of the register is given in a register field of the instruction.
  • the second way is by effective address specification, which can designate an operand location by using one of the Effective Address modes.
  • the third way used by a variety of instructions, is by implicit reference to special registers.
  • Instructions are at least one word in length.
  • the first word of the instruction is called the operation word.
  • the length of the instruction is implicitly determined by fields in the operation word, and in some cases also in the following words.
  • the operation word also specifies the operation to be performed. Any remaining words may further specify the operation or the operands. These words are either extensions to the effective address modes specified in the operation word, or immediate operands which are part of the instruction.
  • the general format of an instruction is thus:
  • the instant processor separates memory references into two classes. This creates two address spaces, each with a complete logical address range.
  • the first class is program references, which means the reference is to the object text of the program being executed.
  • the operation of the execution unit of the instant processor is not unlike the operation of the processor described in the Tredennick patent referenced above, in the sense that an internal clock divides the apparent machine cycle time into four time periods, T1, T2, T3, and T4.
  • Each set of T times is referred to as a "box" since the contents of one microinstruction box is executed in such a period (in some cases where such execution is not possible because, for example, excessive bus accesses were required, the clocks delay the resumption of the sequence until all necessary actions are taken).
  • An example of a microinstruction box and the key for interpreting the same is given in Appendix 1 hereto. In the Tredennick patent, depending upon the instruction type, one of a number of microaddressing sequences could occur.
  • an A1 call was necessary, since all the pertinent information was specified in a single instruction word and there was no necessity to calculate effective addresses.
  • the actual execution of the instruction took longer than one box, however, because when the instruction itself was Called, decoding was immediately begun, but the decoding and subsequent operations, even register operations, could not be completed within four internal clock cycles.
  • the A1 call would provide only a portion of the information necessary to execute the instruction because effective addresses needed to be calculated. In such case, the A1 call would reference an effective address routine or an immediate routine. This would result in an A2 and/or an A3 call to secure the necessary information to complete the instruction.
  • one or more calls may be made depending upon the type of instruction. Since in the instant machine the pipe is deeper than in the machine of the Tredennick patent, decoding can begin earlier and the entire microinstruction can be completed within one box of four microcycles. As noted before, in order to execute instructions where an address must be calculated, additional calls must be made. Also to handle special situations such as coprocessor interactions, additional microaddress calls must be generated. Following is a description of the call levels available, not all of which are pertinent to the instant invention:
  • the A1 calls are decoded by the A1 decoder PLA 20 of Figure 1 which decodes the value in IRC register 34 to provide an address to the first microword to be executed by an instruction. IRC will be loaded, as will be discussed further, during T2 of one microinstruction, and by T1 of the next, the result of the decode is available.
  • the A2/A3 calls are decoded by the A2/A3 decoder PLAs which decode the value in IRD to provide an address to the first microword of any additional functions associated with an instruction if they should be necessary. IRD is loaded during T1 of one microinstruction, and the result of the decode is available at T1 of the next.
  • the execution unit 10 is comprised of three main sections, a P section, an A section, and a D section.
  • the P section is used to calculate instruction stream pointers to facilitate fast access into the cache.
  • the A section calculates operand addresses, and is used for some data manipulation.
  • the D section is the primary location for data manipulation .
  • Figure 2 shows a block disgram of the P section of the execution unit, which handles all instruction stream fetching. It maintains the pointers into the instruction stream as well as the program counter associated with an instruction. Instruction accesses are always reads from the program space which are accessed through the cache.
  • a register ADBPT 42 the address output buffer for the P section, generally points to the next word in the instruction stream to be fetched. It is connected, as are most of the other registers in the P section, between the address bus 44 and the data bus 46.
  • the AOBP register 48 is essentially a copy of the
  • AOBPT register and bit 1 of AOBP is used to determine whether the next prefetch instruction boundary is odd or even
  • the AU 50 is a 32 bit arithmetic unit used for calculating addresses for the P section.
  • a constant register KD is associated with the AU.
  • the register PC 52 is the program counter for the instruction stream, and points at the word following the first word of the instruction being executed.
  • PC is loaded by register TP2 54 which in turn is maintained by register TP1 56.
  • Bit one of TP1 can be set by the microcode associated with the macroinstruction bus controller such that the TP1 is corrected throughout the intermediate stage of an operation.
  • This mechanism allows the processor to prefetch three words of instruction in two cache or bus accesses. Since the bus is 32 bits wide and the instructions are 16 bits wide, two 32 bit accesses always guarantee access of three instruction words, which is the number required to fill the three deep pipe. Thus regardless of the instruction boundary alignment, two words may be accessed in one microinstruction "box" of four microcycles, and one word in the adjacent box.
  • Figure 3 shows a block diagram of a three register deep instruction pipeline, most of the elements of which are also shown in Figure 1. Where common elements are shown, consistent numbering is used. As previously noted, the pipeline is three registers deep, the three levels represented by IRB, the most distant register from the instruction register in the pipe, and the register pairs IRC/IRC2, and IR/IRD.
  • the IRB register 32 usually contains the most recent word read from the data ram or cache memory 30.
  • a cache is a very high speed memory, of limited size, which contains the currently executing instruction stream. If a branch or other instruction stream change requires data not in the cache, an external bus cycle must be run to fetch the required data.
  • the cache communicates with the IRB via cache holding register CHRL/CHRH 58.
  • the IRB register is controlled by a field (PIPEOP) within a microcontrol word if an operation associated with the pipe is involved. IRB can also communicate with the execution unit buses by way of the IML register 60.
  • the IRC register 34 either contains the first extension word of an instruction or the next instruction to be executed. As an extension word, various fields of the word are used to perform branches or to be used as register pointers. As the next instruction to be executed, decoding is immediately begun in order to keep the processor flowing. To accomplish this, all of the initial entry instruction decoding (A1 calls) is done off this register. IRC is also controlled by the PIPEOP field of a microinstruction.
  • the IHC2 register 36 contains the same information as the IRC register.
  • the primary use of the IRC2 register is to aid in coprocessor operations, which form no part of the instant invention, and to allow multiple word instructions to be handled more easily.
  • a multiple word instruction contains control information which must be used throughout the execution time of that instruction.
  • IRC2 contains the second word of the instruction, if such is present.
  • IRC2 is also used as as one of the sources of the A5 and A6 PLA decoders 24 and 26, respectively to support coprocessor operation. IRC2 is controlled by PIPEOP and by an A1 call. During a microinstruction in which an A1 call is made, the contents of IRC are transferred into IRC2.
  • the IR register 38 is used to hold a prefetched instruction for later transfer to IRD 40. Since it is desirable to make any needed instruction accesses as early as possible, IR is loaded with the next instruction as soon as possible. While this may not always be possible, where it is possible, the next instruction word is stored in IR rather than IRD since the word in IRD is still being used for residual control.
  • the IR register is controlled by PIPEOP. A transfer from IR to IRD may be driven by an A1 call.
  • the IRD register 40 contains the first word of the instruction being executed.
  • the instruction is loaded into IRD as soon as possible in the last microinstruction of the previous instruction and it resides there until the last microinstruction of its execution when the next instruction is loaded.
  • the A2/A3 and most of the residual control PLAs are fed by this register.
  • IRD is also controlled by PIPEOP and from an A1 call.
  • the transfer from IR or IR into IRD is controlled by PIPEOP or it is inherent in an A1 call (as is the IRC > IRC2 update).
  • the operation of the pipe is as follows.
  • the external data bus and the cache are both 32 bits wide, so an instruction fetch always produces 32 bits.
  • An access from either the bus or the cache is first loaded into the cache holding register 58. It can be seen from Figure 3 that the cache holding register is divided into high and low segments.
  • the word which was accessed is moved from the cache holding register to register IRB 32 which is a 16 bit register (as are the other pipe registers, IRC, IRC2, IR,and IRD).
  • IRB 32 is a 16 bit register (as are the other pipe registers, IRC, IRC2, IR,and IRD).
  • IRC the contents of IRB are put into IRC and the newly prefetched word is placed in IRB. If at that time a new instruction is to begin execution, i.e. an A1 call has caused the transfer of the instruction in register IR to IRD, IRC is copied into IRC2 so that IRC2 always contains the second word of the instruction. If a new instruction is not beginning execution, IRC is not copied into IRC2, but proceeds to IR as the pipe is advanced.
  • the static registers IRC2 and IRD provide most of the decodes, with IRD providing the first word decodes of the A2/A3 calls and IRC2 providing the second word decodes and register selections.
  • a number of the second word decodes relate to A5 and A6 calls and are not relevant to this invention, except insofar as they occur in the pipe. Note that the Al calls have been previously made at the time when the instruction in IRC was copied into IRC2. Those calls were made, however, from the instruction in the IRC register.
  • the residual decoding including the selection of the ALU, condition code operations, etc., must continue past the time when the early microaddress calls were made. These take place in the IRD register.
  • bit 10 of the second word indicates the size of the dividend
  • bits 14-12 and 2-0 indicate the location of the operands.
  • the dividend may in this case be 64 bits or 32 bits, and the divisor 32 bits.
  • the effective address specified by bits 5-0 of the first word may have multiple words, so the first word may be needed until the end of the instruction.
  • the second word is loaded into IRC2 and the first word is loaded into IRD.
  • IRD tells the ALU what kind of operations to perform.
  • elements will be stepped up the pipe through IRB, IRC, and IR. There may be, for example, five words of effective address extension that are necessary to find the effective address. But the first and second words of the instruction must remain the same so that when the A2/A3 call to actually do the divide operation occurs, the register pointers out of the second word can be used to store the results.
  • While the information used to calculate the effective address is stepped through the pipe, it is not actually used by the pipe. As these words are required to calculate the effective address, they may be accessed by the execution unit through register IML 60. The fact that they may appear in IR is irrelevant, as they are never used there. The only reason for the existence of IR is to act as a staging area to hold the next instruction prior to loading IRD. If the next instruction was always prefetched as the last operation of a microinstruction, there would be no need for IR. But it is frequently useful to prefetch that instruction earlier, so IR is used to hold it pending the residual decoding of the instruction in IRD.
  • A1A - use the A1 PLA sample interrupts, do not sample trace
  • A1B - use the A1 PLA do not sample interrupts or trace
  • A4 - use the A4 latch as next micro address
  • the latch in which this value is held has the following encoding
  • RX is a general register pointer. It is used to point at either special purpose registers or user registers. RX generally is used to translate a register pointer field within an instruction into the control required to select the the appropriate register.
  • ry ry/dbin This is a conditional substitution ry/dob for the normal ry selection (which includes the residual substitutions like dt) with dbin or dob. The substitution is made based on residual control defined in opmap (about 2 ird lines) which selects the dbin/dob and inhibits all action to ry (or the residually defined ry). Depending upon the direction to/from the rails dbin or dob is selected. If the transfer is to the rails then dbin is substituted while if the transfer is from the rails dob is substituted.
  • ror value in rega is rotated right by value in shift count register into regb.
  • sxtd value in rega defined by start and end registers is sign extended to fill the undefined bits and that value is rotated right by the value in the shift count register.
  • the result is in regb.
  • xxtd value in rega defined by start and end registers is PSWX extended to fill the undefined bits and that value is rotated right by the value in the shift count register.
  • the result is in regb.
  • zxtd value in rega defined by start and end registers is zero extended to fill the undefined bits and that value is rotated right by the value in the shift count register.
  • the result is in regb.
  • This value however should be shifted by 3 bits such that osr [4:3] are loaded onto regb[l:0] with zero zero extension of the remaining bits.
  • 3- LDCR load the control register from regb.
  • the register is selected by the value in ar[1:0], this can be gated onto the rx bus.
  • 4- DPSW load the psw with the value in regb. Either the ccr or the psw is loaded depending upon size. If size as byte then only load the ccr portion.
  • 17- LDSH2 load the contents of the shifter control registers from regb. These include wr,osr,count. 19- LDSWB load the internal bus register from regb. This is composed of bus controller state information which must be accessed by the user in fault situations. 21- LDSWI load the first word of sswi (internal status word) from regb. This is composed of tpend, fpend1, fpend2, ar latch 23- LDSH1 load the contents of the shifter control registers from regb. These include st,en,sc. 25- LDUPC load micro pc into A4 from regb and check validity of rev #. 26- LDPER load per with the value on the a-bus.
  • MOVEM requires the least significant bit of the. lower word (16-bits only) that is a one to be encoded and latched into the AR latch and onto the BC BUS (inverted) so that it can be used to point at a register. If no bits are one then the end signal should be active which is routed to the branch pla. After doing the encoding, the least significant bit should be cleared.
  • the output is then gated onto the BC bus where it is sign extended to an 8-bit value. It does not hurt anything in the
  • 34- STCR store the control register in regb. The register is selected by the value in ar[1:0], this can be gated onto the rx bus.
  • 37- STPSW store the psw or the cer in regb based on size. If size as byte then store cer only with bits 8 - 15 as zeros.
  • 38- 0PEND store the psw in regb then set the supervisor bit and clear the trace bit in the psw. Tpend and Fpend are cleared. The whole psw is stored in regb.
  • 39- 1PSWS store the psw in regb then set the supervisor bit and clear both trace bits in the psw.
  • the whole psw is stored in regb.
  • 40- STINST store IRD decoded information onto the BC bus and into regb. This data can be latched from the BC bus into other latches (i.e. wr & osr) by other control.
  • 41- STIRD store the ird in regb.
  • 43- STINL store the new interrupt level in pswi and regb.
  • the three bits are loaded into the corresponding pswi bits.
  • Clear IPEND the following T1.
  • 44- STV# store the format & vector number associated with the exception in regb.

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)

Abstract

Des systèmes pipeline de traitement de données ayant des pipelines profonds opèrent dans de mauvaises conditions, car ils consomment du temps d'accès excessif lors d'opérations normales, le problème s'aggravant lorsqu'il faut exécuter une opération de branchement qui nécessite une recharge du pipeline. Afin de diminuer ces inconvénients, un processeur de données qui utilise un pipeline d'instructions à trois mots composé de registres (32, 34/36 et 38/40) fournit un décodage anticipé par des décodeurs (18, 20, 22, 24 et 26) d'instructions en provenance d'une mémoire (12 et 14). Le processeur de données nécessite uniquement deux cycles d'accès au bus pour remplir le pipeline grâce à l'opération de son unité d'exécution (10). Deux parmi les trois mots requis pour remplir le pipeline sont extraits lors d'un seul cycle d'accès au bus, et tous les registres qui forment le pipeline sont remis simultanément à l'état initial lorsqu'une opération de branchement requiert la recharge du pipeline.
EP19850902321 1984-06-27 1985-04-22 Pipeline d'instructions a trois mots Withdrawn EP0186668A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US62506684A 1984-06-27 1984-06-27
US625066 1984-06-27

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EP0186668A1 true EP0186668A1 (fr) 1986-07-09

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2237391A (en) * 1989-10-23 1991-05-01 Ntn Toyo Bearing Co Ltd Pulse ring for rotation speed sensor

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Publication number Priority date Publication date Assignee Title
KR930005768B1 (ko) * 1989-01-17 1993-06-24 후지쓰 가부시끼가이샤 마이크로 프로세서

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US3156897A (en) * 1960-12-01 1964-11-10 Ibm Data processing system with look ahead feature
US3234524A (en) * 1962-05-28 1966-02-08 Ibm Push-down memory
US3440615A (en) * 1966-08-22 1969-04-22 Ibm Overlapping boundary storage
US3573854A (en) * 1968-12-04 1971-04-06 Texas Instruments Inc Look-ahead control for operation of program loops
US3725868A (en) * 1970-10-19 1973-04-03 Burroughs Corp Small reconfigurable processor for a variety of data processing applications
SE435429B (sv) * 1977-04-26 1984-09-24 Ericsson Telefon Ab L M Anordning for att mot utgaende informationsflodesgrenar forgrena ett inkommande "pipeline"-informationsflode
US4471432A (en) * 1982-10-13 1984-09-11 Wilhite John E Method and apparatus for initiating the execution of instructions using a central pipeline execution unit

Non-Patent Citations (1)

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See references of WO8600435A1 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2237391A (en) * 1989-10-23 1991-05-01 Ntn Toyo Bearing Co Ltd Pulse ring for rotation speed sensor

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Publication number Publication date
WO1986000435A1 (fr) 1986-01-16

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