EP0174694B1 - Circuit for generating a substrate bias - Google Patents
Circuit for generating a substrate bias Download PDFInfo
- Publication number
- EP0174694B1 EP0174694B1 EP85201406A EP85201406A EP0174694B1 EP 0174694 B1 EP0174694 B1 EP 0174694B1 EP 85201406 A EP85201406 A EP 85201406A EP 85201406 A EP85201406 A EP 85201406A EP 0174694 B1 EP0174694 B1 EP 0174694B1
- Authority
- EP
- European Patent Office
- Prior art keywords
- circuit
- control
- transistor
- capacitance
- charge pump
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/205—Substrate bias-voltage generators
Definitions
- the invention relates to a circuit for generating a bias voltage for another circuit which is integrated on a semiconductor substrate, which first-mentioned circuit comprises an oscillator for generating control pulses and at least one charge pump to which electrical pulses derived from the control pulses are applied, which charge pump comprises a series arrangement of a capacitance and a diode, which electrical pulses are applied to a first electrode of the capacitance, whose second electrode is connected to the diode associated with the capacitance, an output of the charge pump being connected to the substrate and the junction point of the capacitance and the diode of the charge pump being connected to the earth point of the integrated circuit via a channel of an insulated-gate switching transistor whose gate is connected to a control circuit which receives the control pulses.
- Such a circuit is known from United States Patent Specification 4,438,346.
- the control electrode of the transistor which connects the junction point of the capacitance and the diode of the charge pump to the earth point, is connected to a junction point of two series-arranged, diode-connected transistors which interconnect the earth point and a junction point carrying the negative substrate voltage.
- the control electrode is at a negative potential when there are no control pulses, thus causing the transistor to remain in the cut-off state if the voltage at the junction point in the charge pump decreases to a value which lies more than one threshold voltage of said transistor below earth potential.
- efficient use is made of the charge stored in the capacitance.
- the negatively-biassed transistor must be rendered conductive. In said circuit this is achieved by means of control pulses which are applied to the control electrode of the transistor via a capacitor and which exceed the supply voltage.
- control pulses For generating such control pulses, a relatively complex control circuit is needed in which the required voltage levels of the control pulses can be generated by means of bootstrap techniques.
- the said U.S. Specification also describes steps, such that the control pulses, generated by the relatively complex control circuit, are no longer needed.
- the control electrode of the switching transistor is connected to the earth point via the junction point of the capacitance and the diode of the charge pump.
- this circuit which is known per se, has the disadvantage that the capacitance is charged to a maximum of V oo - 2V TH (V oo is the supply voltage and VTH is the threshold voltage of the field-effect transistors; the capacitance is usually formed by interconnecting the main electrodes of a field-effect transistor).
- V oo is the supply voltage
- VTH the threshold voltage of the field-effect transistors
- the capacitance is usually formed by interconnecting the main electrodes of a field-effect transistor.
- the charge pump cannot pump much charge (or no charge at all if V oo ⁇ 2V TH ).
- the invention is characterized in that the switching transistor is connected in series with at least one other switching transistor whose insulated-gate electrode receives the electrical pulses for the charge pump, the control pulses being applied to the gate electrode of the first-mentioned switching transistor after having been inverted by the control circuit, which control circuit connects the gate electrode of the first-mentioned switching transistor to its main electrode (source) when a control pulse is applied to the control circuit.
- the capacitance of the charge pump is charged to V oo - V TH , which is advantageous, especially, at a relatively low supply voltage (for example, 2 or 3 V TH ).
- a voltage to -2V TH can be generated because two transistors, which are diode-connected during the pumping cycle, are arranged in series.
- a circuit for generating a substrate bias comprises an oscillator 10 for the generation of control pulses, a first and a second charge pump 1 and 2, respectively, and a control circuit 3.
- the output of amplifier stage a is connected to a first electrode of a capacitance C1 of the first charge pump 1 which further comprises a diode-connected field-effect transistor N1 whose control electrode (gate) is connected to a main electrode (drain) and to an output A.
- Output A of the circuit is connected to the substrate (not shown) on which a further integrated circuit has been provided, for which further circuit the negative substrate bias V BB appearing on output A is generated.
- Junction point B of capacitance C1 and transistor N1 is connected to the output of charge pump 2 which comprises a capacitance C2 and a transistor N2.
- Transistor N2 is diode-connected in known manner and capacitance C2 receives electrical pulses which appear on the output of the amplifier stage 10b. Hence, capacitances C1 and C2 receive (control) pulses which are substantially in phase opposition.
- junction point C of capacitance C2 and transistor N2 is connected to earth point M via two series-connected transistors N3 and N4.
- a source electrode of transistor N4 is connected to earth point M and the gate electrode is connected to the output of the amplifier stage 10b.
- a main electrode (drain) of transistor N3 is connected to junction point C, the source electrode of transistor N3 and the main electrode (drain) of transistor N4 being connected to a junction point D.
- the control electrode of transistor N3 is connected to the output of control circuit 3 which comprises an inverting amplifier with two complementary transistors P1 and N5, and having its input connected to the output of the amplifier stage 10a.
- the source electrode of transistor P1 is connected to the supply voltage V oo and the source electrode of transistor N5 is connected to junction point D.
- the control electrodes of the transistors which are used as capacitances C1 and C2 are, preferably connected to the relevant diode N2 or N1.
- the capacitance C2 (and C1) is constituted by a P-channel transistor, the (inevitable) stray capacitances being connected to the output of amplifier stage 10b (and 10a, respectively) as shown in the drawing, and not to junction point C (and B), consequently, they do not load charging pump 2 (and 1), which would be very disadvantageous.
- the charging period of capacitance C2 ends as soon as the output level of amplifier stage 10a increases from a low potential to a high potential.
- Transistors P1 and N5 of control circuit 3 will be turned off and turned on, respectively, causing the control electrode and the source electrode of transistor N3 to be interconnected after the control electrode has been disconnected from the power supply V oo .
- the ratio of transistors P1 and N5 is chosen (for example, 2.5/10 and 2/2, respectively) so that the control electrode of transistor N3 is connected to the source electrode thereof prior to the pumping cycle of charge pump 2.
- the output level of amplifier stage 10b will decrease from a high potential to a low potential and, hence, connect, in effect, the control electrode of transistor N4 to earth point M.
- junction point C of charge pump 2 is now connected to earth point M via two transistors N3 and N4 which are arranged as diodes.
- the potential at junction point C will decrease to a level below the earth potential (of earth point M) until the two series-arranged diodes N3 and N4 become conductive.
- the negative potential at junction point C is limited to -2V THN , V THN being the threshold voltage of the N-channel transistors N3 and N4.
- charge pumps 1 and 2 cooperate in known manner, and they can generate a substrate bias of -2V at a supply voltage V oo if 2V.
- FIG 2 shows a further embodiment of the invention which, apart from an additional part 3', is identical to the circuit shown in Figure 1. For that reason, all corresponding components of Figures 1 and 2 bear the same reference numerals.
- an additional switching transistor N3' has been provided between the stitching transistors N3 and N4, and it is controlled in the same way as transistor N3.
- the switching transistors N3', N3 and N4 are turned on: the output of amplifier stage 10a is at a low potential, hence the control electrodes of switching transistors N3 and N3' are connected to the power supply V ID via the P-channel transistors P1 and P1', respectively.
- a circuit for generating a substrate bias in accordance with the invention is used, preferably, in a circuit which is integrated in a semiconductor substrate, which circuit has been fabricated, at least in part, in an N-well on a P-type semiconductor substrate, and which must also remain operative at a low supply voltage of, for example, 2V.
- the use of the circuit in accordance with the invention is advantageous, as, because of this, the information content of the relevant memory cells is not disturbed by input signals which exhibit undersirable negative voltage peaks (for example, values to -1 or -1,5 V) as occur in TTL-circuits, which voltage peaks bring about a charge injection in the N-well.
- undersirable negative voltage peaks for example, values to -1 or -1,5 V
Description
- The invention relates to a circuit for generating a bias voltage for another circuit which is integrated on a semiconductor substrate, which first-mentioned circuit comprises an oscillator for generating control pulses and at least one charge pump to which electrical pulses derived from the control pulses are applied, which charge pump comprises a series arrangement of a capacitance and a diode, which electrical pulses are applied to a first electrode of the capacitance, whose second electrode is connected to the diode associated with the capacitance, an output of the charge pump being connected to the substrate and the junction point of the capacitance and the diode of the charge pump being connected to the earth point of the integrated circuit via a channel of an insulated-gate switching transistor whose gate is connected to a control circuit which receives the control pulses.
- Such a circuit is known from United States Patent Specification 4,438,346. In the prior-art circuit, the control electrode of the transistor which connects the junction point of the capacitance and the diode of the charge pump to the earth point, is connected to a junction point of two series-arranged, diode-connected transistors which interconnect the earth point and a junction point carrying the negative substrate voltage. Hence, the control electrode is at a negative potential when there are no control pulses, thus causing the transistor to remain in the cut-off state if the voltage at the junction point in the charge pump decreases to a value which lies more than one threshold voltage of said transistor below earth potential. Thus, during a pumping cycle efficient use is made of the charge stored in the capacitance. However, in order to charge the capacitance, the negatively-biassed transistor must be rendered conductive. In said circuit this is achieved by means of control pulses which are applied to the control electrode of the transistor via a capacitor and which exceed the supply voltage.
- For generating such control pulses, a relatively complex control circuit is needed in which the required voltage levels of the control pulses can be generated by means of bootstrap techniques.
- However, the said U.S. Specification also describes steps, such that the control pulses, generated by the relatively complex control circuit, are no longer needed. The control electrode of the switching transistor is connected to the earth point via the junction point of the capacitance and the diode of the charge pump. However, this circuit, which is known per se, has the disadvantage that the capacitance is charged to a maximum of Voo - 2VTH (Voo is the supply voltage and VTH is the threshold voltage of the field-effect transistors; the capacitance is usually formed by interconnecting the main electrodes of a field-effect transistor). However, at this low supply voltage the charge pump cannot pump much charge (or no charge at all if Voo < 2VTH).
- It is the object of the invention to provide a circuit for generating a substrate bias, which does not require a complicated control circuit (or generating control pulses of relatively high amplitude (for example, higher than the supply voltage) and which comprises a charge pump which operates efficiently, even at a relatively low supply voltage (for example, fractionally higher than 2VTH)·
- For that purpose, the invention is characterized in that the switching transistor is connected in series with at least one other switching transistor whose insulated-gate electrode receives the electrical pulses for the charge pump, the control pulses being applied to the gate electrode of the first-mentioned switching transistor after having been inverted by the control circuit, which control circuit connects the gate electrode of the first-mentioned switching transistor to its main electrode (source) when a control pulse is applied to the control circuit. With the circuit in accordance with the invention, the capacitance of the charge pump is charged to Voo - VTH, which is advantageous, especially, at a relatively low supply voltage (for example, 2 or 3 VTH). During the pumping cycle of the charge pump, a voltage to -2VTH can be generated because two transistors, which are diode-connected during the pumping cycle, are arranged in series.
- The invention will now be described, by way of example, with reference to the accompanying drawing, in which drawing:
- Figure 1 is an embodiment of the invention, and
- Figure 2 is a further embodiment of the invention.
- A circuit for generating a substrate bias, as shown in the relevant Figure, comprises an
oscillator 10 for the generation of control pulses, a first and asecond charge pump 1 and 2, respectively, and acontrol circuit 3.Oscillator 10 is a ring oscillator and it comprises seven, known, inverting amplifier stages 10a, b, c, d, e, f and g, which each comprise two complementary field=effect transistors. The output of amplifier stage a is connected to a first electrode of a capacitance C1 of the first charge pump 1 which further comprises a diode-connected field-effect transistor N1 whose control electrode (gate) is connected to a main electrode (drain) and to an output A. Output A of the circuit is connected to the substrate (not shown) on which a further integrated circuit has been provided, for which further circuit the negative substrate bias VBB appearing on output A is generated. Junction point B of capacitance C1 and transistor N1 is connected to the output ofcharge pump 2 which comprises a capacitance C2 and a transistor N2. Transistor N2 is diode-connected in known manner and capacitance C2 receives electrical pulses which appear on the output of the amplifier stage 10b. Hence, capacitances C1 and C2 receive (control) pulses which are substantially in phase opposition. - Junction point C of capacitance C2 and transistor N2 is connected to earth point M via two series-connected transistors N3 and N4. A source electrode of transistor N4 is connected to earth point M and the gate electrode is connected to the output of the amplifier stage 10b. A main electrode (drain) of transistor N3 is connected to junction point C, the source electrode of transistor N3 and the main electrode (drain) of transistor N4 being connected to a junction point D. The control electrode of transistor N3 is connected to the output of
control circuit 3 which comprises an inverting amplifier with two complementary transistors P1 and N5, and having its input connected to the output of the amplifier stage 10a. The source electrode of transistor P1 is connected to the supply voltage Voo and the source electrode of transistor N5 is connected to junction point D. - The circuit shown operates as follows. If the output of the amplifier stage 10a is at a low level (low potential), the output of
control circuit 3 and the output of amplifier stage 10b will be at a high potential (just below Voo). Due to the high potential at its control electrode, transistor N3 will be conductive as well as transistor N4 which receives the high output potential of amplifier stage 10b at its control electrode. Since transistors N3 and N4 are conductive, capacitance C2 will be charged. Capacitance C2 (and capacitance C1) is formed in known manner by a field-effect transistor whose main electrodes are interconnected. During charging of capacitance C2, a charge Q is stored in the said capacitance, Q = C2. (Voo - VTH), where C2 is the value of capacitance C2, Voo is the supply voltage, and VTH is the threshold voltage of the transistor arranged as constituting capacitance C2. As illustrated the control electrodes of the transistors which are used as capacitances C1 and C2 are, preferably connected to the relevant diode N2 or N1. Preferably, the capacitance C2 (and C1) is constituted by a P-channel transistor, the (inevitable) stray capacitances being connected to the output of amplifier stage 10b (and 10a, respectively) as shown in the drawing, and not to junction point C (and B), consequently, they do not load charging pump 2 (and 1), which would be very disadvantageous. - The charging period of capacitance C2 ends as soon as the output level of amplifier stage 10a increases from a low potential to a high potential. Transistors P1 and N5 of
control circuit 3 will be turned off and turned on, respectively, causing the control electrode and the source electrode of transistor N3 to be interconnected after the control electrode has been disconnected from the power supply Voo. The ratio of transistors P1 and N5 is chosen (for example, 2.5/10 and 2/2, respectively) so that the control electrode of transistor N3 is connected to the source electrode thereof prior to the pumping cycle ofcharge pump 2. The output level of amplifier stage 10b will decrease from a high potential to a low potential and, hence, connect, in effect, the control electrode of transistor N4 to earth point M. Junction point C ofcharge pump 2 is now connected to earth point M via two transistors N3 and N4 which are arranged as diodes. During the pumping cycle, which is effected when the potential at the output of amplifier stage 10b goes from a high to a low level, the potential at junction point C will decrease to a level below the earth potential (of earth point M) until the two series-arranged diodes N3 and N4 become conductive. Thus, the negative potential at junction point C is limited to -2VTHN, VTHN being the threshold voltage of the N-channel transistors N3 and N4. Further,charge pumps 1 and 2 cooperate in known manner, and they can generate a substrate bias of -2V at a supply voltage Voo if 2V. - Figure 2 shows a further embodiment of the invention which, apart from an additional part 3', is identical to the circuit shown in Figure 1. For that reason, all corresponding components of Figures 1 and 2 bear the same reference numerals. In Figure 2, an additional switching transistor N3' has been provided between the stitching transistors N3 and N4, and it is controlled in the same way as transistor N3. During the charging period of capacitance C2, the switching transistors N3', N3 and N4 are turned on: the output of amplifier stage 10a is at a low potential, hence the control electrodes of switching transistors N3 and N3' are connected to the power supply VID via the P-channel transistors P1 and P1', respectively. If the output of amplifier stage 10a goes from a low to a high level, the transistors P1 and P1' will be turned off and the transistors N5 and N5' will be turned on. This will result in the control electrode of switching transistors N3 and N3' being connected to the respective source electrode thereof, so that junction point C is connected to earth point M via three diode-connected transistors N3, N3' and N4. The additional part 3' enables the potential at junction point C to decrease to -3 VTH below earth point potential (M) during the pumping cycle. The use of such an additional part (or two, three etc.) is effective only when the supply voltage VDD is such that |VDD| ≥ 13 VTH I (VTH or 5 VTH etc.), where VDD is the supply voltage and 3 VTH (4 VTH, 5 VTH) is the (maximum) negative voltage of point C at which the three (four, five, etc.) series-arranged, diode-connected transistors (N3, N4, N3', (N3", N3") will become conductive during the pumping cycle.
- A circuit for generating a substrate bias in accordance with the invention is used, preferably, in a circuit which is integrated in a semiconductor substrate, which circuit has been fabricated, at least in part, in an N-well on a P-type semiconductor substrate, and which must also remain operative at a low supply voltage of, for example, 2V. Especially in the case of integrated static-memory circuits, comprising memory cells having high- value resistors and N-channel transistors, the use of the circuit in accordance with the invention is advantageous, as, because of this, the information content of the relevant memory cells is not disturbed by input signals which exhibit undersirable negative voltage peaks (for example, values to -1 or -1,5 V) as occur in TTL-circuits, which voltage peaks bring about a charge injection in the N-well.
Claims (10)
1. A circuit for generating a bias voltage for another circuit which is integrated in a semiconductor substrate, which first-mentioned circuit comprises an oscillator for generating control pulses and at least one charge pump, to which electrical pulses derived from the control pulses are applied, which charge pump comprises a series arrangement of a capacitance and a diode, which electrical pulses are applied to a first electrode of the capacitance, whose second electrode is connected to the diode associated with the capacitance, an output of the charge pump being connected to the substrate and the junction point of the capacitance and the diode of the charge pump being connected to the earth point of the integrated circuit via a channel of an insulated-gate switching transistor whose gate is connected to a control circuit which receives the control pulses, characterized in that the switching transistor is connected in series with at least one other switching transistor, whose insulated control electrode receives the electrical pulses for the charge pump, the control pulses being applied to the control electrode of the first-mentioned switching transistor after having been inverted by the control circuit, which control circuit connects the control electrode of the first-mentioned switching transistor to its main electrode (source) when a control pulse is applied to the control circuit.
2. A circuit as claimed in Claim 1, characterized in that the capacitance is formed by an insulated-gate transistor which is connected to the diode, the pulses being applied to the interconnected main electrodes.
3. A circuit as claimed in Claim 2, characterized in that the capacitance is formed by a transistor of the P-conductivity type.
4. A circuit as claimed in Claim 1, 2 or 3, characterized in that the diode is formed by a diode-connected transistor and that it is of the N-conductivity type like the first-mentioned and further switching transistors, in which circuit the control circuit is an inverting amplifier, a channel of an N-type output transistor of the amplifier connecting the control electrode to the main electrode of the first-mentioned switching transistor.
5. A circuit as claimed in Claim 4, characterized in that the inverting amplifier further comprises a transistor of the P-conductivity type whose channel is connected to the control electrode of the first-mentioned switching transistor and to the power-supply terminal, the control electrodes of the P-channel and the N-channel transistor of the inverting amplifier being connected to a first output of the oscillator, which is a ring oscillator. Comprising an odd number of inverting amplifiers which comprise complementary insulated-gate transistors, the electrical pulses being formed by inverting the control pulses by means of a single complementary amplifier.
6. A circuit as claimed in any one of the preceding Claims, characterized in that there is a further charge pump which comprises a series arrangement of a capacitance and a diode, whose junction point is connected to the output of the first-mentioned charge pump, in which the control pulses are applied to the capacitance and the output of the further charge pump is connected to the substrate.
7. An integrated circuit on a semiconductor substrate provided with a circuit for generating a substrate bias voltage as claimed in any one of the preceding Claims.
8. An integrated circuit as claimed in Claim 7, characterized in that at least part of the circuit is formed in an N-type well (or N-type pocket) on a P-type semiconductor substrate.
9. An integrated circuit as claimed in Claim 8, characterized in that the integrated circuit comprises memory cells having low-value resistors and transistors of the N-channel conductivity type.
10. An integrated memory circuit having rows and columns of memory cells on a semiconductor substrate provided with a circuit for generating a substrate bias voltage as claimed in any one of the preceding Claims.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| NL8402764A NL8402764A (en) | 1984-09-11 | 1984-09-11 | CIRCUIT FOR GENERATING A SUBSTRATE PRELIMINARY. |
| NL8402764 | 1984-09-11 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| EP0174694A1 EP0174694A1 (en) | 1986-03-19 |
| EP0174694B1 true EP0174694B1 (en) | 1989-03-08 |
Family
ID=19844441
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP85201406A Expired EP0174694B1 (en) | 1984-09-11 | 1985-09-06 | Circuit for generating a substrate bias |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US4705966A (en) |
| EP (1) | EP0174694B1 (en) |
| JP (1) | JPH083765B2 (en) |
| CA (1) | CA1232953A (en) |
| DE (1) | DE3568648D1 (en) |
| IE (1) | IE57080B1 (en) |
| NL (1) | NL8402764A (en) |
Families Citing this family (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3681540D1 (en) * | 1985-08-26 | 1991-10-24 | Siemens Ag | INTEGRATED CIRCUIT IN COMPLEMENTARY CIRCUIT TECHNOLOGY WITH A SUBSTRATE PRELOAD GENERATOR. |
| KR960012249B1 (en) * | 1987-01-12 | 1996-09-18 | 지멘스 악티엔게젤샤프트 | C-mos integrated circuit having a latch-up protection circuit |
| JPS63279491A (en) * | 1987-05-12 | 1988-11-16 | Mitsubishi Electric Corp | Semiconductor dynamic ram |
| FR2616602B1 (en) * | 1987-06-12 | 1989-10-13 | Thomson Semiconducteurs | POWER ON CIRCUIT FOR MOS TECHNOLOGY INTEGRATED CIRCUIT |
| JP2501590B2 (en) * | 1987-07-29 | 1996-05-29 | 沖電気工業株式会社 | Driving circuit for semiconductor device |
| JPH0783254B2 (en) * | 1989-03-22 | 1995-09-06 | 株式会社東芝 | Semiconductor integrated circuit |
| JP2645142B2 (en) * | 1989-06-19 | 1997-08-25 | 株式会社東芝 | Dynamic random access memory |
| JP2704459B2 (en) * | 1989-10-21 | 1998-01-26 | 松下電子工業株式会社 | Semiconductor integrated circuit device |
| JP2805991B2 (en) * | 1990-06-25 | 1998-09-30 | ソニー株式会社 | Substrate bias generation circuit |
| US5117125A (en) * | 1990-11-19 | 1992-05-26 | National Semiconductor Corp. | Logic level control for impact ionization sensitive processes |
| JP2575956B2 (en) * | 1991-01-29 | 1997-01-29 | 株式会社東芝 | Substrate bias circuit |
| JP2724919B2 (en) * | 1991-02-05 | 1998-03-09 | 三菱電機株式会社 | Substrate bias generator |
| DE4130191C2 (en) * | 1991-09-30 | 1993-10-21 | Samsung Electronics Co Ltd | Constant voltage generator for a semiconductor device with cascaded charging or discharging circuit |
| JP2937591B2 (en) * | 1991-12-09 | 1999-08-23 | 沖電気工業株式会社 | Substrate bias generation circuit |
| US5182529A (en) * | 1992-03-06 | 1993-01-26 | Micron Technology, Inc. | Zero crossing-current ring oscillator for substrate charge pump |
| DE4221575C2 (en) * | 1992-07-01 | 1995-02-09 | Ibm | Integrated CMOS semiconductor circuit and data processing system with integrated CMOS semiconductor circuit |
| US5412257A (en) * | 1992-10-20 | 1995-05-02 | United Memories, Inc. | High efficiency N-channel charge pump having a primary pump and a non-cascaded secondary pump |
| US5461591A (en) * | 1993-12-02 | 1995-10-24 | Goldstar Electron Co., Ltd. | Voltage generator for semiconductor memory device |
| US5528193A (en) * | 1994-11-21 | 1996-06-18 | National Semiconductor Corporation | Circuit for generating accurate voltage levels below substrate voltage |
| US5874849A (en) * | 1996-07-19 | 1999-02-23 | Texas Instruments Incorporated | Low voltage, high current pump for flash memory |
| US6064250A (en) * | 1996-07-29 | 2000-05-16 | Townsend And Townsend And Crew Llp | Various embodiments for a low power adaptive charge pump circuit |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4229667A (en) * | 1978-08-23 | 1980-10-21 | Rockwell International Corporation | Voltage boosting substrate bias generator |
| JPS6038028B2 (en) * | 1979-07-23 | 1985-08-29 | 三菱電機株式会社 | Substrate potential generator |
| US4336466A (en) * | 1980-06-30 | 1982-06-22 | Inmos Corporation | Substrate bias generator |
| JPS583328A (en) * | 1981-06-29 | 1983-01-10 | Fujitsu Ltd | Generating circuit for substrate voltage |
| JPS5840631A (en) * | 1981-09-04 | 1983-03-09 | Hitachi Ltd | Voltage generating circuit |
| US4438346A (en) * | 1981-10-15 | 1984-03-20 | Advanced Micro Devices, Inc. | Regulated substrate bias generator for random access memory |
| US4585954A (en) * | 1983-07-08 | 1986-04-29 | Texas Instruments Incorporated | Substrate bias generator for dynamic RAM having variable pump current level |
-
1984
- 1984-09-11 NL NL8402764A patent/NL8402764A/en not_active Application Discontinuation
-
1985
- 1985-09-05 US US06/772,790 patent/US4705966A/en not_active Expired - Fee Related
- 1985-09-05 CA CA000490031A patent/CA1232953A/en not_active Expired
- 1985-09-06 DE DE8585201406T patent/DE3568648D1/en not_active Expired
- 1985-09-06 EP EP85201406A patent/EP0174694B1/en not_active Expired
- 1985-09-09 IE IE2213/85A patent/IE57080B1/en not_active IP Right Cessation
- 1985-09-11 JP JP60199618A patent/JPH083765B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6171658A (en) | 1986-04-12 |
| CA1232953A (en) | 1988-02-16 |
| DE3568648D1 (en) | 1989-04-13 |
| EP0174694A1 (en) | 1986-03-19 |
| IE852213L (en) | 1986-03-11 |
| JPH083765B2 (en) | 1996-01-17 |
| NL8402764A (en) | 1986-04-01 |
| US4705966A (en) | 1987-11-10 |
| IE57080B1 (en) | 1992-04-22 |
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