EP0162943A1 - Integrated circuit for decoding traffic radio announcement identification signals - Google Patents

Integrated circuit for decoding traffic radio announcement identification signals Download PDF

Info

Publication number
EP0162943A1
EP0162943A1 EP84106270A EP84106270A EP0162943A1 EP 0162943 A1 EP0162943 A1 EP 0162943A1 EP 84106270 A EP84106270 A EP 84106270A EP 84106270 A EP84106270 A EP 84106270A EP 0162943 A1 EP0162943 A1 EP 0162943A1
Authority
EP
European Patent Office
Prior art keywords
frequency
signal
digital
announcement
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP84106270A
Other languages
German (de)
French (fr)
Other versions
EP0162943B1 (en
Inventor
Heinrich Dipl.-Ing. Pfeifer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Micronas GmbH
Original Assignee
Deutsche ITT Industries GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Deutsche ITT Industries GmbH filed Critical Deutsche ITT Industries GmbH
Priority to DE8484106270T priority Critical patent/DE3467648D1/en
Priority to EP84106270A priority patent/EP0162943B1/en
Priority to US06/736,633 priority patent/US4633517A/en
Priority to JP60115520A priority patent/JPS60264128A/en
Publication of EP0162943A1 publication Critical patent/EP0162943A1/en
Application granted granted Critical
Publication of EP0162943B1 publication Critical patent/EP0162943B1/en
Expired legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G08SIGNALLING
    • G08GTRAFFIC CONTROL SYSTEMS
    • G08G1/00Traffic control systems for road vehicles
    • G08G1/09Arrangements for giving variable traffic instructions
    • G08G1/091Traffic information broadcasting
    • G08G1/094Hardware aspects; Signal processing or signal properties, e.g. frequency bands

Definitions

  • the invention relates to an integrated circuit for decoding traffic announcement signals whose frequency, the announcement frequency, is the information for a traffic announcement and which are contained in the form of a carrier signal amplitude-modulated therewith in a broadcast signal received and already demodulated with a conventional radio receiver, cf. the preamble of claim 1.
  • the demodulated broadcast signal ds which is obtained by means of a conventional broadcast receiver, is fed to the mixing stage ms, whose mixed signal frequency fm is greater than the sum of the announcement frequency fa and its carrier frequency. Based on the system described in the two magazines mentioned at the beginning, this means that the mixed signal frequency should be greater than 57.125 kHz.
  • the announcement identification signal modulated onto the carrier signal is converted into a low-frequency position.
  • the output of the mixer ms lies on the analog low-pass filter af at the input of the analog-digital converter aw, to which the clock signal ft is fed.
  • the upper limit frequency of the low-pass filter af is at most equal to half the frequency of the scanning signal of the analog-digital converter aw, and its output is at the input of the digital absolute value generator br. This forms the amount of the input signal defined in the mathematical sense, i.e. its output signal is always positive and corresponds to the respective pure numerical value for both positive and negative input signals; both the number -7 and the number +7 become +7.
  • the digital signal x is generated in the baseband position, and this is for the announcement frequency fa or the frequency fb, fc deviating from it by at most + 1% or -1% with the first, second or third signal path a, b, c connected.
  • These consist of the digital resonance filter ra, rb, rc for the corresponding frequency fa, fb, in the signal flow direction. fc as their resonance frequency, the digital absolute value generator ba, bb, bc and the digital low-pass filter pa, pb, pc.
  • the magnitude generator br is the series connection of the first and the second further digital low-pass filter p1, p2, whose respective upper cut-off frequency is equal to that of the digital low-pass filters pa, pb, pc or the frequency corresponding to the settling time constant of the resonance filters ra, rb, rc is.
  • the constant multiplier m1 and m2 in a parallel branch.
  • the first signal path a leads to the respective minuend input m of the first, second, third and fourth comparators k1, k2, k3, k4, of which the subtrahend input s of the first and second comparators k1, k2 at the output of the first and second constant multiplier m1, m2 and the subtrahend input s of the third and fourth comparators k3, k4 is at the output of the second and third signal paths b, c.
  • the minuend-larger subtrahend output m> s of the first comparator k1 is located at the S input of the RS memory flip-flop ff, at the Q output of which the binary announcement identification signal dk is to be taken, and the respective minuend-smaller subtrahend output m ⁇ s of the second, third and fourth comparators k2, k3, k4 is located above the OR gate above at the R input of the RS memory flip-flop ff.
  • the constant d1, d2 of the respective constant multiplier ml, m2 is in each case less than one and is equal to the nominal degree of modulation of the announcement characteristic signal or equal to a specifiable fraction of the nominal degree of modulation.
  • FIG. 3 shows that the arrangement according to the invention can also be used with a plurality of broadcasting frequencies, as is the case, for example, for a standard customary in the USA.
  • the three signal paths a, b, c, the comparators k1 ... k4 assigned to them and the RS memory flip-flop ff are to be provided twice, each with a corresponding frequency rating.
  • the common circuit part is then also dimensioned with regard to the highest occurring announcement frequency.
  • the course of the resonance curves of the then six resonance filters is shown in FIG. 3, the resonance frequency of which is fa1, fb1, fcl; fa2, fb2, fc2 are designated.
  • the carrier amplitude, to which the announcement signal is modulated is measured by means of the magnitude generator br, which performs a full-wave rectification, comparable to a rectifier bridge for analog signals.
  • the announcement frequency is demodulated.
  • the three signal paths a, b, c serve as a selective level meter, the signal path a measuring the announcement frequency and the two signal paths b, c detecting closely adjacent interference signals. Only when there is an input signal on the three signal paths with a frequency between the intersections x, y of the resonance curve of the resonance filter ra with the respective resonance curve of the other two resonance filters is the output signal on signal path a greater than that on the other two signal paths b, c. By comparison using the comparators k3, k4 it is then determined and recorded whether the frequency of the input signal is in the range between x and y.
  • the RS memory flip-flop ff is set by means of the comparator k1 if the output signal on the signal path a is greater than the output signal of the absolute value generator br, which is filtered by the low-pass filters p1, p2 and multiplied by the factor d1.
  • the flip-flop ff is reset by means of the comparators k2 ... k4 and the OR gate og in each case when one of the output signals of the signal paths b, c is greater than that of the signal path a or this output signal is smaller than that by means of the low-pass filters p1 , p2 filtered and multiplied by the factor d2 output signal of the magnitude br.
  • a circuit hysteresis can therefore be set with the factor d2.
  • the invention can be implemented particularly advantageously in the form of integrated semiconductor circuits. Since it works exclusively, at least as far as the subcircuits behind the analog-digital converter aw are concerned, according to digital circuit principles, the usual Balbleiterscaria families for digital signal processing can be used, of which in particular the so-called MOS-integrated circuits are applicable, i.e. integrated insulating layer field effect transistor circuits. There is also the advantage that the inventive design with regard to the resonance frequencies of the resonance filters that are adjacent in the one percent range achieves very good interference suppression and reliable announcement frequency detection. Such a narrow resonance frequency measurement with analog resonance filters would only be achievable with considerable effort.

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Multimedia (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Circuits Of Receivers In General (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

Die Schaltung ist im wesentlichen als Digitalschaltung konzipiert. Das auf übliche Art demodulierte Rundfunksignal (ds) wird mittels des Analog-Digital-Wandlers (aw) digitalisiert, und dieses Signal wird mittels dreier Signalwege (a, b, c) mit jeweils einem Resonanzfilter (ra, rb, rc) mit eng benachbarten Resonanzfrequenzen und gleicher Resonanzkurve und Resonanzüberhöhung verarbeitet. Die Ausgangssignale dieser drei Signalwege werden mittels vier Komparatoren (kl...k4) und eines RS-Speicherflipflops (ff) so ausgewertet, daß am Q-Ausgang des Flipflops (ff) nur bei tatsächlich vorliegender Durchsagefrequenz (fa) das Durchsagekennsignal (dk) auftritt.

Figure imgaf001
The circuit is essentially designed as a digital circuit. The broadcast signal (ds) demodulated in the usual way is digitized by means of the analog-digital converter (aw), and this signal is converted by means of three signal paths (a, b, c), each with a resonance filter (ra, rb, rc) with closely adjacent ones Processed resonance frequencies and the same resonance curve and resonance exaggeration. The output signals of these three signal paths are evaluated by means of four comparators (kl ... k4) and an RS memory flip-flop (ff) in such a way that the announcement identification signal (dk) only appears at the Q output of the flip-flop (ff) if the announcement frequency (fa) is actually present. occurs.
Figure imgaf001

Description

Die Erfindung betrifft eine integrierte Schaltung zur Decodierung von Verkehrsfunk-Durchsagekennsignalen, deren Frequenz, die Durchsagefrequenz, die Information für eine Verkehrsdurchsage ist und die in Form eines damit amplitudenmodulierten Trägersignals in einem empfangenen und mit einem üblichen Rundfunkempfänger bereits demodulierten Rundfunksignal enthalten sind, vgl. den Oberbegriff des Anspruchs 1.The invention relates to an integrated circuit for decoding traffic announcement signals whose frequency, the announcement frequency, is the information for a traffic announcement and which are contained in the form of a carrier signal amplitude-modulated therewith in a broadcast signal received and already demodulated with a conventional radio receiver, cf. the preamble of claim 1.

In der Zeitschrift "Funkschau", 1974, Seiten 535 bis 538 ist das seinerzeit in Deutschland eingeführte und inzwischen in weiteren Ländern verwendete System zur Übermittlung von Verkehrsdurchsagen an Rundfunkhörer beschrieben, wobei unter anderem eine sogenannte Durchsagekennung während einer Verkehrsdurchsage gesendet wird. Zusätzlich hierzu werden auch noch Bereichskennsignale gesendet. Die Kennsignale sind recht niederfrequent und mittels Amplitudenmodulation dem Trägersignal, das beim bekannten System eine Frequenz von 57 kHz hat, aufmoduliert und werden durch ganzzahlige Frequenzteilung aus dem Trägersignal abgeleitet.In the magazine "Funkschau", 1974, pages 535 to 538, the system for transmitting traffic announcements to radio listeners, which was introduced in Germany at the time and is now used in other countries, is described, with what is known as an announcement identifier being transmitted during a traffic announcement. In addition to this, area identification signals are also sent. The characteristic signals are quite low-frequency and are modulated onto the carrier signal, which has a frequency of 57 kHz in the known system, by means of amplitude modulation and are derived from the carrier signal by integer frequency division.

Wie der Zeitschrift "Rundfunktechnische Mitteilungen", 1974, Seiten 193 bis 202, worin dieses Verkehrsfunksystem ebenfalls ausführlich beschrieben ist, entnommen werden kann, wurden die Systemparamet er seinerzeit so gewählt, daß die für den Verkehrsfunk erforderlichen empfängerseitigen Decoderschaltungen mit den üblichen, analoge Signale verarbeitenden Empfängerschaltungen kompatibel sind und insbesondere keine gegenseitige Störung auftritt. Die bisher üblichen Decoderschaltungen sind daher ebenfalls Analogschaltungen.As can be seen from the magazine "Rundfunk Technische Mitteilungen", 1974, pages 193 to 202, in which this traffic radio system is also described in detail, the system parameters were selected in such a way that the receiver-side decoder circuits required for traffic radio processing with the usual analog signals Receiver circuits are compatible and in particular no mutual Disorder occurs. The previously common decoder circuits are therefore also analog circuits.

Demgegenüber ist es Aufgabe der im Patentanspruch gekennzeichneten Erfindung, eine integrierte Schaltung zur Decodierung von Verkehrsfunk-Durchsagekennsignalen anzugeben, die nach den Prinzipien der Digitaltechnik arbeitet und somit weitgehend aus digitalen Teilschaltungen aufgebaut ist. Dabei soll die Ansprechzeit der Schaltung kleiner als eine Sekunde sein, z.B. 800 ms betragen, und die Durchsageerkennung soll unempfindlich gegenüber Rauschen sein.In contrast, it is an object of the invention characterized in the claim to provide an integrated circuit for decoding traffic announcement signals, which works according to the principles of digital technology and is thus largely constructed from digital subcircuits. The response time of the circuit should be less than one second, e.g. 800 ms, and the announcement detection should be insensitive to noise.

In der eigenen älteren europäischen Anmeldung 83 10 2412.4 ist eine integrierte Schaltung zur Decodierung von Verkehrsfunk-Bereichskennsignalen beschrieben, der eine für diesen Zweck modifizierte, mit der Erfindung vergleichbare Aufgabe zugrundeliegt. Die Erfindung greift bei der Lösung der ihr gestellten Aufgabe auf einige Teilschaltungen der älteren Anordnung zurück, die Gesamtanordnung entsprechend der Erfindung ist jedoch offensichtlich eine andere als die der älteren Anmeldung, was sich ohne weiteres aus der unterschiedlichen Zweckbestimmung ergibt.In the own older European application 83 10 2412.4, an integrated circuit for decoding traffic area code signals is described, which is based on a task modified for this purpose and comparable to the invention. The invention makes use of a few subcircuits of the older arrangement in order to achieve the object set for it, but the overall arrangement according to the invention is obviously different from that of the older application, which is evident from the different purpose.

Die Erfindung und ihre Vorteile werden nun anhand der

  • Figuren der Zeichnung näher erläutert.
  • Fig. 1 zeigt in Form eines Blockschaltbilds den Aufbau eines Ausführungsbeispiels der Erfindung,
  • Fig. 2 zeigt schematisch die Resonanzkurven der bei der Erfindung verwendeten Resonanzfilter, und
  • Fig. 3 zeigt schematisch die Lage der Resonanzkurven nach Fig. 2 für den Fall, daß zwei Durchsage-Kennsignale zu verarbeiten sind.
The invention and its advantages are now based on the
  • Figures of the drawing explained in more detail.
  • 1 shows in the form of a block diagram the structure of an embodiment of the invention,
  • Fig. 2 shows schematically the resonance curves of the resonance filters used in the invention, and
  • Fig. 3 shows schematically the position of the resonance curves of Fig. 2 for the case that two announcement identification signals are to be processed.

Als Ausführungsbeispiel ist in Fig. 1 das Blockschaltbild einer integrierten Schaltung zur Decodierung von Verkehrsfunk-Durchsage-Kennsignalen nach der Erfindung gezeigt. Zur weiteren Demodulation und Analog-Digital-Wandlung ist das demodulierte Rundfunksignal ds, das mittels eines üblichen Rundfunkempfängers gewonnen wird, der Mischstufe ms zugeführt, deren Mischsignal-Frequenz fm größer als die Summe aus der Durchsagefrequenz fa und aus deren Trägerfrequenz ist. Bezogen auf das in den eingangs genannten beiden Zeitschriften beschriebene System bedeutet dies, daß die Mischsignalfrequenz größer als 57,125 kHz sein soll. Mittels der Mischstufe ms wird das dem Trägersignal aufmodulierte Durchsagekennsignal in eine niederfrequente Lage umgesetzt.1 shows the block diagram of an integrated circuit for decoding traffic announcement identification signals according to the invention. For further demodulation and analog-digital conversion, the demodulated broadcast signal ds, which is obtained by means of a conventional broadcast receiver, is fed to the mixing stage ms, whose mixed signal frequency fm is greater than the sum of the announcement frequency fa and its carrier frequency. Based on the system described in the two magazines mentioned at the beginning, this means that the mixed signal frequency should be greater than 57.125 kHz. By means of the mixer stage ms, the announcement identification signal modulated onto the carrier signal is converted into a low-frequency position.

Der Ausgang der Mischstufe ms liegt über das analoge Tiefpaßfilter af am Eingang des Analog-Digital-Wandlers aw, dem das Taktsignal ft zugeführt ist. Die obere Grenzfrequenz des Tiefpaßfilters af ist höchstens gleich der halben Frequenz des Abtastsignals des Analog-Digital-Wandlers aw, und sein Ausgang liegt am Eingang des digitalen Betragsbildners br. Dieser bildet den im mathematischen Sinne definierten Betrag des Eingangssignals, d.h. sein Ausgangssignal ist immer positiv und entspricht sowohl bei positivem als auch bei negativem Eingangssignal dem jeweiligen reinen Zahlenwert; sowohl die Zahl -7 als auch die Zahl +7 wird also zu +7.The output of the mixer ms lies on the analog low-pass filter af at the input of the analog-digital converter aw, to which the clock signal ft is fed. The upper limit frequency of the low-pass filter af is at most equal to half the frequency of the scanning signal of the analog-digital converter aw, and its output is at the input of the digital absolute value generator br. This forms the amount of the input signal defined in the mathematical sense, i.e. its output signal is always positive and corresponds to the respective pure numerical value for both positive and negative input signals; both the number -7 and the number +7 become +7.

Am Ausgang des Betragsbildners br entsteht das Digitalsignal x in Basisband-Lage, und dieses ist für die Durchsagefrequenz fa bzw. die um höchstens +1% bzw. -1% davon abweichende Frequenz fb, fc mit dem ersten bzw. zweiten bzw. dritten Signalweg a, b, c verbunden. Diese bestehen jeweils in Signalflußrichtung aus dem digitalen Resonanzfilter ra, rb, rc für die entsprechende Frequenz fa, fb, fc als deren Resonanzfrequenz,dem digitalen Betragsbildner ba, bb, bc und dem digitalen Tiefpaß pa, pb, pc. Dessen jeweilige obere Grenzfrequenz ist kleiner als die doppelte Durchsagefrequenz fa, und die drei Resonanzfilter ra, rb, rc haben die gleiche Bandbreite und die gleiche Resonanzuberhöhung, wie dies die Fig. 2 veranschaulicht.At the output of the absolute value generator br, the digital signal x is generated in the baseband position, and this is for the announcement frequency fa or the frequency fb, fc deviating from it by at most + 1% or -1% with the first, second or third signal path a, b, c connected. These consist of the digital resonance filter ra, rb, rc for the corresponding frequency fa, fb, in the signal flow direction. fc as their resonance frequency, the digital absolute value generator ba, bb, bc and the digital low-pass filter pa, pb, pc. Whose respective upper cut-off frequency is less than twice the ra D urchsagefrequenz fa, and the three resonant filters, rb, rc have, as illustrated the same bandwidth and the same Resonanzuberhöhung FIG. 2.

Am Ausgang des Betragsbildners br liegt andererseits die Reihenschaltung des ersten und des zweiten weiteren digitalen Tiefpasses p1, p2, dessen jeweilige obere Grenzfrequenz gleich der der digitalen Tiefpässe pa, pb, pc bzw. gleich der der Einschwingzeitkonstanten der Resonanzfilter ra, rb, rc entsprechenden Frequenz ist. Auf diese folgt in je einem Parallelzweig der Konstantenmultiplizierer m1 bzw. m2.On the other hand, at the output of the magnitude generator br is the series connection of the first and the second further digital low-pass filter p1, p2, whose respective upper cut-off frequency is equal to that of the digital low-pass filters pa, pb, pc or the frequency corresponding to the settling time constant of the resonance filters ra, rb, rc is. This is followed by the constant multiplier m1 and m2 in a parallel branch.

Der erste Signalweg a führt zum jeweiligen Minuend-Eingang m des ersten, zweiten, dritten und vierten Komparators k1, k2, k3, k4, von denen der Subtrahend-Eingang s des ersten und des zweiten Komparators k1,k2 am Ausgang des ersten bzw. zweiten Konstantenmultiplizierers m1, m2 und der Subtrahend-Eingang s des dritten bzw. vierten Komparators k3, k4 am Ausgang des zweiten bzw. des dritten Signalwegs b, c liegt. Der Minuend-größer-Subtrahend-Ausgang m>s des ersten Komparators k1 liegt am S-Eingang des RS-Speicherflipflops ff, an dessen Q-Ausgang das binäre Durchsagekennsignal dk abzunehmen ist, und der jeweilige Minuend-kleiner-Subtrahend-Ausgang m<s des zweiten, des dritten bzw. des vierten Komparators k2, k3, k4 liegt über das ODER-Gatter og am R-Eingang des RS-Speicherflipflops ff.The first signal path a leads to the respective minuend input m of the first, second, third and fourth comparators k1, k2, k3, k4, of which the subtrahend input s of the first and second comparators k1, k2 at the output of the first and second constant multiplier m1, m2 and the subtrahend input s of the third and fourth comparators k3, k4 is at the output of the second and third signal paths b, c. The minuend-larger subtrahend output m> s of the first comparator k1 is located at the S input of the RS memory flip-flop ff, at the Q output of which the binary announcement identification signal dk is to be taken, and the respective minuend-smaller subtrahend output m < s of the second, third and fourth comparators k2, k3, k4 is located above the OR gate above at the R input of the RS memory flip-flop ff.

Die Konstante d1, d2 des jeweiligen Konstantenmultiplizierers ml, m2 ist jeweils kleiner als eins und gleich dem Nenn-Modulationsgrad des Durchsagekennsignals bzw. gleich einem vorgebbaren Bruchteil des Nenn-Modulationsgrades.The constant d1, d2 of the respective constant multiplier ml, m2 is in each case less than one and is equal to the nominal degree of modulation of the announcement characteristic signal or equal to a specifiable fraction of the nominal degree of modulation.

Die Fig. 3 zeigt, daß die Anordnung nach der Erfindung auch bei mehreren gesendeten Durchsagefrequenzen angewendet werden kann, wie dies beispielsweise für eine in den USA übliche Norm zutrifft. In diesem Falle sind die drei Signalwege a, b, c, die ihnen zugeordneten Komparatoren k1...k4 und das RS-Speicherflipflop ff doppelt vorzusehen mit jeweiliger entsprechender Frequenzbemessung.FIG. 3 shows that the arrangement according to the invention can also be used with a plurality of broadcasting frequencies, as is the case, for example, for a standard customary in the USA. In this case, the three signal paths a, b, c, the comparators k1 ... k4 assigned to them and the RS memory flip-flop ff are to be provided twice, each with a corresponding frequency rating.

Auch der gemeinsame Schaltungsteil ist dann im Hinblick auf die höchste vorkommende Durchsagefrequenz zu bemessen. Für eine derartige Anordnung ist in Fig. 3 der Verlauf der Resonanzkurven der dann vorhandenen sechs Resonanzfilter gezeigt, deren Resonanzfrequenz mit fa1, fb1, fcl; fa2, fb2, fc2 bezeichnet sind.The common circuit part is then also dimensioned with regard to the highest occurring announcement frequency. For such an arrangement, the course of the resonance curves of the then six resonance filters is shown in FIG. 3, the resonance frequency of which is fa1, fb1, fcl; fa2, fb2, fc2 are designated.

Mittels des Betragsbildners br, der, einer Gleichrichterbrücke bei analogen Signalen vergleichbar, eine Doppelweg-Gleichrichtung vornimmt, wird die Trägeramplitude, der das Durchsagesignal aufmoduliert ist, gemessen. Gleichzeitig wird die Durchsagefrequenz demoduliert. Die drei Signalwege a, b, c dienen als selektive Pegelmesser, wobei der Signalweg a die Durchsagefrequenz mißt und die beiden Signalwege b, c dazu eng benachbarte Störsignale detektieren. Nur bei einem Eingangssignal an den drei Signalwegen mit einer Frequenz zwischen den Schnittpunkten x, y der Resonanzkurve des Resonanzfilters ra mit der jeweiligen Resonanzkurve der beiden anderen Resonanzfilter ist das Ausgangssignal am Signalweg a größer als das an den beiden anderen Signalwegen b, c. Durch Vergleich mittels der Komparatoren k3, k4 wird dann festgestellt und festgehalten, ob die Frequenz des Eingangssignals im Bereich zwischen x und y liegt.The carrier amplitude, to which the announcement signal is modulated, is measured by means of the magnitude generator br, which performs a full-wave rectification, comparable to a rectifier bridge for analog signals. At the same time, the announcement frequency is demodulated. The three signal paths a, b, c serve as a selective level meter, the signal path a measuring the announcement frequency and the two signal paths b, c detecting closely adjacent interference signals. Only when there is an input signal on the three signal paths with a frequency between the intersections x, y of the resonance curve of the resonance filter ra with the respective resonance curve of the other two resonance filters is the output signal on signal path a greater than that on the other two signal paths b, c. By comparison using the comparators k3, k4 it is then determined and recorded whether the frequency of the input signal is in the range between x and y.

Mittels des Komparators k1 wird das RS-Speicherflipflop ff gesetzt, wenn das Ausgangssignal am Signalweg a größer als das mittels der Tiefpässe p1, p2 gefilterte und mit dem Faktor d1 multiplizierte Ausgangssignal des Betragsbildners br ist. Das Rücksetzen des Flipflops ff erfolgt mittels der Komparatoren k2...k4 und des ODER-Gatters og jeweils dann, wenn eines der Ausgangssignale der Signalwege b, c größer ist als das des Signalwegs a oder dieses Ausgangssignals kleiner wird als das mittels der Tiefpässe p1, p2 gefilterte und mit dem Faktor d2 multiplizierte Ausgangssignal des Betragsbildners br. Mit dem Faktor d2 läßt sich also eine Schaltungshysterese einstellen.The RS memory flip-flop ff is set by means of the comparator k1 if the output signal on the signal path a is greater than the output signal of the absolute value generator br, which is filtered by the low-pass filters p1, p2 and multiplied by the factor d1. The flip-flop ff is reset by means of the comparators k2 ... k4 and the OR gate og in each case when one of the output signals of the signal paths b, c is greater than that of the signal path a or this output signal is smaller than that by means of the low-pass filters p1 , p2 filtered and multiplied by the factor d2 output signal of the magnitude br. A circuit hysteresis can therefore be set with the factor d2.

Die Erfindung läßt sich besonders vorteilhaft in Form integrierter Halbleiterschaltungen realisieren. Da sie ausschließlich, jedenfalls was die Teilschaltungen hinter dem Analog-Digital-Wandler aw betrifft, nach digitalen Schaltungsprinzipien arbeitet, sind die für digitale Signalverarbeitung üblichen Balbleiterschaltungsfamilien anwendbar, wovon insbesondere die sogenannten MOS-integrierten Schaltungen anwendbar sind, d.h. integrierte Isolierschicht-Feldeffekt-Transistorschaltungen. Ferner ergibt sich der Vorteil, daß durch die erfindungsgemäße Bemessung hinsichtlich der im Ein-Prozent-Bereich benachbarten Resonanzfrequenzen der Resonanzfilter eine sehr gute Störbefreiung und sichere Durchsagefrequenz-Erkennung erreicht wird . Eine derartig enge Resonanzfrequenz-Bemessung bei analogen Resonanzfiltern wäre nur mit beträchtlichem Aufwand zu erreichen.The invention can be implemented particularly advantageously in the form of integrated semiconductor circuits. Since it works exclusively, at least as far as the subcircuits behind the analog-digital converter aw are concerned, according to digital circuit principles, the usual Balbleiterschaltung families for digital signal processing can be used, of which in particular the so-called MOS-integrated circuits are applicable, i.e. integrated insulating layer field effect transistor circuits. There is also the advantage that the inventive design with regard to the resonance frequencies of the resonance filters that are adjacent in the one percent range achieves very good interference suppression and reliable announcement frequency detection. Such a narrow resonance frequency measurement with analog resonance filters would only be achievable with considerable effort.

Claims (2)

1. Integrierte Schaltung zur Decodierung von Verkehrsfunk- Durchsage-Kennsignalen, deren Frequenz,die Durchsagefrequenz (fa), die Information für eine Verkehrsdurchsage ist und die in Form eines damit amplitudenmodulierten Trägersignals in einem empfangenen und mit einem üblichen Rundfunkempfänger bereits demodulierten Rundfunksignal (ds) enthalten sind, gekennzeichnet durch folgende Merkmale: - aus dem demodulierten Rundfunksignal (ds.) ist durch weitere Demodulation und Analog-Digital-Wandlung ein Digitalsignal (x) in Basisband-Lage erzeugt, - das Digitalsignal (x) ist für jede Durchsagefrequenz (fa; fa1,fa2) bzw. je eine um höchstens +1% bzw. -1% davon abweichende Frequenz (fb,fc; fb1, fb2; fc1,fc2) einem ersten bzw. einem zweiten bzw. dritten Signalweg, (a, b, c) zugeführt, der in Signalflußrichtung aus einem digitalen Resonanzfilter (ra, rb, rc) für die entsprechende Frequenz (fa, fb, fc; fa1, fb1, fc1; fa2, fb2, fc2) als deren Resonanzfrequenz, einem digitalen Betragsbildner (ba,bb, bc) und einem digitalen Tiefpaß (pa, pb, pc) besteht, dessen jeweilige obere Grenzfrequenz kleiner als die doppelte Durchsagefrequenz (fa) ist und welche drei Resonanzfilter (ra, rb, rc) die gleiche Bandbreite und die gleiche Resonanzüberhöhung haben, - das Digitalsignal (x) ist der Reihenschaltung eines ersten und eines zweiten weiteren digitalen Tiefpasses (p1, p2) zugeführt, dessen jeweilige obere Grenzfrequenz gleich der der digitalen Tiefpässe (pa, pb, pc) bzw. gleich der der Einschwingzeitkonstanten der Resonanzfilter (ra, rb, rc) entsprechenden Frequenz ist, - der erste Signalweg (a) führt zum jeweiligen Minuend-eingang (m) eines ersten, eines zweiten, eines dritten und eines vierten digitalen Komparators (k1, k2, k3, k4), von denen der Subtrahend-Eingang (s) des ersten Komparators (k1) über einen ersten Konstantenmultiplizierer (m1) und der des zweiten Komparators (k2) über einen zweiten Konstantenmultiplizierer (m2) am Ausgang des zweiten weiteren Tiefpasses (p2) und der Subtrahend-Eingang (s) des dritten bzw. des vierten Komparators (k3, k4) am Ausgang des zweiten bzw. des dritten Signalwegs (b, c) liegt, - der Minuend-größer-Subtrahend-Ausgang (m>s) des ersten Komparators (k1) liegt am S-Eingang eines RS-Speicherflipflops (ff), an dessen Q-Ausgang das binäre Durchsagekennsignal (dk) abzunehmen ist, - der jeweilige Minuend-kleiner-Subtrahend-Ausgang (m<s) des zweiten, des dritten bzw. des vierten Komparators (k2, k3, k4) liegt über ein ODER-Gatter (og) am R-Eingang des RS-Speicherflipflops (ff), und - die Konstante (d1, d2) des jeweiligen Konstantenmultiplizierers (m1, m2) ist jeweils kleiner als eins und gleich dem Nenn-Modulationsgrad des Durchsagekennsignals bzw. gleich einem vorgebbaren Bruchteil des Nenn-Modulationsgrads. 1. Integrated circuit for decoding traffic information D urchsage characteristic signals, the paging frequency (fa), is the frequency of the information for a traffic announcement and the previously demodulated a thus amplitude-modulated carrier signal in a received and with a conventional radio receiver in the form of broadcast signal (ds ) are included, characterized by the following features: a digital signal (x) in the baseband position is generated from the demodulated broadcast signal (ds.) by further demodulation and analog-digital conversion, - The digital signal (x) is for each announcement frequency (fa; fa1, fa2) or a frequency deviating by a maximum of + 1% or -1% therefrom (fb, fc; fb1, fb2; fc1, fc2) a first or a second or third signal path, (a, b, c), which in the signal flow direction from a digital resonance filter (ra, rb, rc) for the corresponding frequency (fa, fb, fc; fa1, fb1, fc1; fa2, fb2, fc2) as their resonance frequency, a digital absolute value generator (ba, bb, bc) and a digital low-pass filter (pa, pb, pc), whose respective upper cut-off frequency is less than twice the announcement frequency (fa) and which three resonance filters (ra , rb, rc) have the same bandwidth and the same resonance increase, - The digital signal (x) is fed to the series circuit of a first and a second further digital low-pass filter (p1, p2), whose respective upper cut-off frequency is equal to that of the digital low-pass filter (pa, pb, pc) or the settling time constant frequency corresponding to the resonance filter (ra, rb, rc), - The first signal path (a) leads to the respective minuend input (m) of a first, a second, a third and a fourth digital comparator (k1, k2, k3, k4), of which the subtrahend input (s) of the first comparator (K1) via a first constant multiplier (m1) and the second comparator (K2) through a second constant multiplier (m2) at the output of the second further low-pass filter (p2) and the S ubtrahend input (s) of the third and fourth Comparator (k3, k4) at the output of the second or third signal path (b, c), the minuend-larger-subtrahend output (m> s) of the first comparator (k1) is at the S input of an RS memory flip-flop (ff), at the Q output of which the binary announcement identification signal (dk) can be obtained, - The respective minuend-smaller-subtrahend output (m <s) of the second, the third or the fourth comparator (k2, k3, k4) is connected via an OR gate (above) to the R input of the RS memory flip-flop ( ff), and - The constant (d1, d2) of the respective constant multiplier (m1, m2) is in each case less than one and equal to the nominal degree of modulation of the announcement characteristic signal or equal to a predeterminable fraction of the nominal degree of modulation. 2. Integrierte Schaltung nach Anspruch 1, gekennzeichnet durch folgende Merkmale zur weiteren Demodulation und Analog-Digital-Wandlung: - das demodulierte Rundfunksignal (ds) ist einer Mischstufe (ms) zugeführt, deren Mischsignal-Frequenz (fm) größer als die Summe aus der Durchsagefrequenz und deren Trägerfrequenz (fa) ist, und - der Ausgang der Mischstufe (ms) liegt über ein analoges Tiefpaßfilter (af) am Eingang eines Analog-Digital-Wandlers (aw), welches analoge Tiefpaßfilter (af) eine obere Grenzfrequenz höchstens gleich der halben Frequenz des Abtastsignals (ft) des Analog-Digital-Wandlers (aw) hat, dessen Ausgang am Eingang eines weiteren digitalen Betragsbildners (br) liegt. 2. Integrated circuit according to claim 1, characterized by the following features for further demodulation and analog-digital conversion: - The demodulated broadcast signal (ds) is fed to a mixer (ms), the mixed signal frequency (fm) is greater than the sum of the announcement frequency and its carrier frequency (fa), and - The output of the mixer (ms) is via an analog low-pass filter (af) at the input of an analog-to-digital converter (aw), which analog low-pass filter (af) has an upper cutoff frequency which is at most equal to half the frequency of the scanning signal (ft) of the analog Has digital converter (aw), the output of which is at the input of another digital amount generator (br).
EP84106270A 1984-06-01 1984-06-01 Integrated circuit for decoding traffic radio announcement identification signals Expired EP0162943B1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
DE8484106270T DE3467648D1 (en) 1984-06-01 1984-06-01 Integrated circuit for decoding traffic radio announcement identification signals
EP84106270A EP0162943B1 (en) 1984-06-01 1984-06-01 Integrated circuit for decoding traffic radio announcement identification signals
US06/736,633 US4633517A (en) 1984-06-01 1985-05-21 Circuit for decoding traffic information message tone signals
JP60115520A JPS60264128A (en) 1984-06-01 1985-05-30 Decoding circuit of traffic information message tone signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP84106270A EP0162943B1 (en) 1984-06-01 1984-06-01 Integrated circuit for decoding traffic radio announcement identification signals

Publications (2)

Publication Number Publication Date
EP0162943A1 true EP0162943A1 (en) 1985-12-04
EP0162943B1 EP0162943B1 (en) 1987-11-19

Family

ID=8191962

Family Applications (1)

Application Number Title Priority Date Filing Date
EP84106270A Expired EP0162943B1 (en) 1984-06-01 1984-06-01 Integrated circuit for decoding traffic radio announcement identification signals

Country Status (4)

Country Link
US (1) US4633517A (en)
EP (1) EP0162943B1 (en)
JP (1) JPS60264128A (en)
DE (1) DE3467648D1 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3709523A1 (en) * 1987-03-23 1988-10-13 Bosch Gmbh Robert BROADCAST RECEIVER WITH AT LEAST ONE TRAFFIC RADIO DECODER
US5007069A (en) * 1987-11-13 1991-04-09 Talkie Tooter Inc. Decoding of signals using cophase and differentiating signal detection
US4962457A (en) * 1988-10-25 1990-10-09 The University Of Michigan Intelligent vehicle-highway system
US5164904A (en) * 1990-07-26 1992-11-17 Farradyne Systems, Inc. In-vehicle traffic congestion information system
JP3258171B2 (en) * 1994-06-08 2002-02-18 パイオニア株式会社 PTY burst signal detection method
US5900825A (en) * 1996-08-01 1999-05-04 Manitto Technologies, Inc. System and method for communicating location and direction specific information to a vehicle
US7908080B2 (en) 2004-12-31 2011-03-15 Google Inc. Transportation routing

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0035166A1 (en) * 1980-03-01 1981-09-09 Licentia Patent-Verwaltungs-GmbH Digital receiver
DE3233829A1 (en) * 1982-09-11 1984-03-15 Blaupunkt-Werke Gmbh, 3200 Hildesheim Method for demodulating amplitude-modulated input signals and circuit arrangement therefor

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5765025A (en) * 1980-10-08 1982-04-20 Pioneer Electronic Corp Receiver for traffic informatin
DE3121034C2 (en) * 1981-05-27 1987-01-02 Blaupunkt-Werke Gmbh, 3200 Hildesheim FM receiver
US4561115A (en) * 1984-03-08 1985-12-24 Itt Industries, Inc. Decoder for traffic information regional tone signals

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0035166A1 (en) * 1980-03-01 1981-09-09 Licentia Patent-Verwaltungs-GmbH Digital receiver
DE3233829A1 (en) * 1982-09-11 1984-03-15 Blaupunkt-Werke Gmbh, 3200 Hildesheim Method for demodulating amplitude-modulated input signals and circuit arrangement therefor

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
FUNKSCHAU, Nr. 14, Juli 1982, Seiten 41-46, München, DE; U. BUHSE et al.: "Ein-Chip-Decoder für Zweikanal-Fernsehton" *

Also Published As

Publication number Publication date
JPH0423966B2 (en) 1992-04-23
JPS60264128A (en) 1985-12-27
US4633517A (en) 1986-12-30
DE3467648D1 (en) 1987-12-23
EP0162943B1 (en) 1987-11-19

Similar Documents

Publication Publication Date Title
EP0308520B1 (en) Digital-demodulator
EP0210292A1 (en) Frequency demodulation circuit with zero-crossing counter
EP0162943B1 (en) Integrated circuit for decoding traffic radio announcement identification signals
DE1298120B (en) Method and circuit arrangement for the coherent demodulation of synchronous, frequency-modulated Duobinaer signals
EP0204849B1 (en) Circuit arrangement for filtering and demodulating a frequency-modulated signal with at least one sound signal
EP0080157A2 (en) Method and arrangement for demodulating frequency-modulated signals using sampled values
EP0512133B1 (en) Method for automatic sweep tuning of audio carriers for satellite television
DE19504566A1 (en) Multi-standard television receiver
EP0793361B1 (en) Circuit for decoding auxiliary data in a broadcast signal
DE4338700C2 (en) Circuit arrangement for the detection of adjacent channel interference in a stereo multiplex broadcast receiver
DE1762423B2 (en) SIGNAL TRANSMISSION PROCEDURE
DE3131892C2 (en) Frequency separator
EP0161325A1 (en) Digital frequency discriminator demodulating a digital signal
DE1262369B (en) FM / AM converter
EP0119280B1 (en) Integrated circuit for decoding radio broadcast traffic area identification signals
DE3505950C2 (en)
EP0691049B1 (en) Method for deriving a quality signal dependent on the quality of a received multiplex signal
DE3789498T2 (en) MAC FORMAT WITH ALTERNATING DC CURRENT LEVEL AND CLOCK RECOVERY SIGNALS.
EP0626786A1 (en) Circuit for recognising the sound standard in a television receiver
DE2533946C3 (en) Additional circuit for recognizing a pilot signal
EP0670643B1 (en) Method and circuit for digital frame synchronisation
DE4311933A1 (en) Circuit arrangement for generating a stop signal for a station search
EP1118163A1 (en) Filtering of a receive frequency band
DE2029622C3 (en) Pulse shaping circuit
DE3411259A1 (en) Method for distinguishing an identification signal modulating a carrier signal and arrangement for carrying out the method

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 19850411

AK Designated contracting states

Designated state(s): DE FR GB IT NL

17Q First examination report despatched

Effective date: 19870114

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE FR NL

REF Corresponds to:

Ref document number: 3467648

Country of ref document: DE

Date of ref document: 19871223

ET Fr: translation filed
PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed
REG Reference to a national code

Ref country code: FR

Ref legal event code: DL

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 19950623

Year of fee payment: 12

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 19960515

Year of fee payment: 13

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: NL

Payment date: 19960529

Year of fee payment: 13

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Effective date: 19970301

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: NL

Effective date: 19980101

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 19980227

NLV4 Nl: lapsed or anulled due to non-payment of the annual fee

Effective date: 19980101

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST