EP0154551A3 - Vorrichtung, die einen ersten Prozessor befähigt, einen zweiten Prozessor zu veranlassen, um eine Datenübertragung zwischen besagten Prozessoren zu bewirken - Google Patents
Vorrichtung, die einen ersten Prozessor befähigt, einen zweiten Prozessor zu veranlassen, um eine Datenübertragung zwischen besagten Prozessoren zu bewirken Download PDFInfo
- Publication number
- EP0154551A3 EP0154551A3 EP85301542A EP85301542A EP0154551A3 EP 0154551 A3 EP0154551 A3 EP 0154551A3 EP 85301542 A EP85301542 A EP 85301542A EP 85301542 A EP85301542 A EP 85301542A EP 0154551 A3 EP0154551 A3 EP 0154551A3
- Authority
- EP
- European Patent Office
- Prior art keywords
- processor
- data
- processors
- transfer
- enabling
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- Quality & Reliability (AREA)
- Multi Processors (AREA)
- Information Transfer Systems (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US58668184A | 1984-03-06 | 1984-03-06 | |
US586681 | 1984-03-06 |
Publications (2)
Publication Number | Publication Date |
---|---|
EP0154551A2 EP0154551A2 (de) | 1985-09-11 |
EP0154551A3 true EP0154551A3 (de) | 1987-12-16 |
Family
ID=24346736
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP85301542A Ceased EP0154551A3 (de) | 1984-03-06 | 1985-03-06 | Vorrichtung, die einen ersten Prozessor befähigt, einen zweiten Prozessor zu veranlassen, um eine Datenübertragung zwischen besagten Prozessoren zu bewirken |
Country Status (2)
Country | Link |
---|---|
EP (1) | EP0154551A3 (de) |
JP (1) | JPS61855A (de) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3750311T2 (de) * | 1986-05-30 | 1995-03-30 | Bull Hn Information Syst | Gerät und Verfahren zur Übertragung zwischen Prozessoren. |
DE69218644T2 (de) * | 1991-01-30 | 1997-09-11 | Canon Kk | Kontrollverfahren und Vorrichtung der Verbindung zwischen Mikrocomputer(n) und einem Zentralrechner |
DE19653429C2 (de) * | 1996-12-20 | 1998-10-15 | Siemens Ag | Verfahren zur Überprüfung der Funktionsfähigkeit einer Recheneinheit |
JP3263362B2 (ja) | 1998-06-05 | 2002-03-04 | 三菱電機株式会社 | データ処理装置 |
CA2335450A1 (en) * | 1998-06-24 | 1999-12-29 | Ricos International, Inc. | Method and system for controlling a digital subscriber line |
US7158536B2 (en) | 2004-01-28 | 2007-01-02 | Rambus Inc. | Adaptive-allocation of I/O bandwidth using a configurable interconnect topology |
US9547553B1 (en) | 2014-03-10 | 2017-01-17 | Parallel Machines Ltd. | Data resiliency in a shared memory pool |
US9781027B1 (en) | 2014-04-06 | 2017-10-03 | Parallel Machines Ltd. | Systems and methods to communicate with external destinations via a memory network |
US9690713B1 (en) | 2014-04-22 | 2017-06-27 | Parallel Machines Ltd. | Systems and methods for effectively interacting with a flash memory |
US9594688B1 (en) | 2014-12-09 | 2017-03-14 | Parallel Machines Ltd. | Systems and methods for executing actions using cached data |
US9753873B1 (en) | 2014-12-09 | 2017-09-05 | Parallel Machines Ltd. | Systems and methods for key-value transactions |
US9639473B1 (en) | 2014-12-09 | 2017-05-02 | Parallel Machines Ltd. | Utilizing a cache mechanism by copying a data set from a cache-disabled memory location to a cache-enabled memory location |
US9781225B1 (en) | 2014-12-09 | 2017-10-03 | Parallel Machines Ltd. | Systems and methods for cache streams |
US9639407B1 (en) | 2014-12-09 | 2017-05-02 | Parallel Machines Ltd. | Systems and methods for efficiently implementing functional commands in a data processing system |
US9632936B1 (en) | 2014-12-09 | 2017-04-25 | Parallel Machines Ltd. | Two-tier distributed memory |
US11762743B2 (en) * | 2021-06-28 | 2023-09-19 | International Business Machines Corporation | Transferring task data between edge devices in edge computing |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3678467A (en) * | 1970-10-20 | 1972-07-18 | Bell Telephone Labor Inc | Multiprocessor with cooperative program execution |
US4149244A (en) * | 1976-06-07 | 1979-04-10 | Amdahl Corporation | Data processing system including a program-executing secondary system controlling a program-executing primary system |
EP0044033A1 (de) * | 1980-07-11 | 1982-01-20 | Siemens Aktiengesellschaft | Einrichtung zum schnellen blockorientierten Datentransfer zwischen zwei sich im Betrieb befindlichen Rechnern |
US4355354A (en) * | 1978-06-29 | 1982-10-19 | Standard Oil Company (Indiana) | Interface apparatus for coupling a minicomputer to a microcomputer for the transfer of data between them and method for using same |
EP0068994A2 (de) * | 1981-06-18 | 1983-01-05 | The Bendix Corporation | Prüfverfahren mit Rechnern |
-
1985
- 1985-03-06 EP EP85301542A patent/EP0154551A3/de not_active Ceased
- 1985-03-06 JP JP4449085A patent/JPS61855A/ja active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3678467A (en) * | 1970-10-20 | 1972-07-18 | Bell Telephone Labor Inc | Multiprocessor with cooperative program execution |
US4149244A (en) * | 1976-06-07 | 1979-04-10 | Amdahl Corporation | Data processing system including a program-executing secondary system controlling a program-executing primary system |
US4355354A (en) * | 1978-06-29 | 1982-10-19 | Standard Oil Company (Indiana) | Interface apparatus for coupling a minicomputer to a microcomputer for the transfer of data between them and method for using same |
EP0044033A1 (de) * | 1980-07-11 | 1982-01-20 | Siemens Aktiengesellschaft | Einrichtung zum schnellen blockorientierten Datentransfer zwischen zwei sich im Betrieb befindlichen Rechnern |
EP0068994A2 (de) * | 1981-06-18 | 1983-01-05 | The Bendix Corporation | Prüfverfahren mit Rechnern |
Non-Patent Citations (1)
Title |
---|
ELECTRICAL COMMUNICATION, vol. 57, no. 3, 1982, pages 187-194, Heidenheim, DE; H. NYMAN et al.: "Data modem evolution" * |
Also Published As
Publication number | Publication date |
---|---|
JPS61855A (ja) | 1986-01-06 |
EP0154551A2 (de) | 1985-09-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0154551A3 (de) | Vorrichtung, die einen ersten Prozessor befähigt, einen zweiten Prozessor zu veranlassen, um eine Datenübertragung zwischen besagten Prozessoren zu bewirken | |
EP0148478A3 (en) | A data processor with control of the significant bit lenghts of general purpose registers | |
AU568395B2 (en) | An arrangement for the generation of information and/or an instruction intended for input to the program memory of computer | |
EP0340900A3 (de) | Multiprozessor-Zeitablaufsteuerung | |
AU588815B2 (en) | Emulation of a data processing system | |
EP0136560A3 (en) | Loosely coupled multiprocessor system capable of transferring a control signal set by the use of a common memory | |
EP0473420A3 (en) | Virtual long instruction word memory architecture for digital signal processor | |
AU559960B2 (en) | Error recovery system in data processor | |
AU562415B2 (en) | Data processor | |
EP0121044A3 (en) | Method of providing an extended error diagnosis to assist the user in an interactive data entry system | |
AU554059B2 (en) | A data processor system having improved data throughput of multiprocessor system | |
ES532492A0 (es) | Una instalacion de control de almacenamiento intermedio en un procesador de datos | |
JPS54100634A (en) | Computer | |
IT1237008B (it) | Trasduttori elettroacustici direttivi comportanti un guscio stagno in due parti | |
AU3031284A (en) | Word processor | |
EP0270081A3 (de) | Während einer Instruktionsausführung eine Unterbrechungsanforderung empfangender Mikroprogrammkontrolleur | |
AU560527B2 (en) | Data processor | |
AU567557B2 (en) | Start-up control system and vessel for lmfbr | |
AU557162B2 (en) | Data processor | |
EP0100240A3 (de) | Verfahren und Vorrichtung zur Systemgenerierung | |
EP0257252A3 (de) | Mikroprozessor | |
DE3376698D1 (en) | A timing control system in a data processor | |
EP0183486A3 (de) | Mikroprozessor-Interface für Anwendung in einem Fernmeldesystem | |
JPS5712545A (en) | Data processor and its module structure | |
JPS575142A (en) | Data processor with interface function |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
AK | Designated contracting states |
Designated state(s): DE FR GB NL |
|
PUAL | Search report despatched |
Free format text: ORIGINAL CODE: 0009013 |
|
AK | Designated contracting states |
Kind code of ref document: A3 Designated state(s): DE FR GB NL |
|
17P | Request for examination filed |
Effective date: 19880615 |
|
17Q | First examination report despatched |
Effective date: 19891026 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION HAS BEEN REFUSED |
|
18R | Application refused |
Effective date: 19910622 |
|
RIN1 | Information on inventor provided before grant (corrected) |
Inventor name: QURESHI, SHAHID U.H. Inventor name: CHAMBERLIN, GEORGE P. |
|
P01 | Opt-out of the competence of the unified patent court (upc) registered |
Effective date: 20230522 |