EP0149399B1 - Graphic display controller - Google Patents

Description

The present invention relates to graphic display controllers ensuring the coupling between a pilot microprocessor and a graphic display device and its associated screen memory. One of the main roles of such a controller is to ensure the management of the screen memory both for the display and maintenance of the stored image and for the modifications of this stored image from guiding parameters. received from the pilot microprocessor. The present invention relates more specifically to a graphic display controller on the interface circuits with the screen memory making it possible to ensure modifications on an image the elementary points of which are each defined with a plurality of appearance bits, in number greater than 2, which are stored in as many individual memory plans assigned to the different possible display aspects.

A graphic display controller, such as that known under the name J.LPD 7220 from the firm NEC and described in the article entitled “Graphic coprocessor, J.LPD 7220: architecture and operation published in the review Minis et Micros n ° 196 , October 1983 - pages 63 and following, essentially comprises a control processor, a coupling interface with the pilot microprocessor and a coupling interface with the graphic display device and its screen or maintenance memory. The interface between the pilot microprocessor and the control processor essentially comprises a bidirectional bus for data and address transfer which enables the creation of an image displayed by the graphic display device. The interface between the control processor and the graphic display device essentially comprises a video sync generator which provides the basic signals for scanning the screen. The interface between the control processor and the screen memory includes a memory sequence generator which develops two cycles for the screen memory: a refresh cycle for the displayed image and a cycle for modifying the stored image. ; this memory sequence generator delivers two control signals necessary for controlling the screen memory. This interface between the maintenance or screen memory control processor further comprises, connected to the processor by an address and data bus, a circuit for multiplexing the image data and their addresses, ensuring on the one hand the bilateral data exchanges between the control processor and the memory and on the other hand the addressing of the memory.

The control processor is programmed to essentially ensure the automatic management of the screen memory during the display and maintenance of the stored image, the definition of the modifications to be carried out on the stored image from the signals it receives from the pilot microprocessor and the execution of these modifications.

The circuit for multiplexing data and addresses, the interface between the control processor and the screen memory advantageously makes it possible to have image data coming from or going to memory on the same bidirectional bus. screen, or addresses relating to this data. It is associated on the one hand with an address output circuit and on the other hand with a data switching circuit.

The address output circuit advantageously makes it possible to store the image data in the form of words, in particular of 16 bits, and to allocate only one address per word, and, thereby, to make compatible the response time of the memories and of the control processor with a frequency of scanning of the image points on the screen and a density of high image points which ensure an effect of displayed image continuity. This address output circuit also makes the length of the addresses compatible, which in particular must be defined on at least 13 bits for an image of 512 × 256 points defined in words of 16 bits, with the existing current memories with bus. addressing to 8 conductors, by delivering in two stages such a complete address received at one time from the data and address multiplexing circuit.

The data switching circuit of the screen memory control processor ultertace has the function, during the stored image modification cycles, of establishing the appropriate connections between a bus connecting it to the screen memory and the bidirectional bus connecting it to the control processor through the data and address multiplexing circuit, to replace a data word read from the screen memory with a modified data word defined at the level of the control processor. This substitution is carried out through a logical routing circuit.

In graphic display systems offering several possibilities of image display aspect either with a brightness scale and flashing for monochrome systems, or in different colors and possibly flashing for polychrome systems, it is also known to decompose the screen memory associated with the graphic display device into different memory planes each assigned to memorizing the image in one of its aspects.

In known graphic display controllers, of the aforementioned type, the control processors are however capable of processing only one aspect bit at a time. If they are therefore perfectly suited for controlling the modification of an image stored in the screen memory associated with a monochrome display device, without brightness scale or flashing On the other hand, they cannot be used directly, with a graphic display device with display with brightness scale or in several colors, to control the modification of the image stored in the different memory planes. It would then be possible either to use a command processor per memory plane or to use only one command processor but to assign it successively to each of the memory planes, in order to carry out modifications in different memory planes. The disadvantages of such resulting controllers would be the cost for the first solution above and the slowness for the second.

The object of the present invention is to avoid these drawbacks by allowing, by means of a particular interface circuit between the control processor and the screen memory in the form of a plurality of memory planes, simultaneous access to several memory plans for modifying the stored image.

• - un générateur de mot fictif de données d'image, dit mot de transposition, dont les bits respectifs sont de même valeur,
• - une pluralité de dispositifs correcteurs de données chacun relié d'une part à l'un des plans mémoire auquel il est affecté, pour recevoir de ce plan mémoire un mot de données lu et lui délivrer un mot de données modifié, et, d'autre part, au microprocesseur pilote pour recevoir un signal de commande de mode opératoire,
• - et un circuit d'aiguillage couplant ledit générateur de mot de transposition audit processeur de commande et délivrant, en réponse, sur un bus de sortie relié en commun auxdits dispositifs correcteurs, un mot dit de masque définissant en position, dans les mots de données reçus par les différents dispositifs correcteurs des plans mémoire respectifs, au moins l'un des bits à modifier.

The present invention relates to a graphic display controller comprising a control processor, a bilateral exchange interface circuit with a pilot microprocessor and output interface circuits controlled by the control processor and connected to a graphic display and an associated screen memory constituted by a plurality of memory planes assigned to the storage of an image for its different display aspects, respectively, and in which said output interface circuits include means for generating a video sync signal, a so-called memory sequence signal formed by image refresh cycles for its display and data modification cycles for the modification of the stored image and an address signal from said screen memory , for reading and writing words from image data, and a data switch connected to said screen memory for modifying the image ge stored at the address defined by the addressing signal during each data modification cycle, characterized in that said data switch comprises:

• a dummy word generator of image data, called transposition word, the respective bits of which have the same value,
• - A plurality of data correcting devices each connected on the one hand to one of the memory plans to which it is assigned, to receive from this memory plan a read data word and to deliver a modified data word to it, and, on the other hand, to the pilot microprocessor for receiving an operating mode control signal,
• - And a switching circuit coupling said transposition word generator to said control processor and delivering, in response, on an output bus connected in common to said correcting devices, a so-called mask word defining in position, in the data words received by the various correcting devices of the respective memory plans, at least one of the bits to be modified.

According to another characteristic, each of said data correcting devices comprises means for performing logical functions of binary value inversion, forcing to value 0, forcing to value 1, of each of the bits of the data word read that 'it receives from the memory plan to which it is assigned.

Other characteristics and advantages of the present invention will appear during the description of an embodiment of the graphic display controller, according to the invention, illustrated in the single figure of the attached drawing.

The graphic display controller illustrated ensures the coupling between a pilot microprocessor 1 and a graphic display device 2, with cathode-ray tube for color display 20 and associated video signal generator 21, and its screen memory made up, here, of four separate memory plans 3A, 3B, 3C and 3D. These four memory planes are assigned to the memorization of the image defined in several aspects, for example in three different colors and a blinking aspect. Each memory plane will therefore contain, for each image point, a bit for controlling all or nothing each of the three beams of the three-color tube and the blinking aspect of this point. Each of these memory planes 3A to 3D advantageously stores the image in the form of words at 16 bits per address, the bits defining successive points of this image for each display aspect. The memory plans will therefore be connected to the display device 2 through individual parallel-series converters 4A, 4B, 4C and 4D; the outputs of these converters supply the video signal generator 21.

The graphic display controller essentially comprises a control processor 5, an interface circuit with the pilot microprocessor, represented simply by a bidirectional link bus 6 between the pilot microprocessor 1 and the. control processor 5, but also including in particular memories, and output interface circuits, essentially 7 to 10, between the control processor 5 and the display device 2 and its screen memory 3A to 3D.

The control processor essentially manages the operations for displaying and maintaining the stored image and the operations for modifying the stored image, as a function of the image storage mode adopted which, in the example chosen, is performed in the form of 16-bit words per address in the various memory plans. A clock signal generator, not shown, supplies it with clock signals H necessary for the management of these operations carried out from the addresses for reading or writing in the memory planes, relating to the 16-bit words concerned, that he elaborates. For modifications of the stored image, to be executed in response to a command received from the pilot microprocessor, this command processor "interprets the command received, determines the image points to modify, and defines for each image point to modify the address of the stored word containing it and the position of the bit concerned in this word. Such a control processor is as such known. It will for example conform to that of the graphic display controller known under the reference µPD 7220 from the company NEC.

The output interface circuits include a video synchro generator 7, connected by a bus 17 to the control processor 5, generating the control signals for scanning the screen of the display device 2 which it delivers to it by links. symbolized at 27. They further include a memory sequence generator 8 connected by a bus 18 to the control processor 5, generating for the screen memory, or the four memory planes which constitute it, two operating cycles, the one for the display and the maintenance of the image called image refresh cycle and the other for the modification of the image called image modification cycle, and delivering two signals ALE (Address Latch Enable Output) and DBIN (Display Memory Read Input Flag) for the corresponding control of screen memory. This memory sequence generator 8 is connected to a logic circuit 28 for controlling the screen memory which consequently applies, to the memory planes 3A to 3D, read signals R during the image refresh cycles and signals of reading R then of writing W during the image modification cycles.

These interface circuits also include a multiplexer circuit for image data and addresses 9 connected to the control processor 5 by a bus 19. This multiplexer circuit 9 is connected by the same bidirectional bus 29 on the one hand to a circuit of address output 30 itself connected to the addressing inputs of each memory plane by another bus 39 with 8 conductors, in accordance with the usual design of the memory plane addressing buses and on the other hand to a circuit of data switching 10. This multiplexer circuit 9 allows the same bus 29 to be used as the address output bus and the data input or output bus. The address output circuit 30 makes compatible the length of the addresses at least 13 bits necessary for the storage of 2 ¹³ words each of 16 bits defining the image memorized in each memory plane, for a display of the image in 256 lines each at 512 image points, with the length of the possible 8-bit addresses on the addressing inputs of each memory plane. It delivers each address word with at least 13 bits, which it receives from bus 29, in two stages on bus 39 and in the form of two successive address words. This address output circuit is controlled by the ALE signal delivered by the memory sequence generator 8.

These output interface circuits, comprising the video sync generator 7, the memory sequence generator 8 and the multiplexer circuit 9 are also as such already known, they are in particular in accordance with those incorporated in the aforementioned graphic display controller. from the firm NEC. During the image refresh cycles, these interface circuits 7 to 9 ensure the simultaneous reading control of the four memory planes, triggered by the ALE signal and transmitted by the signal R to the memory planes. During this read operation, the four 16-bit words per stored address are applied by buses 43A, 43B, 43C and 43D to the corresponding serial-parallel converters 4A to 4D which deliver them, bit by bit, to the display device 2 in synchronism with the screen scan.

The data switch 10 connected to the bidirectional bus 29 is intended to ensure the modifications of the stored image, on the basis of guiding parameters defining these modifications delivered by the pilot microprocessor 1 and received by the control processor 5.

According to the present invention, this data switch 10 makes it possible to intervene simultaneously on different memory planes from the single control processor 5 of this graphic display controller.

The data switch according to the invention comprises a routing circuit 11 connected to the bidirectional bus 29 and having an input bus 22 and an output bus 23; it also receives the DBIN signal for its command, during a memorized image modification cycle. The bus 29 provides the link between the routing circuit 11 and the control processor 5 through the multiplexer circuit 9. The bus 22 is connected to a generator 12 of word dp fictitious image data called hereinafter transposition word , of the same length as that of the image data words stored by address but the bits of which are all set, under the control of the pilot microprocessor 1, to the same value, for example 0, and force the bus 22 to this value. The output bus 23 is connected to four data correcting devices 13A, 13B, 13C and 13D assigned to the four memory planes 3A, 3B, 3C and 3D respectively, to which it transmits a modification control word, hereinafter called mask.

Each of these data correcting devices has, in addition to control inputs connected to the bus 23, data inputs and outputs connected to the outputs and data inputs of the memory plane to which this correction device is assigned and operating mode control inputs linked to the pilot microprocessor 1. Buses 43A to 43D transmit the data from the memory plans to the corresponding corrective devices. Buses 24A to 24D transmit the data from these correcting devices to the corresponding memory plans. Links 25A, 25B, 25C and 25D, belonging to an output bus 25 of the pilot microprocessor 1, ensure the distribution of control signals emitted by the pilot microprocessor on the correcting devices 13A to 13D.

In this arrangement, the buses 29, 22, 23, 43A to 43D, 24A to 24D will have a capacity of at least 16 conductors, for the 16-bit words which they transmit put, buses 25 and 39 will advantageously be 8 conductors.

This interface circuit 10 intended to ensure the modification of the stored image data words cooperates with the multiplexing circuit 9 during each data modification cycle generated by the generator 8. In a first phase of a modification cycle data, via the bus 29, the address output circuit 30 receives the address word of the image data word to be modified. The address of this word delivered in two stages on the bus 39 will allow the reading of the words of corresponding image data stored in the various memory planes and their reception in the respective correcting devices 13A to 13D.

In a next phase of this cycle of modification of stored image data, the routing circuit 11 provides the appropriate connections between the buses 22, 29 and 23. This routing circuit receives the transposition word from the bus 22, and transmits it to the control processor 5 by bus 29 and the multiplexing circuit 9. It receives in return by bus 29, a new word of the same length, developed in response to the transposition word received and at the bit position to be modified available to the control processor, the needle and delivers it on its output bus 23.

During these latter operations, at the level of the control processor 5, the transposition word received, by the very fact of its composition of bits of the same level, cannot "denature the bit position information to be modified which is available to this processor. It therefore follows that the bit position function to be modified is found in the new resulting word developed and applied, by buses 29 and 23, to all the data correcting devices 13A to 13D which use it individually as mask word for all the bits of the data image word received, except for the bit to be modified.

At the level of these correcting devices, the modification, defined simultaneously in position by the word mask, is moreover defined individually in kind by the various control signals which are transmitted to them from the pilot microprocessor by the bus 25. Due to the definition in all or nothing of each picture point for each of its different aspects, which has been adopted, the possible modifications of the bit designated in each word of image data will be limited; they will consist either of a forcing to the value 1, or to a forcing to the value 0, or to an inversion of its value. The control signal applied to each of the four correcting devices by two of the eight links on bus 25 will therefore define the absence of modification or one of these possible modifications for each of the image data words received from the memory card concerned. . Each correcting device therefore generates the resulting image data word from the image data word received from the memory plane to which it is assigned, from the mask word and from the specific control signal which are applied to it.

The correcting devices 13A to 13D implementing simple logic functions, with a selection of one of these functions by the received control signal, are of obvious design for those skilled in the art, consequently, a particular structure of these devices is therefore not given below.

In a last phase of the image data modification cycle, each of the four memory planes, written by the signal W delivered by the memory sequence generator 8, receives the word of image data available on the sound outputs. corrective device. This image data word is stored at the reading address of the memory planes, defined at the start of this data modification cycle.

Thanks to the data switch, any data modification cycle relates both to the different memory planes of the image and this by using only one control processor. From the described embodiment, it is easily understood that a modification to be carried out relating only to some of the memory planes can be easily obtained from the control signals applied to the correcting devices and that this modification can also be different from one of these. memory plans to another.

As a variant, a modification to be carried out on all of the memory plans, or simply on a part of them, can also be obtained by distribution, through logic gates assigned to each of the memory plans and individually controlled accordingly. by the pilot microprocessor, of the write signal W, at the end of the data modification cycle.

In addition, it will be noted that another advantage of the present invention lies in the easy adaptation of a monochrome graphic display controller into a full color graphic display controller or to a plurality of image display aspects. In fact, in this latter controller, the control processor and its interface circuits with the pilot microprocessor and the screen memory remain unchanged, except for the data switch. This data switch itself, due to the application of the transposition word, which constitutes a particular fictitious word of image data, advantageously uses as switching circuit 11 the data switching circuit of a monochrome controller this although, from one to the other of these two types of controllers, the resulting function (namely transfer to the output bus of the modified word for the switching circuit in a monochrome display controller and transfer to the mask word output bus for the routing circuit in the controller according to the present invention) is different.

The data switch circuit according to the invention and the resulting graphic display controller lend themselves to the use of an image memory with separate memory planes for each aspect organized in words of any length, different from 16 bits, according to the charac control processor. It can in particular also, by using functions available in the control processor to define therein at the same time the positions of several bits to be modified in the same image data word, deliver a mask signal translating, at the level of the correcting devices , the positions of these different bits in the image data word that each of them receives.

Claims (2)

1. A graphic visualization controller comprising a command processor, a bilateral interface exchange circuit with a control microprocessor and output interface circuit controlled by the command processor and connected with a graphic visualization device and an associated screen memory constituted by a plurality of memory planes intended for storing an image in its different aspects of display, respectively, and in which the said output interface circuits comprise means for generating a video sync signal, a signal termed the memory sequence formed by image refresh cycles for displaying same and data modification cycles for the modification of the stored image and an address signal for the said screen for reading and writing image data words and a data switch connected to the said screen memory in order to ensure a modification of the stored image at the address defined by the address signal in the course of each data modification cycle, characterized in that the said data switch comprises ;

- a generator (12) for the data image fictive word, termed the transposition word, whose respective bits are of the same value,

- a plurality of data correction devices (3A - 3D) each connected on the one hand with one of the memory planes (3A - 3D) for which it is intended, in order to receive a read data word from this memory plane and to supply it with a modified data word, and on the other hand with the control microprocessor (1) in order to receive an operational mode command signal,

- and a direction circuit (11) coupling the said transposition word generator (12) with the said command processor (5) and delivering in reply on an output bus (23) connected jointly with the said correcting devices, a word termed the mask word defining positionally, in the data words received by the different correcting devices of the respective memory plane, at least one of the bits to be modified.

2. The graphic visualization controller as claimed in claim 1 characterized in that each of the said correcting devices (13A - 13D) comprises means to perform the logical functions of inversion of a binary value, forcing the value to change to 0, forcing it to change to 1, in respect of each of the bits of the read data word which it receives from the memory plane for which it is intended.

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