EP0146594B1 - Verfahren und vorrichtung zum erzeugen von vektorattributen - Google Patents

Verfahren und vorrichtung zum erzeugen von vektorattributen Download PDF

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Publication number
EP0146594B1
EP0146594B1 EP19840902290 EP84902290A EP0146594B1 EP 0146594 B1 EP0146594 B1 EP 0146594B1 EP 19840902290 EP19840902290 EP 19840902290 EP 84902290 A EP84902290 A EP 84902290A EP 0146594 B1 EP0146594 B1 EP 0146594B1
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European Patent Office
Prior art keywords
address
refresh memory
attribute
vector
starting address
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Expired
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EP19840902290
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English (en)
French (fr)
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EP0146594A4 (de
EP0146594A1 (de
Inventor
David M. Smith
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RAMTEK CORP
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RAMTEK CORP
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Priority to AT84902290T priority Critical patent/ATE57439T1/de
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Publication of EP0146594A4 publication Critical patent/EP0146594A4/de
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/22—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of characters or indicia using display control signals derived from coded signals representing the characters or indicia, e.g. with a character-code memory
    • G09G5/30—Control of display attribute

Definitions

  • the present invention relates, generally, to computer data graphics systems and, more particularly, to a method and apparatus for generating patterned vector attribute data in conjunction with the creation of a vector in the refresh memory for the graphic system visual display device.
  • a cathode ray tube monitor provides the user with a visual image that is generated from data stored in a refresh memory.
  • the refresh memory contains data which defines the attributes of each pixel of the cathode ray display.
  • the user generates a visual image on the cathode ray tube by writing attribute data into the refresh memory.
  • the refresh memory is typically erased and loaded entirely with a background intensity level. When a new picture is created, a foreground intensity replaces the background intensity, along the image being created.
  • the structure for implementing such an operation involved the use of a first register loaded with the background level, and a second register loaded with the foreground level. These registers would then supply these levels to a two-to-one multiplexer. The output of the two-to-one multiplexer would be supplied to the refresh memory data input line. In the two-to-one multiplexer, the outputs thereof would be selected between the foreground and the background by an appropriate control signal.
  • a vector generator generated the addressing to the refresh memory for the point in the refresh memory at which the image was being created.
  • the refresh memory was split up into an attribute memory, and an information memory.
  • a refresh memory supplies image data to a visual display device for display, and wherein the contents of the refresh memory are written therein according to addresses supplied by a vector address generator and to attributes supplied by the present invention in accordance with an attribute format instruction.
  • the present invention includes a memory means for storing data corresponding to a plurality of different attributes at selected addresses.
  • the plurality of attributes can include different levels of intensity, color and the like.
  • means for addressing the attribute storage means in response to the attribute format instruction and in conjunction with the addresses supplied from the vector address generator.
  • the addressing means execute the attribute format instructions to generate a set of addresses which cause the memory means to provide the appropriate attribute data to the refresh memory in concert with the addressing to the refresh supplied thereto by the vector address generator means. This greatly reduces the amount of time that the microprocessor must spend in the generation of the screen image.
  • the addressing means includes scaler counter means, address counter means and length counter means.
  • the attribute format instructions include a scaler parameter, a length parameter, and a starting address.
  • the scaler counter means receives a control signal from the vector generator which is generated in conjunction with the addressing of the refresh memory. An increment count pulse is output after the number of pulses specified by the scaler parameter have been received from the vector address generator control signal. In response to the count pulse from the scaler counter means, the address counter increments the starting address by one count.
  • the length counter means is also responsive to the count pulse, counting the number of count pulses provided by the scaler counter means and, thereafter, outputting a load pulse to the address counter means after a number of counts, specified by the length parameter, have been received from the scaler counter means.
  • the address counter means receives the load signal from the length counter means, it reloads the original starting address and begins incrementing that starting address anew.
  • a display device 10 such as a cathode ray tube, receives display data from a refresh memory 12.
  • Display device 10 supplies appropriate addressing signals on display control line 14 to cause the contents of refresh memory 12 to be read out over display data line 16 on a periodic basis.
  • refresh memory 12 During the vertical retrace cycle, or a similar cycle which has been designated for display modification, the contents of refresh memory 12 are modified. This modification is typically conducted on a pixel-by-pixel basis. The location of each pixel to be modified is provided by addresses on line 18. These addresses are provided by vector address generator 20. Vector address generator 20 also provides a write enable signal to the refresh memory 12.
  • the actual data which describes the attribute for the particular pixel being modified is supplied to refresh memory 12 on line 22.
  • the attribute data is supplied on line 22 from attribute random access memory (RAM) 24.
  • RAM attribute random access memory
  • Attribute RAM 24 is addressed by addressing circuitry 26.
  • the contents of attribute RAM 24 are supplied by central processing unit 28 via data line 30 and control line 32.
  • Central processing unit (CPU) 28 also supplies attribute format instructions to addressing circuitry 26 on data line 30, along with control signals on lines 34.
  • CPU 28 also communicates with vector address generator 20.
  • vector address generator 20 supplies control signals to addressing circuitry 26 via line 37.
  • vector address generator 20 the function of this device is to provide addressing on a pixel-by-pixel basis of the location of the image in the refresh memory, in response to signals received from the central processing unit 28, or some interface unit (not shown). In turn, the signals from the interface unit or the central processing unit 28, are derived from input signals from the user. These signals take the form of location, direction and length information.
  • Vector address generator 20 converts these signals into specific pixel addresses. When these pixel addresses are supplied to refresh memory 12, along with attribute information on line 22, an image is created within refresh memory 12.
  • Vector address generation is well known in the graphics display area. Methods and structures for implementing such a function are described in numerous texts.
  • Addressing circuitry 26 includes a presettable address counter 36, which is supplied with a starting address by address register 38.
  • the presettable address counter 36 increments the starting address according to a clock supplied on line 40 from presettable scaler counter 42.
  • Scaler counter 42 is supplied with the control signal on line 37 from vector address generator 20.
  • Scaler counter 42 counts the number of pulses present on line 37 and outputs a clock pulse on line 40 after a predetermined number of pulses have appeared on line 37. This predetermined number is specified by the contents of scaler register 44.
  • Presettable length counter 46 receives length data from length register 48 and issues a load pulse to address counter 36 after a predetermined number of clock pulses, as specified by the length data, have been detected on line 40.
  • length register 48, starting address register 38, and scaler register 44 receive data and control signals from central processing unit 28 on lines 30 and 34, respectively.
  • This data can be viewed as an instruction from central processing unit 28, which instruction is executed by addressing circuitry 26 without the need for further participation by central processing unit 28 during the execution of the instruction.
  • Attribute RAM 24 can be viewed as a look-up table, the contents of which can be modified by central processing unit 28 via lines 30 and 32. Attribute RAM 24 preferably contains selected addressesforall of the vector attribute information required for the images sought to be generated. This attribute information would include data such as background intensity, color, and the like, data on the various degrees of intensity which are to be used in the display, data on the various colors which are to be used in the display, and other similar information. As mentioned above, this information is stored at selected addresses so that the instructions supplied by the central processing unit 28 to the addressing circuitry 26, will cause the addressing circuitry 26 to address the attribute RAM 24 to select the appropriate attributes required for the vector being written into refresh memory 12 and for the image being generated.
  • the resulting attribute data supplied to refresh memory 12 from attribute RAM 24 can be viewed as an attribute format which is being written into refresh memory 12 at the locations specified by the addressing from vector address generator 20.
  • the structure of the present invention as illustrated in Fig. 1 provides a high degree of flexibility in the generation of different attribute formats.
  • the scaling data supplied to the scaler counter 42 determines for how many pixels the attribute currently being addressed in the attribute RAM 24 will continue to be supplied to refresh memory 12. Thus, if the scaling data represents a large number, the attribute being currently addressed will be supplied for a large number of pixels. Conversely, if the scaling data represents a small number, then the attribute data will change frequently.
  • the starting addresses supplied to address counter 36 from starting address register 38 specify at what point in the range of possible attributes the attribute actually being generated will be located. Similarly, where an attribute is being varied between a background level and some other level, the starting address will then be typically specified so that the background level is stored in the attribute RAM 24 at a location adjacent to the location of the other attribute level.
  • the length data determines the number of address counter iterations which will be permitted to occur before the address counter is reset to the starting address.
  • length counter 46 provides a cyclical control or a segment control of the attribute format being generated.
  • Fig. 2 illustrates the generation of a dashed-line attribute format in which the image varies between five pixels of background level and five pixels of intensity M, for example.
  • the background level intensity attribute is located at address N in attribute RAM 24, while the intensity level M is located at address N+1 in attribute RAM 24, for example.
  • the central processing unit 28 supplies a starting address of N, a scaler count of 5, and a length count of 2.
  • the first line of Fig. 2 illustrates the signal on vector generator control signal line 37, while the second line of the figure illustrates the addresses being supplied to refresh memory 12.
  • Line 3 illustrates the output of scaler counter 42, while line 4 illustrates the output of address counter 36.
  • Line 5 illustrates the output of length counter 46.
  • line 6 illustrates the attribute which is output from attribute RAM 24.
  • scaler counter 42 After the second set of five pulses has occurred, scaler counter 42 provides a second clock pulse. In response thereto, length counter 46 provides an output pulse which causes address counter 36 to reload the starting address from starting address register 38. Thus, the output of address counter 36 at this point is N. This pattern continues so long as pulses are provided on vector control line 37, or until central processing unit 28 provides the next instruction to the addressing circuitry 26.
  • FIG. 3 an attribute format wherein the intensity level is permitted to increase every two pixels for a total of 128 pixels is illustrated.
  • the first line of Fig. 3 depicts the signals on vector generator control line 37.
  • the second line illustrates the scaler counter 42 output.
  • the third and fourth lines illustrate the length counter output and the address counter output, respectively.
  • the fifth line illustrates the graphical equivalent of the attribute information being supplied from attribute RAM 24.
  • the scaler counter 42 is loaded with the number 2
  • the length counter is loaded with length 64
  • the starting address counter is loaded with address M.
  • scaler counter 42 provides a pulse for every two pulses on the vector generator control line 37.
  • address counter increments its output by 1, starting with starting address M.
  • address counter 42 After the scaler counter 42 has output 64 pulses, corresponding to 128 pixels being addressed by vector generator 20, length counter 46 outputs a load pulse to address counter 36, thereby causing the original starting address M to be loaded into address counter 36.
  • a stair step-like attribute is created by this format.
  • parameter RAM 24 can be a 256 x 4 RAM comprising four 256 x 1 random access memories which are addressed in parallel.
  • Commercially available parts such as industry number 10422, manufactured by Motorola, Inc. of Phoenix, Arizona are suitable for use in such an application.
  • the counter functional blocks 46, 36 and 42 can be industry part number 10136, manufactured by Motorola, Inc. of Phoenix, Arizona.
  • registers 48, 38 and 44 can be commercial part number 74LS374, manufactured by Signetics Corporation of Sunnyvale, CA.
  • a storage means which stores a plurality of different attribute data at selected locations provides attribute data to a refresh memory associated with a visual display device, in conjunction with addresses supplied thereto by a vector address generator. Addressing for the storage means is supplied from an address generator.
  • the method of the present invention comprises the steps of storing a plurality of different attributes at selected addresses in the storage means, providing an attribute format instruction to the addressing means, addressing the storage means in accordance with the attribute format instruction, wherein the addressing step includes the steps of starting the addressing at a specified starting address, incrementing the address whenever a predetermined number of pixel addresses has been supplied to the refresh memory by the vector address generator, wherein the predetermined number is supplied in the attribute format instruction, and restarting the addressing from the starting address when a predetermined number of increment counts has been supplied wherein the predetermined number is provided in the attribute format instruction.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Digital Computer Display Output (AREA)

Claims (14)

1. Vorrichtung zum Einschreiben von Mustervektoren mit einem vorgegebenen Attributformat in einen Auffrischspeicher (12) eines graphischen Bildschirmsystems mit einem Bildschirmgerät (10), einem Vektor-Adressengenerator (20) und einer Einrichtung (28) zur Lieferung von Attributformatbefehlen, wobei das Bildschirmgerät (10) ein Bild aus einer Matrix von Bildpunkten liefert und die Attribute jedes einer Stelle im Bild entsprechenden Bildpunktes durch Attributdaten angegeben werden, die an einer entsprechenden Stelle im Auffrischspeicher (12) gespeichert sind, und wobei der Vektor-Adressengenerator (20) auf den Auffrischspeicher (12) an denjenigen Stellen zugreift, in die die Mustervektoren einzuschreiben sind,
mit einer mit dem Auffrischspeicher verbundenen Einrichtung (24) zur Speicherung einer Vielzahl unterschiedlicher Attributdaten und zur Lieferung von Attributdaten an den Auffrischspeicher (12),
einer mit dem Vektor-Adressengenerator (20) und der Speichereinrichtung (24) verbundenen Einrichtung (26), die unter Ansprechen auf die Attributformatbefehle die Speichereinrichtung (24) in Verbindung mit dem Zugreifen des Auffrischspeichers (12) durch den Vektoradressengenerator (20) adressiert, wobei die Adressiereinrichtung (26) Adressen an die Speichereinrichtung (24) liefert, die entsprechend den Attributformatbefehlen gewählt sind, so daß gewählte Attributdaten durch die Speichereinrichtung (24) an den Auffrischspeicher (12) geliefert und in Speicherstellen geschrieben werden, die durch den Vektor-Adressengenerator (20) zugegriffen werden.
2. Vorrichtung nach Anspruch 1, bei der die Speichereinrichtung (24) ein Speicher mit wahlfreiem Zugriff ist.
3. Vorrichtung nach Anspruch 1, bei der die Attributformatbefehle eine Startadresse, einen Längenparameter und einen Skalierfaktor umfassen, wobei die Adressiereinrichtung (26) aufweist:
eine Adressenänderungseinrichtung (36), die unter Ansprechen auf die Startadresse (38) diese in vorbestimmter Weise in Verbindung mit einem Weiterschalt-Taktsignal abändert und an die Speichereinrichtung (24) liefert, und
eine Takteinrichtung (42), die mit dem Vektor-Adressengenerator (20) verbunden ist und unter Ansprechen auf den Skalierfaktor (44) das Weiterschalt-Taktsignal immer dann erzeugt, wenn der Vektor-Adressengenerator (20) eine vorgegebene Anzahl von Zugriffsvorgängen auf den Auffrischspeicher (12) durchgeführt hat, wobei die vorgegebene Anzahl durch den Skalierfaktor (44) definiert ist, so daß die durch die Speichereinrichtung (24) an den Auffrischspeicher (12) gelieferten Attributdaten sich nach der angegebenen Anzahl von Zugriffsvorgängen ändern.
4. Vorrichtung nach Anspruch 3, mit ferner einer Einrichtung (46), die mit der Adressenabänderungseinrichtung (36) verbunden ist und unter Ansprechen auf den Längenparameter (48) und das Weiterschalt-Taktsignal (42) die Adressenabänderungseinrichtung (36) auf die Startadresse (38) immer dann einstellt, wenn eine vorbestimmte Anzahl von Weiterschalt-Taktsignalen aufgetreten ist, wobei die vorbestimmte Anzahl durch den Längenparameter angegeben wird.
5. Vorrichtung nach Anspruch 3, bei der die Adressenabänderungseinrichtung (36) eine Folge von Adressen erzeugt, die ausgehend von der Startadresse (38) mit jedem von der Takteinrichtung (42) empfangenen Weiterschalt-Taktsignal weitergeschaltet wird.
6. Vorrichtung nach Anspruch 4, bei der das Weiterschalt-Taktsignal eine Impulsfolge ist und die Adressenabänderungseinrichtung (36) einen ersten voreinstellbaren Zähler umfaßt, der mit der Startadresse (38) voreingestellt wird und bei Empfang des Weiterschalt-Taktsignals von der Startadresse (38) ausgehend weiterzählt.
7. Vorrichtung nach Anspruch 6, bei der die Adressenabänderungseinrichtung (36) ferner ein Startadressenregister (38) umfaßt, das unter Ansprechen auf die Startadresse diese an den ersten voreinstellbaren Zähler (36) liefert.
8. Vorrichtung nach Anspruch 4, bei der die Takteinrichtung einen zweiten voreinstellbaren Zähler (42) umfaßt, der mit dem Skalierfaktor (44) voreingestellt wird und seinen Zählwert immer dann zurückzählt, wenn der Vektoradressengenerator (20) auf den Auffrischspeicher (12) zugreift, wobei der zweite voreinstellbare Zähler (42) das Weiterschalt-Taktsignal immer dann ausgibt, wenn sein Zählwert Null erreicht.
9. Vorrichtung nach Anspruch 8 mit ferner einem Skalierregister (44), das unter Ansprechen auf den Skalierfaktor diesen an den zweiten voreinstellbaren Zähler (42) liefert.
10. Vorrichtung nach Anspruch 4, bei der das Weiterschalt-Taktsignal eine Impulsfolge ist und die Einstelleinrichtung einen dritten voreinstellbaren Zähler (46) umfaßt, der auf den Längenparameter voreingestellt wird und seinen Zählwert mit jedem empfangenen Weiterschalt-Taktsignal zurückzählt, wodurch der dritte einstellbare Zähler (46) die Adressenabänderungseinrichtung (36) einstellt, wenn sein Zählwert Null erreicht.
11. Vorrichtung nach Anspruch 10 mit ferner einem Längenregister (48), das unter Ansprechen auf den Längenparameter diesen an den dritten voreinstellbaren Zähler (46) liefert.
12. Verfahren zum Einschreiben von Mustervektoren mit einem vorgegebenen Attributformat in einen Auffrischspeicher (12) eines graphischen Bildschirmsystems mit einem Bildschirmgerät (10), einem Vektor-Adressengenerator (20) und einer Einrichtung (28) zur Lieferung von Attributformatbefehlen, wobei das Bildschirmgerät (10) ein Bild aus einer Matrix von Bildpunkten liefert und die Attribute jedes Bildpunktes entsprechend einer Stelle im Bild durch Attributdaten angegeben werden, die an einer entsprechenden Stelle im Auffrischspeicher (12) gespeichert sind, und wobei der Vektor-Adressengenerator (20) auf den Auffrischspeicher (12) an Stellen zugreift, in die der Mustervektor einzuschreiben ist, mit den Verfahrensschritten :
a. Speichern einer Vielzahl unterschiedlicher Attributdaten an gewählten Adressen in einer Speichereinrichtung (24),
b. Adressieren der Speichereinrichtung (24) entsprechend den Attributformatbefehlen und in Verbindung mit dem Zugreifen durch den Vektor-Adressengenerator (20) auf den Auffrischspeicher (12), so daß gewählte Attributdaten von der Speichereinrichtung (24) ausgegeben werden, und
c. Liefern der gewählten Attributdaten an den Auffrischspeicher (12) in Verbindung mit dem Zugreifen durch den Vektor-Adressengenerator (20) auf den Auffrischspeicher (12).
13. Verfahren nach Anspruch 12, bei dem die Attributformatbefehle eine Startadresse (38), einen Skalierparameter (44) und einen Längenparameter (48) umfassen und wobei der Schritt "b" die folgenden Schritte umfaßt:
i) Zählen (42), wie oft der Vektor-Adressengenerator (20) auf den Auffrischspeicher (12) zugreift,
ii) Ausgeben eines Weiterschalt-Taktsignals immer dann, wenn der Zählwert des Schrittes i) dem Skalierparameter entspricht,
iii) Weiterschalten der Startadresse um eine Speicherstelle bei jedem Auftreten des Weiterschalt-Taktsignals gemäß Schritt ii),
iv) Zählen (46) der Anzahl von Weiterschalt-Taktsignalen, die beim Schritt ii) ausgegeben werden,
v) Wiederholen der Schritte i) bis iv), bis der Zählwert beim Schritt iv) dem Längenparameter (48) entspricht, und
vi) Einleiten des Schrittes iii) derart, daß er mit der Startadresse (48) beginnt.
EP19840902290 1983-05-25 1984-05-23 Verfahren und vorrichtung zum erzeugen von vektorattributen Expired EP0146594B1 (de)

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AT84902290T ATE57439T1 (de) 1983-05-25 1984-05-23 Verfahren und vorrichtung zum erzeugen von vektorattributen.

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US49802583A 1983-05-25 1983-05-25
US498025 1983-05-25

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EP0146594A4 EP0146594A4 (de) 1987-07-23
EP0146594B1 true EP0146594B1 (de) 1990-10-10

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JP (1) JPS60501575A (de)
AU (1) AU2966984A (de)
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US4837563A (en) * 1987-02-12 1989-06-06 International Business Machine Corporation Graphics display system function circuit
NL194254C (nl) * 1992-02-18 2001-10-02 Evert Hans Van De Waal Jr Inrichting voor het converteren en/of integreren van beeldsignalen.
EP0676721A3 (de) * 1994-04-06 1996-04-03 Hewlett Packard Co System zur Darstellung stilisierter Vektoren.

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JPS5297632A (en) * 1976-02-12 1977-08-16 Hitachi Ltd Display unit
US4225861A (en) * 1978-12-18 1980-09-30 International Business Machines Corporation Method and means for texture display in raster scanned color graphic
JPS56111884A (en) * 1980-02-08 1981-09-03 Hitachi Ltd Refreshing system for display picture
US4342991A (en) * 1980-03-10 1982-08-03 Multisonics, Inc. Partial scrolling video generator
US4366476A (en) * 1980-07-03 1982-12-28 General Electric Company Raster display generating system
EP0062669B1 (de) * 1980-10-27 1988-05-25 Digital Equipment Corporation Grafik- und text-bildgenerator für eine rasterabtastanzeige
US4368466A (en) * 1980-11-20 1983-01-11 International Business Machines Corporation Display refresh memory with variable line start addressing

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JPS60501575A (ja) 1985-09-19
WO1984004832A1 (en) 1984-12-06
DE3483390D1 (de) 1990-11-15
AU2966984A (en) 1984-12-18
EP0146594A4 (de) 1987-07-23
EP0146594A1 (de) 1985-07-03

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