Classifications

• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
  • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
  • G09G5/39—Control of the bit-mapped memory
  • G09G5/393—Arrangements for updating the contents of the bit-mapped memory
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
  • G09G5/22—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of characters or indicia using display control signals derived from coded signals representing the characters or indicia, e.g. with a character-code memory
  • G09G5/30—Control of display attribute

Definitions

• the present invention relates, generally, to computer data graphics systems and, more particularly, to a method and apparatus for generating patterned vector attribute data in conjunction with the creation of a vector in the refresh memory for the graphic system visual display device.
• a cathode ray tube monitor provides the user with a visual image that is generated from data stored in a refresh memory.
• the refresh memory contains data which defines the attributes of each pixel of the cathode ray display.
• the user generates a visual image on the cathode ray tube by writing attribute data into the refresh memory.
• the refresh memory is typically erased and loaded entirely with a background intensity level. When a new picture is created, a foreground intensity replaces the background intensity, along the image being created.
• SHEET would be supplied to the refresh memory data input line. In the two-to-one multiplexer, the outputs thereof would be selected between the foreground and the background by an appropriate control signal.
• a vector generator generated the addressing to the refresh memory for the point in the refresh memory at which the image was being created.
• a refresh memory supplies image data to a visual display device for display, and wherein the contents of the refresh memory are written therein according to addresses supplied by a vector address generator and to attributes supplied by the present invention in accordance with an attribute format instruction.
• the present invention includes a memory means for storing data corresponding to a plurality of different attributes at selected addresses.
• the plurality of attributes can include different levels of intensity, color and the like.
• means for addressing the attribute storage means in response to the attribute format instruction and in conjunction with the addresses supplied from the vector address generator. With such a structure, the addressing means execute the attribute format instructions to generate a set of addresses which cause the memory means to provide the appropriate attribute data to the refresh memory in concert with the addressing to the refresh
• the addressing means includes sealer counter means, address counter means and length counter means.
• the attribute format instructions include a sealer parameter, a length parameter, and a starting address.
• the sealer counter means receives a control signal from the vector generator which is generated in conjunction with the addressing of the refresh memory. An increment count pulse is output after the number of pulses specified by the sealer parameter have been received from the vector address generator control signal. In response to the count pulse from the sealer counter means, the address counter increments the starting address by one count.
• the length counter means is also responsive to the count pulse, counting the number of count pulses , provided by the sealer counter means and, thereafter, outputting a load pulse to the address counter means after a number of counts, specified by the length parameter, have been received from the sealer counter means.
• the address counter means receives the load signal from the length counter means, it reloads the original starting address and begins incrementing that starting address anew.
• Fig. 1 is a functional block diagram of the present invention.
• Fig. 2 illustrates the generation of attributes in accordance with the present invention for a dashed-line image.
• Fig. 3 illustrates the generation of vector attributes in accordance with the present invention for a vector in which the intensity increases every two pixels for a predetermined number of pixels, and is then reset to begin anew.
• a display device 10 such as a cathode ray tube, receives display data from a refresh memory 12.
• Display device 10 supplies appropriate addressing signals on display control line 14 to cause the contents of refresh memory
• SUBSTITUTE SHEET 12 to be read out over display data line 16 on a periodic basis.
• refresh memory 12 During the vertical retrace cycle, or a similar cycle which has been designated for display modification, the contents of refresh memory 12 are odrfied. This modification is typically conducted on a pixel-by-pixel basis. The location of each pixel to_ be modified is provided by addresses on line 18. These addresses are provided by vector address generator 20. Vector address generator 20 also provides a write enable signal to the refresh memory 12.
• the actual data which describes the attribute for the particular pixel being modified is supplied to refresh memory 12 on line 22.
• the attribute data is supplied on line 22 from attribute random access memory (RAM) 24.
• RAM attribute random access memory
• Attribute RAM 24 is addressed by addressing circuitry 26.
• the contents of attribute RAM 24 are supplied by central processing unit 28 via data line 30 and control line 32.
• Central processing unit (CPU) 28 also supplies attribute format instructions to addressing circuitry 26 on data line 30, along with control signals on lines 34.
• CPU 28 also communicates with vector address generator 20.
• vector address generator 20 supplies control signals to addressing circuitry 26 via line 36.
• the function of this device is to provide addressing on a pixel-by-pixel basis of the location of the image in the refresh memory, in response to signals received from the central processing unit 28, or some interface unit (not shown).
• the signals from the interface unit or the central processing unit 28 are derived from input signals from the user. These signals take the form of location, direction and length
• Vector address generator 20 converts these signals into specific pixel addresses. When these pixel addresses are supplied to refresh memory 12, along with attribute information on line 22, an image is created within refresh memory 12.
• Vector address generation is well known in the graphics display are. Methods and structures for implementing such a function are described in numerous texts.
• Addressing circuitry 26 includes a presettable address counter 36, which is supplied with a starting address by address register 38.
• the presettable address counter 36 increments the starting address according to a clock supplied on line 40 from presettable sealer counter 42.
• Sealer counter 42 is supplied with the control signal on line 37 from vector address generator 20. Sealer counter 42 counts the number of pulses present on line 37 and outputs a clock pulse on line 40 after a predetermined number of pulses have appeared on line 37. This predetermined number is specified by the contents of sealer register 44.
• Presettable length counter 46 receives length data from length register 48 and issues a load pulse to address counter 36 after a predetermined number of clock pulses, as specified by the length data, have been detected on line 40.
• length register 48, starting address register 38, and sealer register 44 receive data and control signals from central processing unit 28 on lines 30 and 34, respectively.
• This data can be viewed as an instruction from central processing unit 28, which instruction is executed by addressing circuitry 26 without the need for further participation by central processing unit 28 during the execution of the instruction.
• Attribute RAM 24 can be viewed as a look-up table, the contents of which can be modified by central processing unit 28 via lines 30 and 32. Attribute RAM 24 preferably contains selected addresses for all of the vector attribute information required for the images sought to be generated. This attribute information would include data such as background intensity, color, and the like, data on the various degrees of intensity which are to be used in the display, data on the various colors which are to be used in the display, and other similar information. As mentioned above, this information is stored at selected addresses so that the instructions supplied by the central processing unit 28 to the addressing circuitry 26, will cause the addressing circuitry 26 to address the attribute RAM 24 to select the appropriate attributes required for the vector being written into refresh memory 12 and for the image being generated. For a given attribute format instruction from central processing unit 28, the resulting attribute data supplied to refresh memory 12 from attribute RAM 24 can be viewed as an attribute format which is being written into refresh memory 12 at the locations specified by the addressing from vector address generator 20.
• the structure of the present invention as illustrated in Fig. 1 provides a high degree of flexibility in the generation of different attribute formats.
• the scaling data supplied to the sealer counter 42 determines for how many pixels the attribute currently being addressed in the attribute RAM 24 will continue to be supplied to refresh memory 12. Thus, if the scaling data represents a large number, the attribute being currently addressed will be supplied
• the starting addresses supplied to address counter 36 from starting address register 38 specify at what point in the range of possible attributes the attribute actually being generated will be located. Similarly, where an attribute is being varied between a background level and some other level, the starting address will then be typically specified so that the background level is stored in the attribute RAM 24 at a location adjacent to the location of the other attribute level.
• the length data determines the number of address counter iterations which will be permitted to occur before the address counter is reset to the starting address.
• length counter 46 provides a cyclical control or a segment control of the attribute format being generated.
• CMPI Fig. 2 illustrates the generation of a dashed-line attribute format in which the image varies between five pixels of background level and five pixels of intensity M, for example.
• the background level intensity attribute is located at address N in attribute RAM 24, while the intensity level M is located at address N+l in attribute RAM 24, for example.
• the central processing unit 28 supplies a starting address of N, a sealer count of 5, and a length count of 2.
• the first line of Fig. 2 illustrates the signal on vector generator control signal line 37, while the second line of the figure illustrates the addresses being supplied to refresh memory 12.
• Line 3 illustrates the output of sealer counter 42, while line 4 illustrates the output of address counter 36.
• Line 5 illustrates the output of length counter 46.
• line 6 illustrates the attribute which is output from attribute RAM 24.
• the address being supplied to parameter RAM 24 is N. This results in a attribute RAM 24 output of intensity level M. This intensity level is then stored at refresh memory locations A through A+4.
• sealer counter 42 provides a clock pulse.
• the address from address counter 36 is incremented by one.
• parameter RAM 24 provides the background intensity attribute.
• sealer counter 42 After the second set of five pulses has occurred, sealer counter 42 provides a second clock pulse. In response thereto, length counter 46 provides an output pulse which causes address counter 36 to reload the starting address from starting address register 38.
• SUBSTITUTE SHEET N This pattern continues so long as pulses are provided on vector control line 37, or until central processing unit 28 provides the next instruction to the addressing circuitry 26 .
• Fig. 3 an attribute format wherein the intensity level is permitted to increase every two pixels for a total of 128 pixels is illustrated.
• the first line of Fig. 3 depicts the signals on vector generator control line 37.
• the second line illustrates the sealer counter 42 output.
• the third and fourth lines illustrate the length counter output and the address counter output, respectively.
• the fifth line illustrates the graphical equivalent of the attribute information being supplied from attribute RAM 24.
• sealer counter 42 In order to generate the above-described format, the sealer counter 42 is loaded with the number 2, the length counter is loaded with length 64, and the starting address counter is loaded with address M. As can be seen from Fig. 3, sealer counter 42 provides a pulse for every two pulses on the vector generator control line 37. With each pulse from sealer counter 42, address counter increments its output by 1, starting with starting address M. After the sealer counter 42 has output 64 pulses, corresponding to 128 pixels being addressed by vector generator 20, length counter 46 outputs a load pulse to address counter 36, thereby causing the original starting address M to be loaded into address counter 36. As can be seen from the fifth line of Fig. 3, a stair step-like attribute is created by this format.
• parameter RAM 24 can be a 256 X 4 RAM comprising four 256 X 1 random access memories which are addressed in parallel.
• H parts such as industry number 10422, manufactured by Motorola, Inc. of Phoenix, Arizona are suitable for use in such an application.
• the counter functional blocks 46, 36 and 42 can be industry part number 10136, manufactured by Motorola, Inc. of
• registers 48, 38 and 44 can be commercial part number 74LS374, manufactured by Signetics Corporation of Sunnyvale, CA.
• a storage means which stores a plurality of different attribute data at selected locations provides attribute data to a refresh memory associated with a visual display device, in conjunction with addresses supplied thereto by a vector address generator. Addressing for the storage means is supplied from an address generator.
• the method of the present invention comprises the steps of storing a plurality of different attributes at selected addresses in the storage means, providing an attribute format instruction to the addressing means, addressing the storage means in accordance with the attribute format instruction, wherein the addressing step includes the steps of starting the addressing at a specified starting address, incrementing the address whenever a predetermined number of pixel addresses has been supplied to the refresh memory by the vector address generator, wherein the predetermined number is supplied in the attribute format instruction, and restarting the addressing from the starting address when a predetermined number of increment counts has been supplied wherein the predetermined number is provided in the attribute format instruction.

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• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• General Physics & Mathematics (AREA)
• Theoretical Computer Science (AREA)
• Controls And Circuits For Display Device (AREA)
• Digital Computer Display Output (AREA)

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• 1984
  • 1984-05-23 EP EP19840902290 patent/EP0146594B1/fr not_active Expired
  • 1984-05-23 JP JP50228184A patent/JPS60501575A/ja active Pending
  • 1984-05-23 WO PCT/US1984/000787 patent/WO1984004832A1/fr active IP Right Grant
  • 1984-05-23 AU AU29669/84A patent/AU2966984A/en not_active Abandoned
  • 1984-05-23 DE DE8484902290T patent/DE3483390D1/de not_active Expired - Fee Related

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