EP0138906A4

EP0138906A4 - Redundant memory circuit and method of programming and verifying the circuit.

Info

Publication number: EP0138906A4
Application number: EP19840901265
Authority: EP
Inventors: George W Brown; Phi Thai
Original assignee: Advanced Micro Devices Inc
Current assignee: Advanced Micro Devices Inc
Priority date: 1983-04-18
Filing date: 1984-02-23
Publication date: 1987-07-09
Also published as: JPH0481840B2; EP0138906A1; US4577294A; WO1984004196A1; JPS60501080A

Abstract

A redundant memory circuit having a memory for storing information in a matrix of interconnected rows and columns, and a row and a column address decoder to access the rows and columns. The memory has a redundant row or rows to replace a defective row or rows in the matrix and a programmable decoder which is programmed with the row address of the defective row to access the redundant row. The row and column address decoders are used to access the defective row and to sequentially access the columns so as to entirely disconnect the defective row from the columns. The programmable decoder is then programmed with the defective row address, bit by bit, in response to the column addresses, to access the redundant row. After this procedure, a verification circuit can be used to verify that the redundant row can be accessed and that the programmable decoder is properly programmed to decode only one address to one row.

Description

REDUNDANT MEMORY CIRCUIT AND METHOD OF PROGRAMMING AND VERIFYING THE CIRCUIT

Background of the Invention

Field of the Invention. The present invention relates generally to apparatus for accessing stored information and, more specifically, to a redundant memory circuit and a method of programming the circuit.

Discussion of Background and Prior Art. A wide variety of apparatus exists for accessing stored information. One type of apparatus is known as a redundant memory circuit, which has a memory for storing the information and circuitry for accessing the stored information. The memory, such as a programmable read-only memory (PROM) or a random access memory (RAM) , generally has an array of programmable data bit storage elements arranged in a matrix of interconnected rows and columns. The circuitry used to access the information stored on the memory includes row and column address decoders which receive and decode row and column addresses and, thereby, activate tho corresponding rows nnd columns. In, for example, a PROM, each programmable data bit storage element is a fuse which is programmed or "blown," i.e., opened, to store a data bit of one logic level, e.g., logic 1, or left closed to store a data bit of the other logic level, e.g. logic 0. The redundant memory circuit can be manufactured, for example, as an integrated circuit (IC) oh a semiconductor chip and housed in an IC package.

In the manufacture of the memory, any one or more well-known defects can occur which cause a given bit or bits in a given row to be unusable for storing the information. Consequently, the redundant memory circuit typically is manufactured with the memory having a redundant row to replace the defective row and a programmable row address decoder which is used to access the redundant row in response to the address to the defective row. A general algorithm for making use of the redundant memory circuit involves two basic operations, which are first to deselect the defective row and then secondly to select the redundant row.

U.S. Patent No. 4,250,570 to Tsang et al., issued February 10, 1981, discloses such a redundant memory circuit. Two embodiments are described for deselecting a defective row. One of the two embodiments permanently physically deselects the defective row from its associated row address decoder, while the other embodiment electronically deselects the defective row from its row address decoder whenever the defective row is addressed. Tsang et al. also disclose an embodiment for selecting the redundant row.

In the one embodiment of the patent for physically deselecting a defective row, additional circuitry is provided between each row address decoder and the corresponding row of the memory. This additional circuitry includes a programmable fuse and other components, external of the memory, for coupling the output of the particular row address decoder to the corresponding row. After a defective row in the memory is identified, the corresponding row address decoder is enabled to pass programming current through the fuse and the other components, thereby opening the fuse and physically disconnecting the defective row from its row address decoder.

A problem with the one embodiment for physically deselecting the defective row is the fact that the additional circuitry is required between each row address decoder and the associated row in the memory, which has disadvantages such as the need for increased space on the IC chip to support this circuitry and higher manufacturing costs. Also, in the course of programming the memory to store the data bits, a good or non-defective row can be undesirably deselected. This can occur as a result of the programming current that is developed in the good row to store the bits causing current to flow through and open the external programmable fuse and, thereby, physically disconnect the good row from the corresponding row address decoder. Furthermore, while the defective row is physically disconnected from the corresponding row address decoder, internally of the memory the entire defective row, particularly the unprogrammed or closed data bit storage elements, is not disconnected from all the columns of the memory matrix. This means that the defective row will have parasitic capacitance that is coupled to the columns. Therefore, upon reading a good row, the parasitic capacitance tied to the columns that are also interconnected with the defective row still must be discharged, thereby disadvantageously reducing the speed of the memory access.

In the other embodiment of Tsang et al. for electronically deselecting a defective row, a redundant row address decoder, in particular a NAND gate, responds to the address to the defective row by outputting a signal to access the associated redundant row. In addition, this output signal is coupled through an inverter to disable all the other row address decoders associated with their corresponding rows, one of which is the row address decoder that also receives the address to the defective row. Thus, all the rows including the defective row, but not the redundant row, are electronically deselected when the address to the defective row is received by the redundant row address decoder. One disadvantage with this embodiment is that a delay is introduced in accessing the data stored in the redundant row, thereby reducing memory access speed. This is because a significant amount of time is needed to fully and reliably disable the other row address decoders before access should be made to the redundant row. Furthermore, as with the one embodiment mentioned above, the entire defective row is not disconnected internally from the columns, thereby resulting in the same disadvantage of reduced memory access speed upon reading a good row.

In the embodiment of Tsang et al. for selecting the redundant row, the redundant row address decoder is programmed to decode or respond to the address of the defective row to access the redundant row. An address buffer and associated decoder fuses of the decoder are associated with each bit of the defective row address. Essentially, the programming of the redundant row address decoder occurs bit-by-bit, in which all the address buffers except the address buffer corresponding to the bit currently being programmed are held at a high voltage level. Programming current is then passed through or sunk by the one address buffer to program one of the associated decoder fuses. The remaining decoder fuses associated with the remaining address buffers are programmed in the same manner with all the address buffers except one being held at the high voltage level at any one time during the programming. A disadvantage with the prior programming of the redundant row address decoder is that at any given time all but one of the address buffers must be at a high voltage level. This presents a significant multiplexing problem in that a multiplexer must simultaneously switch very high input voltages to all of the address buffers but the one, and this is difficult to accomplish. This multiplexing of the high input voltages also complicates the method of programming the redundant row address decoder. Furthermore, the programming current for the decoder fuses of the redundant row address decoder is not supplied in a controlled manner. That is, the programming current develops or increases across each decoder fuse until the fuse opens slightly. This has the disadvantage that the fuse may not open sufficiently from a programming point of view so as to provide a wide gap which reliably represents the bit of the row address. Still furthermore, the redundant row address decoder pf the patent uses multiple emitter transistors (METs) whose output is coupled to the redundant row, which METs inherently have a low base to emitter voltage breakdown. Consequently, during the programming phase of the redundant row address decoder, the redundant row can be undesirably subjected to the programming voltages through this emitter-base voltage breakdown phenomenon, the consequence of which is that the programming voltage must be set at a lower limit than is optimum.

Another overall disadvantage of prior redundant memory circuits is that programming pads on the IC chip through which the programming currents are supplied, in addition to the other typical bonding pads, such as those through which the row and column addresses are supplied, are required in order to deselect a defective row and select the redundant row, thereby undesirably increasing the number of components needed for the circuit. Also, the programming of the prior redundant memory circuits typically occurs at a point in the manufacturing process known as the "wafer sort". When performed at this stage, the programming current must pass through long needle-like probes which have an undesirable resistive and inductive effect that limits the programming voltage and induces inductive voltage overshoots and ringing when a decoder fuse opens, thus potentially stressing the chip.

Summary of the Invention.

It is an object of the present invention to provide a novel apparatus for accessing stored information.

It is another object of the present invention to provide a redundant memory circuit having a minimum number of components.

It is still another object of the present invention to prevent the deselection of an otherwise good row of a memory.

Yet another object of pifesent invention is to provide fast access to a memory having a defective row, i.e., no loss of access time when accessing a redundant row.

Another object of the present invention is to reliably and conveniently program the redundant memory circuit to deselect a defective row and select a redundant row.

Still another object of the present invention is to be able to easily program the redundant row address decoder of the redundant memory circuit to decode the address of a defective row of a memory.

Another object of the present invention is to be able to provide relatively high programming voltages and currents for programming the redundant memory circuit.

Additional objects, advantages and novel features of the invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of instrumentalities and combinations particularly pointed out in the appended claims.

Statement of the Invention.

To achieve the foregoing and other objects in accordance with the purpose of the present invention, as embodied and broadly described herein, the apparatus of this invention can comprise a memory having a matrix of a plurality of rows and columns and a redundant row, row address decoder means and column address decoder means for receiving and decoding, respectively, row and column addresses to access the plurality of rows and columns and to deselect a defective row of the plurality of rows, programmable decoder means, coupled to the redundant row, for receiving and decoding any one of the row addresses to select the redundant row and means, coupled to the column address decoder means, for programming the programmable decoder means to decode the row address of the defective row.

Preferably, the entire defective row is disconnected from the plurality of columns. It is also preferred that the programmable decoder means has a plurality of decoder columns having programmable decoder elements which are sequentially accessed to sequentially provide programming current for the decoder elements. Preferably, also, the apparatus includes means for verifying the selection of a redundant row and the proper programming of the programmable decoder means.

In a further aspect of the present invention, in accordance with its objects and purposes, a method is provided of substituting or replacing, in a memory having a selection of the redundant row can be verified by the manufacturer or the user of the package and without requiring any additional IC package pins.

Brief Description of the Drawings. The accompanying drawings, which are incorporated in and form a part of the specification, illustrate an embodiment of the present invention and, together with the description, serve to explain the principles of the invention. In the drawings: Figure 1 is a block diagram of an overall system having the present invention;

Figure 2 is a block diagram of the apparatus of the present invention;

Figure 3 is a schematic illustration of circuit components of the present invention shown in Figure 2;

Figure 4 is a schematic illustration of other circuit components of the present invention of Figure 2; and

Figure 5 shows the relationship of Figure 3 to Figure 4.

Detailed Description of the Invention. Reference will now be made in detail to the present preferred embodiment of the invention, an example of which is illustrated in the accompanying drawings. Figure 1 illustrates a system 10 having an integrated circuit (IC) package 12 which houses programmable apparatus 14 for accessing stored information. The package 12 includes a plurality of pins P for receiving various signals over signal lines shown generally at SL and circuitry shown generally at 16 for producing the various signals on SL. The package 12 and, in particular, the apparatus 14, is programmed in response to the signals on selection of the redundant row can be verified by the manufacturer or the user of the package and without requiring any additional IC package pins.

Figure 2 is a block diagram of the apparatus of the present invention;

Figure 5 shows the relationship of Figure 3 to Figure 4.

Detailed Description of the Invention. Reference will now be made in detail to the present preferred embodiment of the invention, an example of which is illustrated in the accompanying drawings. Figure 1 illustrates a system 10 having an integrated circuit (IC) package 12 which houses programmable apparatus 14 for accessing stored information. The package 12 includes a plurality of pins P for receiving various signals over signal lines shown generally at SL and circuitry shown generally at 16 for producing the various signals on SL. The package 12 and, in particular, the apparatus 14, is programmed in response to the signals on SL and after such programming becomes a separate useful product independent of the circuitry 16.

Specifically, the apparatus 14 is a redundant memory circuit 18 which, among other circuit components 19 to be described, includes a memory 20 for storing information in a matrix 22 of a plurality of rows R and a plurality of columns C interconnected with the rows R. As one example, matrix 22 also has at least one redundant row RR₀ which can be selected in accordance with the present invention to replace a defective row in the plurality of rows R. The memory 20 can be, for example, a programmable read-only memory (PROM) or a random access memory (RAM) or other type of programmable memory. And, while the redundant memory circuit 18 is indicated as being implemented as an integrated circuit (IC) , it will become appreciated that the redundant memory circuit 18 can constitute other types of circuit implementation.

The circuitry 16 includes an address generator 24 for generating addresses A_o...A_y...A_x... over address lines 26 of SL. In particular, address generator 24 generates Y-bit column addresses A_o-A_Y that are coupled from lines 26 and over lines 28 to pins P_o-P_Y and (X-Y)-bit row addresses A_Y+1-A_X that are coupled from lines 26 and over lines 30 to pins P_Y+1-P_X. Bits A_o-A_Y of column addresses A₀-A_Y, which are received at pins P_o-P_Y, respectively, identify the plurality of columns C, respectively, with bit A_Y also being a control bit that is used for example, if memory 20 has more than one redundant row RR_o, as will be further described. Bits A_Y+1-A_χ of row addresses A_Y+1-A_X are coupled over lines 30 to pins P_Y+1-P_χ, respectively, and identify the plurality of rows R, respectively. Thus, for example, if matrix 22 has 32 columns C, then generator 24 produces 5-bit column addresses A₀-A₄ with A₄ also used for control purposes, and if matrix 22 has 128 rows R, then generator 24 produces 7-bit row addresses A₅-A₁₁. A signal generator 32 produces a control signal on a line 34 of SL. For example, a chip select (CS) signal is produced by signal generator 32 on line 34 and is received by a pin P_CS of package 12. A programming voltage supply 36 supplies a programming voltage over a line 38 that is coupled to, for example, pin P₃ (not specifically shown) of package 12. Pin P₃, therefore, is used for purposes of receiving bit A₃ of the column addresses A₀-A₄ and for receiving the programming voltage. As will be further described, CS controls the gating of programming current produced in response to the programming voltage on line 38 to program the redundant memory circuit 18.

Figure 2 shows in more detail the redundant memory circuit 18, including the memory 20 and matrix 22 for storing information. In the present example, the matrix 22 of memory 20 has 32 columns C₀-C₃₁ and 128 rows

R₀-R₁₂₇ which are interconnected by programmable devices PD that constitute data bit storage elements. The matrix 22 also includes at least one redundant row RR₀ extending across the plurality of columns C₀-C₃₁ and having the programmable devices PD to store data that otherwise would be stored at a defective row R₀-R₁₂₇. As also indicated, the memory 20 can be divided into, for example, 2 banks B₁ and B₂. Columns C₀-C₁₅ can extend along bank B₁ and columns C₁₆-C₃₁ can extend along bank B₂. Bit A₄, as will further be described, can be used to activate columns

C₀-C₁₅ of bank B₁, while bit can be used to activate columns C₁₆-C₃₁ of bank B₂.

As will be further described, for any number ofwell-known reasons, the matrix 22 may have one or more defects which make a given row R₀-R₁₂₇ unusable for storing one or more data bits via programmable devices PD. For example, a given defect may prevent row R₅₀ from being used for the storage of the information. Consequently, in accordance with the present invention, the defective row R₅₀ will be deselected and the redundant row RR₀ will be selected to replace the defective row R_50. In particular, the entire row R₅₀ will be disconnected from the plurality of columns C₀-C₃₁ by the programming of the programmable devices PD. The manner of first detecting if a row R₀-R₁₂₇ is defective is well-known and can occur during a procedure known as "array blank checking."

The redundant memory circuit 18 also has column address decoder means 40 for receiving and decoding bits A₀-A₃ of the column addresses A₀-A₄ via pins P₀-P₃ and for receiving and decoding A₄ via pin P₄. The redundant memory circuit 18 also includes row address decoder means 42 for receiving and decoding the row addresses A₅-A₁₁ via pins P₅-P₁₁. In response to A₀-A₃ of the column addresses A₀-A₄, decoder means 40 outputs on lines 44 a plurality of column select signals CS₀-CS₁₅ and, in response to A₄, decoder means 40 outputs A₄ and on lines 46.

A column select circuit (CSC) means 48 selects or activates the plurality of columns C₀-C₃₁ over lines 50 in response to CS₀-CS₁₅ on lines 44, respectively, and in response to A₄ and on lines 46. Branch lines 52 from lines 44 carry CS₀-CS₆ for purposes to be more fully described below.

Row address decoder means 42 responds to the row addresses A₅-A₁₁ by outputting on lines 54 row driver (RD) signals RD₀-RD₁₂₇, respectively, to access or drive on the rows R₀-R₁₂₇. Thus, for example, an entire row R of matrix 22 can be accessed by holding the row address A₅-A₁₁ to that row at decoder means 42 while incrementing or sequencing the column addresses A₀-A₄ to sequentially generate CS₀-CS₁₅ and, thereby, sequentially select all the columns C₀-C₃₁ coupled across the one row R. This row and column addressing algorithm, as will be further described, is used to deselect any defective row R, such as the defective row R₅₀. Redundant memory circuit 18 also includes programmable redundant row address decoder means 56 for accessing redundant row RR₀ via a line 58 carrying a redundant row driver (RRD₀) signal. Decoder means 56 is coupled to row address decoder means 42 via lines 60 for receiving and decoding any one of the row addresses A₅-A₁₁. When programmed, as will be further described, the redundant row address decoder means 56 will decode the row address A₅-A₁₁ to the defective row R, i.e., row R₅₀ in the example, whereby the redundant row RR₀ will be selected.

The redundant memory circuit 18 further has means 62 for programming the programmable redundant row address decoder means 56 to decode the row address A₅-A₁₁ of any defective row R₀-R₁₂₇, such as the defective row R₅₀. In general, programming means 62 responds to CS₀-CS₆ on lines 52 to sequentially program, respectively, via lines 64, the bits of the defective row address A₅-A₁₁ into the decoder means 56. Thus, the number of column select signals on lines 52 is at least equal to the number of bits of the row addresses A₅-A₁₁, so that, in the present example, there are 7 signals CS₀-CS₆ for the 7 bits of the row addresses A₅-A₁₁, respectively.

In particular, and as also shown in Figure 2, the programming voltage on line 38 from supply 36 (see Figure 1) is coupled through pin P₃ and over a line 66 to programming means 62. Also, the chip select signal CS from signal generator 32 (see Figure 1) is coupled through line 34 via pin P_CS and over a line 68 to programming means 62 which also receives A₄/ on lines 46. With the programming voltage being supplied on line 66, and in response to CS on line 68 and A₄/ on lines 46, programming current will be gated from programming means 62 to decoder means 56 via lines 64 to program the bits of the defective row address A₅-A₁₁ in response to CS₀-CS₆ which are generated from A₀-A₂ of the column addresses A₀-A₄. Essentially, therefore, the sequential generation of

CS₀-CS₆ on lines 52 results in programming means 62 providing a multiplexing function by which the programming voltage on line 66 is used to produce sequentially the programming current on lines 64 for programming the bits of the defective row address A₅-A₁₁ into decoder means 56.

Bits A₄ and are used by programming means 62 if the memory 20 is manufactured with redundant row RR₀ and another redundant row RR₁ (see Figure 3) for replacing another defective row R. In this event, programming means 62 will program decoder means 56 to decode another defective row address A₅-A₁₁, and thereby select the other redundant row RR₁.

Another feature of the redundant memory circuit 18 is a means 70 for verifying the selection of a redundant row RR₀ or RR₁ and for verifying the proper programming of the programmable decoder means 56. Means 70 responds to A₄ and on lines 46 to sense, via lines 72, this selection and proper programming. The verification can occur without using additional pins P on package 12 and may be performed by the manufacturer or user of package 12, as will be described more fully below.

In operation, generally, assume that IC package 12 having the redundant memory circuit 18 has been manufactured with one redundant row RR₀. Also, assume that the above-mentioned "array blank checking" procedure has been or is being performed and that row R_{5 0} is identified as being defective.

Then, in accordance with the present invention, the row address A₅-A₁₁ to defective row R₅₀ is supplied to or held via pins P₅-P ₁₁ at row address decoder means 42 which responds by driving on row R₅₀ via one of the lines

54. Then, with this defective row address A₅-A₁₁ being held at decoder means 42, the column addresses A₀-A₄ are sequentially generated and supplied to pins P₀-P₄, whereby CS₀-CS₁₅ are sequentially produced in response to A₀-A₃ to access respectively the plurality of columns C₀-C₃₁ with A₄ and activating bank B₁ and bank B₂, respectively. As will be further described, when each column C₀-C₃₁ is accessed, programming current is supplied through the respective columns C₀-C₃₁ to program or open the associated programmable devices PD coupled to row R₅₀, whereby the entire defective row R₅₀ will be physically disconnected from the plurality of columns C₀-C₃₁. With the defective row R₅₀ now deselected, the redundant row RR₀ is then to be selected. To select the redundant row RR₀, the defective row address A₅-A₁₁ is held at the pins P₅-P₁₁. Then, the column addresses A₀-A₄ are again sequentially supplied to pins P₀-P₄, whereby column address decoder means 40 outputs sequentially CS₀-CS₆ in response to A₀-A₂ on lines 44 and, hence, lines 52. Programming means 62 responds to CS₀-CS₆, to CS on line 68 and to the programming voltage on line 66 by sequentially gating programming current onto lines 64 to programmable redundant row address decoder means 56. Consequently, each bit of the defective row address A₅-A₁₁ for defective row R₅₀ is programmed into decoder means 56. Therefore, with decoder means 56 so programmed, whenever thereafter the defective row address A₅-A₁₁ to defective row R₅₀ is produced, both decoder means 56 and decoder means 42 will respond to drive on defective row R₅₀ and the redundant row RR₀. However, since defective row R₅₀ has been previously disconnected, only redundant row RR₀ is selected.

After deselecting the defective row R₅₀ and selecting the redundant row RR₀, the means 70 can be utilized to perform the above-mentioned verification function, as will be more fully described below.

As shown in more detail in Fig. 3, the column address decoder means 40 includes a column address buffer 74 of individual address buffers AB₀-AB₄ for receiving on input lines 76₀-76₄ respectively, the bits of column addresses A₀-A₄. Each buffer AB₀-AB₄ outputs on lines 78₀, -78₄ the true and complementary logic values of the corresponding bit it receives, so that, for example, buffer AB₀ outputs A₀ and on lines 78₀, respectively. A column address decoder 80 receives the true and complementary outputs of the respective address buffers

AB₀-AB₄ to decode the column addresses A₀-A₄. Thus, decoder 80 outputs any one of CS₀-CS₁₅ on respective lines 44 in response to A₀ - A₃ of a given column address A₀-A₄ on lines 76₀-76₃, and A₄ and on lines 46 in response to A₄ on line 76₄.

The column select circuit means 48 includes respective column select circuits CSC₀-CSC₃₁ for supplying current to the respective columns C₀-C₃₁. Each column select circuit CSC₀-CSC₃₁ includes a programming current source 82 coupled to respective columns C₀-C₃₁, together with a Schottkey diode 84 and a Schottkey diode 86 which are coupled to a common gating line 88 to gate programming current to flow to the respective columns C₀-C₃₁ when diodes 84,86 are biased. As indicated, diodes 84 are biased in response to CS₀-CS₁₅, respectively, while diodes 86 are biased by A₄ or as will be further described. Programming current sources 82 receive a conventional "array programming voltage" on a common line 89.

In the operation of column select circuits CSC₀-CSC₁₅, assume that A₄ is at logic 1 to bias the associated diodes 86. Then, in connection with column select circuit CSC₀ of CSC₀-CSC₁₅, when CS₀ is at logic 1, the associated diode 84 is biased and programming current from source 82 will be gated to flow along column C₀. When CS₀ is at logic 0, current will not be gated to flow to column C₀. A similar operation occurs for column select circuits CSC₁-CSC₁₅ in response to CS₁-CS₁₅, respectively, with A₄ remaining at logic 1. Since CS₀-CS₁₅ are generated sequentially in response to A₀-A₃ of the sequentially generated column addresses A₀-A₄, each column C₀-C₁₅ is sequentially accessed.

Similarly, assume that is at logic 1 to bias the associated diodes 86 of CSC₁₆-CSC₃₁. Then, when CS₀-CS₁₅ are generated, as mentioned above, programming current from sources 82 of CSC₁₆-CSC₃₁ will be gated sequentially to flow along columns C₁₆-C_{3 1}.

Fig. 3 also shows in more detail the memory 20 and, in particular, the matrix 22 having the plurality of rows R₀-R₁₂₇. and the plurality of columns C₀-C₃₁ being interconnected by the programmable devices PD. Also shown is the redundant row RR₀ and another redundant row RR₁, each of which can be used to replace a defective row R₀-R₁₂₇. As is conventional, 1 bit of information is stored at each interconnection or programmable device PD between a given column C₀-C₃₁ and a given row R₀-R₁₂₇. Each programmable device PD includes a programmable element 90, such as a fuse 92, and, for example, a Schottky diode 94. If the fuse 92 is not programmed, i.e., if it remains closed as shown, this constitutes one logic state, e.g., logic 0, and if it is programmed or "blown", i.e., if it is opened, this constitutes the other logic state, i.e., logic 1. As is known, at each interconnection PD, if a fuse 92 is not blown, parasitic capacitance C exists, which must be charged along a given addressed column C₀-C₃₁, which thereby slows the speed at which the stored information can be accessed when the columns C₀-C₃₁ along an addressed row R₀-R₁₂₇ are sequentially addressed. In accordance with the present invention, by disconnecting the entire defective row R₅₀ from the plurality of columns C₀-C₃₁ , the parasitic capacitance C is not present at that row and the memory speed is not reduced when accessing a good row R (shown in Fig. 1). Defective row R₅₀, as shown in Fig. 3, can have one or more of a number of known defects that prevent its use for the storage of information. For example, a fuse 92 interconnecting column C₃₁ and row R₅₀ can be defective, e.g., it can be open as manufactured when it should be closed at this time. Or, for example, row R₅₀ can have an open metal line between column C₈ and column C₉ (not specifically shown) , thereby preventing the bits stored at columns C₉-C₃₁ from being read along row R₅₀. In accordance with the present invention, when row R₅₀ is detected to have any one or more of these defects, it will be entirely disconnected from columns C₀-C₃₁ by opening all associated fuses 92 and will be replaced by, for example, redundant row RR₀. in the operation of Fig. 3 thus far described, assume that using the conventional "array blank checking" that row R₅₀ has been determined to be defective and is presently being addressed by row address decoder means 42 in response to the address A₅-A₁₁ to row R₅₀ (see Fig. 2). Also assume that A₄ on line 76₄ is high and that A₄ on lines 46 is at logic 1, thus biasing diodes 86 associated with CSC₀-CSC₁₅. Then, with column addresses A₀-A₄ being sequentially generated, A₀-A₃ sequentially provide CS₀-CS₁₅. Therefore, diodes 84 of CSC₀-CSC₁₅ are sequentially biased, whereby programming current flows through columns C₀-C₁₅ and programmable devices PD, sequentially, to the addressed row R₅₀ and is sunk by a row driver RD₅₀ (see Fig. 4) . Consequently, the associated fuses 92 between each column C₀-C₁₅ and the defective row R₅₀ are blown.

Next, A₄ at line 76₄ is brought low, thus bringing on line 46 to a logic 1 and biasing diodes 86 of CSC₁₆-CSC₃₁. Then, A₀-A₃ are again sequenced to provide sequentially CS₀-CS₁₅. Therefore, diodes B4 of CSC₁₆-CSC₃₁ are sequentially biased, whereby programming current now flows to C₁₆-C₃₁ and the respective programming devices PD, sequentially to the addressed row R₅₀. Consequently, the associated fuses 92 between the remaining columns C₁₆-C₃₁ and the defective row R₅₀ are disconnected by programming them to an open state.

Now, the entire defective row R₅₀ is disconnected from e plurality of columns C₀-C₃₁. This completes the procedure for deselecting row R₅₀. Any other row R that is detected and determined to be defective can be deselected in a similar manner. Also shown in Fig. 3 are conventional column select circuits CSC'₀-CSC'₃₁ for accessing the columns C₀-C₃₁ to read data that are stored in the memory 20. Column select circuits CSC'₀-CSC'₃₁ have read current sources 82' coupled in common to V_cc via a line 89', diodes

84' which are biased by CS₀-CS₁₅, respectively, and diodes

86' which are biased by A₄ (for CSC'₀-CSC'₁₅) and (for

CSC'₁₆-CSC'₃₁) . Circuits CSC'₀-CSC'₃₁ have junctions

J₀-J₃₁ coupled to columns C₀-C₃₁, respectively, and transistors T₀-T₃₁, respectively. As may be readily seen, when A₄ is at logic 1 and CS₀-CS₁₅ are sequentially produced, read current is sequentially supplied from sources 82' and via junctions J₀-J₁₅ of CSC'₀-CSC'₁₅ to columns C₀-C₁₅ to read data. When is at logic 1 and CS₀-CS₁₅ are sequentially produced, read current is sequentially supplied from sources 82' and via junctions

J₁₆-J₃₁ of CSC ' _{1 6}-CSC ' ₃₁ to columns C_{1 6} -C₃₁ to read data. With reference to Figure 4, the row address decoder means 42 includes a row address buf fer 95 having individual address buffers AB₅-AB _{1 1} for receiving, respectively, on lines 96₅-96_{1 1} the bits of the row addresses A₅-A₁₁. The outputs of each address buffer AB₅-AB ₁₁ are the true and complementary logic values of the inputs so that, for example, address buffer AB₅ outputs A₅ and on respective lines 98₅, Each address buffer AB₅-AB _{1 1} will sink programming current received at one of its outputs to program redundant row address decoder means56 with one or more defective row addresses, as will be further described. A conventional row address decoder 100 of decoder means 42 has address decoder lines ADL₀-ADL₁₂₇ and row drivers RD₀ -RD _{12 7} coupled , respectively , to rows R₀-R ₁₂₇. Decoder lines ADL₀-ADL₁₂₇ have Schottky diodes 106 coupled to pairs of column lines 108₅, 108₁₁, leading to respective lines 98₅, 98₁₁, . Each decoder line ADL₀-ADL₁₂₇ is supplied with decoder current via respective current sources 110₀-110₁₂₇. If, for example, row R₀ were to be addressed, then address A₅-A₁₁ would be 1111111, resulting in only ADL₀ decoding this address to drive on row R₀ via row driver RD₀. In a similar manner, the other lines ADL₀-ADL₁₂₇ uniquely decode the respective row addresses A₅-A₁₁.

The programmable redundant row address decoder means 56, which, as previously mentioned, can be programmed to decode any one of the row addresses A₅-A₁₁, has a redundant row decoder line RRDL₀ and redundant row driver RRD₀ for accessing the redundant row RR₀ , and a plurality of decoder columns (DC₀)₀-(DC₆)₀, respectively, interconnected with RRDL₀. In particular, the plurality of decoder columns (DC₀)₀-(DC₆)₀ includes programming current lines 112₅-112₁₁ ultimately terminating at the true outputs of the address buffers AB ₅-AB₁₁ via lines 108₅-108₁₁ and parallel programming current lines ultimately terminating at the complementary outputs of the address buffers AB₅-AB₁₁ via lines . Each such programming current line has a series-connected Schottky diode 114 and prograimnable element 116, such as a decoder fuse 118. Line RRDL₀ is coupled to each programming line 112₅, ...112₁₁, of the decoder columns (DC₀)₀- (DC₆)₀ via respective diodes 122 which are connected between diode 114 and decoder fuse 118 of each such line.

Similarly, decoder means 56 has a redundant row decoder line RRDL₁ and a redundant row driver RRD₁ for accessing the redundant row RR₁ and a plurality of decoder columns (DC₀)₁- (DC₆)₁ , respectively, interconnected with RRDL₁. The plurality of decoder columns (DC₀)₁- (DC₆)₁ includes programming current lines 120₅-120₁₁ ultimately terminating at the true outputs of address buffers AB₅-AB _{1 1} via junctions 124 and parallel programming current lines ultimately terminating at the complementary outputs of AB₅-AB _{1 1} via junctions 126. Each such programming current line similarly has the series-connected diode 114 and decoder fuse 118, as shown. Line RRDL₁ is similarly coupled to the respective lines of decoder columns (DC₀)₁- (DC₆)₁ via diodes 122.

As will be further described, one of the decoder fuses 118 of each pair of lines 112₅, ...112₁₁, of decoder columns (DC₀)₀- (DC₆)₀ will be programmed or blown in dependence on a defective row address A₅-A₁₁. The result will be that redundant row decoder line RRDL₀ will decode that defective row address to access the redundant row RR₀. Similarly, one of the decoder fuses 118 of each pair of lines 120₅, ...120₁₁ , of decoder columns (DC₀)₁- (DC₆)₁ will be programmed or blown in dependence on another defective row address A₅-A₁₁. The result will be that redundant row decoder line RRDL₁ will decode this other defective row address to access redundant row RR₁.

The programming means 62 preferably includes a plurality of programming circuit sections (PCS₀)₀- (PCS₆)₀ for programming or controlling the flow of programming current to the plurality of decoder columns (DC₀0₁- (DC₆)₀. Another plurality of programming circuit sections (PCS₀)₁- (PCS₆)₁ are used for programming or controlling the flow of programming current to the plurality of decoder columns (DC₀)₁- (DC₆)₁. Means 62 preferably also includes a gating circuit section (GCS) which is common to all the programming circuit sections (PCS₀)₀-(PCS₆)₀, (PCS₀)₁-(PCS₆)₁ and which controls the gating of the programming current by the programming means 62 to the decoder means 56.

Each programming circuit section (PCS₀)₀- (PCS₆)₀ and (PCS₀)₁- (PCS₆)₁ receives the programming voltage on the common line 66 (see Figure 2) when the programming voltage is applied to pin P₃. The programming circuit sections

(PCS₀)₀- (PCS₆)₀ have respective current sources 128 for supplying programming current over lines 130 to the respective decoder columns (DC₀)₀- (DC₆)₀ in response to the programming voltage on line 66 when gated by lines 132. In this aspect of the invention, the programming circuit sections (PCS)₀-(PCS₆)₀ have diodes 134 connected between lines 132 and one of the lines 46 (see Figure 2) carrying A₄. If A₄ is at logic 0, programming current from current sources 128 will be gated off via diodes 134 and lines 132. Therefore, when A₄ is at logic 0, all the programming circuit sections (PSC₀)₀- (PSC₆)₀ will be disabled in that no programming current will be supplied to the respective decoder columns (DC₀)₀- (DC₆)₀. On the other hand, if A₄ is at logic 1, diodes 134 will be biased, whereby programming current sources 128 can be gated on to supply programming current over lines 130 to the decoder columns

(DC₀) ₀- (DC₆) ₀.

Other diodes 136 of (PCS₀)₀-(PCS₆)₀ are coupled between lines 132 and respective lines 52 (see Figure 2) carrying CS₀-CS₆. When CS₀-CS₆, respectively, are at logic 0, programming current from current sources 128 will be gated off by lines 132 and diodes 136 whereby programming current is not supplied to the decoder columns (DC₀)₀-(DC₆)₀. When CS₀-CS₆ are at logic 1, diodes 136 are biased and current sources 128 are thoroby gatod on and can supply the programming current over lines 130 to the decoder columns (DC₀)₀- (DC₆)₀. Since CS₀-CS₆ are sequentially switched to a logic 1 state, as previously mentioned, only one of the current sources 128 at a given time will be gated on and allowed to direct the programming current to the corresponding decoder column (DC₀)₀- (DC₆)₀. This in effect constitutes a multiplexing function of the programming means 62, whereby the programming current from sources 128 are multiplexed or sequentially gated or turned on so that programming current can be supplied to the respective decoder columns (DC₀)₀-(DC₆)₀. During this column sequencing, all the row address buffers AB₅-AB₁₁ are at the normal logic levels required to address the defective row, so that contrary to prior redundant memory circuits, high voltage levels need not be multiplexed to the inputs of AB₅-AB₁₁.

Each programming circuit section (PSC₀)₀- (PSC₆)₀ also has a diode 138 which is coupled between the line 132 and the output of the gating circuit section GCS over a line 140. When line 140 is at logic 0, the programming current from current sources 128 is gated off via lines 132, diodes 138 and line 140, as will be further described. When line 140 is switched logic 1, diodes 138 are biased and the programming current from sources 128 can be gated on to flow over lines 130 to the respective decoder columns

(DC₀)₀-(DC₆)₀.

The programming circuit sections (PCS₀)₁- (PCS₆)₁ for supplying programming current to the decoder columns (DC₀)₁- (DC6)₁ are similar to the programming circuit sections (PCS₀)₀- (PCS₆)₀. Thus, for (PCS₀)₁- (PCS₆)₁, current sources 128 are coupled to the line 66, diodes 136 are coupled, respectively, to the lines 52 (see Fig. 2) carrying CS₀-CS₆ and diodes 138 are coupled to the gating control section GCS. However, the diodes 134 of (PCS₀)₁-(PCS₆)₁ are coupled to the other of the lines 46 carrying . Thus, either diodes 134 of (PCS₀) ₁-(PCS₆)₁ or diodes 134 of (PCS₀)₀-(PCS₆)₀ will be biased for enabling current sources 128 of the former or current sources 128 of the latter to supply programming current to the plurality of decoder columns (DC₀)₁- (DC₆)₁ or the plurality of decoder columns (DC₀)₀- (DC₆)₀.

The gating control section GCS includes a transistor 14 ase is coupled via line 68 to pin P_CS carrying CS (See Figure 2) . The collector of transistor 142 is coupled to a junction 144 and the emitter is coupled to ground over a line 146. A resistor-diode path shown generally at 148 is coupled between the line 66 carrying the programming voltage and junction 144. Another transistor 150 is base biased by the voltage at junction 144 and has its collector coupled to a junction 152 leading to output line 140 and its emitter coupled to ground. A resistor-diode path shown generally at 154 is coupled to junction 152 and the positive supply voltage V_cc. In the operation of GCS, when CS on line 68 is at logic 0, transistor 142 is biased off, whereby current in path 148 produces a biasing voltage at junction 144 to turn on transistor 150. Consequently, current flows from path 154 through junction 152 and transistor 150 to ground, whereby line 140 is at logic 0. When CS is switched to a logic 1, transistor 142 is turned on, and transistor 150 base current flows through path 148, junction 144 and through the collector of turned on transistor 142 to ground via line 146, whereby transistor 150 is turned off. Consequently, junction 152 and line 140 are switched to a logic 1 to bias all the diodes 138.

In operation generally to program decoder means 56 to select redundant row RR₀, assume that, for example, the defective row address A₅-A₁₁ to defective row R₅₀ is inputted to address buffers AB ₅- AB _{1 1}. Depending on the logic 1 or logic 0 state of each of the bits of this defective row address A₅-A₁₁, one of the output lines 98₅, ...98₁₁, of each address buffer AB₅-AB₁₁ will be at logic 0, whereby AB₅-AB₁₁ can sink programming current via those logic 0 lines. Also assume that A₄ is at logic 1 to bias diodes 134 of (PCS₀) ₀- (PCS₆)₀.

Then, a relatively high programming voltage, e.g. 20 volts, is applied via pin P₃ and line 66 to (PCS₀)₀-(PCS₆)₀. Next, the first column address A₀-A₄ is generated, resulting in a logic 1 CS₀ from bits A₀-A₂ to bias diode 136 of (PCS₀)₀ while CS₁-CS₆ are at logic 0. Then, a logic 1 CS is supplied to line 68, resulting in line 140 going to logic 1 and diode 138 being biased. Consequently, programming current from source 128 is now gated onto line 130 to decoder column (DC₀)₀.

As n result, the programming current will flow through line 112₅ or line , depending on the logic state of bit A₅, as previously mentioned, resulting in the associated fuse 118 being blown or opened, and leaving the other fuse 118 closed. Consequently, the diode 122 Coupled to the fuse 118 that is not blown will be in circuit wi the redundant row decoder line KDRL₀. At this point, one bit, i.e., A₅, is programmed into RRDL₀ of decoder means 56. Thereafter, to program bit A₆ of the defective row address A₅-A₁₁, the programming voltage on line 66 is lowered and CS on line 68 is switched to logic 0. Then, the column address A₀-A₄ is incremented, resulting in a logic 1 CS₁, with CS₀, CS₂-CS₆ being at logic 0. Next, the programming voltage is again raised on line 66 and then CS is switched to a logic 1. Consequently, programming current is supplied to (DC₁)₀ (not specifically shown), resulting, in a similar manner as previously described, in one of the decoder fuses (not shown) being blown, with the other decoder fuse remaining closed. Thereafter, a similar procedure occurs for programming, bit-by-bit, the defective row address A₅-A₁₁ held at address buffers AB₅-AB₁₁. This results in redundant row decoder line RRDL₀ being coupled to address buffers AB₅-AB₁₁ in the identical manner that the address decoder line ADL₅₀ for defective row R₅₀ in the present example is coupled to AB₅-AB₁₁. Therefore, whenever this defective row address A₅-A₁₁ is present at AB₅-AB₁₁ it will be decoded by RRDL₀ to select redundant row RR₀ in lieu of defective row R₅₀.

Furthermore, RRDL₁ can be programmed in a similar manner to decode another defective row address to another defective row R ₀-R₄₉, R₅₁-R₁₂₇. To accomplish this, the other defective row address A₅-A₁₁ is held at AB₅-AB₁₁ and is held at logic 1 to activate (PCS₀)₁-(PCS₆)₁.

Consequently, programming current can be sequentially gated to (DC₀)₁-(DC₆)₁ to program RRDL₁.

By performing the gating function mentioned above, the programming voltage on line 66 will be allowed to build up to its full value, e.g. 20 volts, before the programming current is gated on, resulting in a "rush" of programming current when the logic 1 CS is produced on line 68. This rush o.f programming current, therefore, will ensure that the particular decoder fuse 118 will be fully blown open and, thereby, reliably program decoder means 56. In the overall specific operation of the present invention to deselect defective row R₅₀ and select redundant row RR_n, assume that the "array blank checking" is occurring with the row address A₅-A₁₁ to row R₅₀ being inputted to AB₅-AB₁₁. Assume also that using this "array blank checking" procedure, row R₅₀ has been determined to be defective.

Now, with the defective row address A₅-A₁₁ being generated by address generator 24 and being held at AB₅-AB₁₁, address decoder line ADL₅₀ of decoder 95 responds by driving on row R₅₀ via row driver RD₅₀. Then, the column addresses A₀-A₄ are sequentially generated by address generator 24 and received by AB₀-AB₄. Therefore, column address decoder 80 sequentially generates CS₀-CS₁₅, and A₄ and to provide programming current from current sources 82 to columns C₀-C₃₁. Consequently, the fuses 92 coupling columns C₀-C₃₁ to addressed row R₅₀ are sequentially blown, whereby row R₅₀ is entirely disconnected from columns C₀-C₃₁. Next, to select the redundant row RR₀, the defective row address A₅-A₁₁ is continued to be generated by address generator 24 and held at AB₅-AB₁₁. Then, program voltage supply 36 is activated to provide programming voltage via pin P₃ to line 66. Next, address generator 24 is incremented to produce the column address A₀-A₄ at AB₀-AB₄ that results, via A₀-A₂, in the logic 1 CS₀. Then, the control signal generator 32 is enabled to produce CS on line 68 and, thereby, gate programming current to decoder column (DC₀)₀. Thereafter, the supply of the programming voltage is discontinued and CS is switched to logic 0. Then, the programming voltage again is supplied by supply 36 and the column address A₀-A₄ produced by address generator 24 is incremented, whereby a logic 1 CS₁ is produced. Next, a logic 1 CS again is produced by generator 32, so that now programming current is gated to the decoder column (DC₁)₀.

The above procedure continues through to the generation of CS₆ to program the bits of the defective row address A₅-A₁₁ into RRDL₀. Furthermore, as can now be appreciated, a similar operation occurs if another defective row R is detected to deselect that defective row and to select the redundant row RR₁ by programming RRDL₁.

With the IC package 12 now being programmed with at least redundant row RR₀ being selected, the system 10 can be used by the package manufacturer to verify this selection via verification means 70. Alternatively, the IC package 12 can now be sold to a user who can perform the verification using its own address generator 24, as now will be described. With reference again to Figure 3, the verifying means 70 includes a circuit 70A and a circuit 70B. Circuit 70A has a current source 156 for supplying current along aline 158 which is coupled to redundant row RR₀ via aninterconnection 160 and to redundant row RR₁, via an interconnection 162. A diode 164 and a diode 166 are coupled to a line 168, which is connected to a junction 170, and can be biased by A₄ and being at logic 1. A₄ and are both forced to a logic 1 by applying a voltage much higher than a normal logic 1 to the A₄ input buffer AB₄ at line 76₄, e.g. 13 volts. This high voltage overrides the normal function of the buffer AB₄ using a 5V Zener diode circuit (not shown) to force the line to a logic 1 while the A₄ true output 78₄ goes to logic 1 by the normal circuitry used in the A₄ address buffer AB₄. Under this biasing condition, a transistor 172 can be turned on. A sense amplifier 174 is coupled to the emitter of transistor 172 via a junction 176 to sense the on-off state of transistor 172.

Circuit 70B similarly has a current source 156, diode 164, diode 166, line 168, junction 170, transistor 172, and junction 176 coupled to a sense amplifier 174. However, the comparable line 158' of circuit 70B is coupled only to redundant row RR₀ via an interconnection 160.

In operation, and to verify that redundant memory circuit 18 has at least one redundant row RR₀ or RR₁ replacing a defective row R, such as row R₅₀, all the columns C₀-C₃₁ are deactivated by causing CS₀-CS₁₅ to be at logic 0. Then lines 158 and 158' are selected by supplying a high voltage, e.g., 13 volts, to AB₄ via pin P₄, whereby A₄ and A₄ go to logic 1 to bias diodes 164 and 166 of circuit 70A and circuit 70B. If it is assumed that neither redundant row RR₀ nor redundant row RR₁ is being addressed, i.e., line 158 and 158' are now decoupled from rows RR₀ and RR₁ because their respective row drivers RRD₀ and RRD₁ are held off via decoder means 56, then no current will flow from sources 156 of circuit 70A and circuit 70B and biasing voltages are developed at junctions 170 to turn on the respective transistors 172. The respective sense amplifiers 174 will sense the on state of transistors 172. Then, redundant row RR₀ is addressed, as previously indicated, via the programmed decoder means 56. Consequently, line 158 and line 158' are now coupled to redundant row RR₀, whereby current will flow from sources 156 and via interconnection 160 to redundant row RR₀. Consequently, transistors 172 of circuit 70A and circuit

70B will now be turned off, and this will be sensed by the respective sense amplifiers 174, thereby indicating that redundant row RR ₀ is active or selected.

Next, redundant row RR₁ is activated by the programmed decoder means 56. Now, current will flow from source 156, along line 158 and via interconnection 162 to redundant row RR₁ , whereby transistor 172 of circuit 70A remains off. However, with redundant row RR₀ not being addressed, current from source 156 of circuit 70B now cannot flow along line 158', whereby transistor 172 of circuit 70B is biased on. The off state of transistor 172 of circuit 70A and on state of transistor 172 of circuit 70B are sensed by respective sense amplifiers 174, thereby indicating that redundant row RR, is active or selected. While not previously mentioned, it is possible that, for example, redundant row decoder line RRDL₀ of programmable decoder means 56 could be improperly programmed to decode addresses to multiple rows R₀-R₁₂₇, when, in fact, it should only decode one address to one defective row. This could occur if, for example, the two decoder fuses 118 of a given decoder column (DC₀)₀- (DC₆)₀ are inadvertently blown or are otherwise open. As previously indicated, only one of these two decoder fuses should be blown for a given bit of row address A₅-A₁₁. Otherwise, as can be appreciated, if, for example, two separate row addresses have bit A₅ being logic 1 and logic 0, respectively, and if both decoder fuses 118 of decoder columns (DC₀)₀ are open, these bits will be decoded as the same bit, which is incorrect. If the two decoder fuses 118 of any given decoder column (DC₀)₀- (DC₆)₀ or (DC₀)₁- (DC₀)₁ are open, the redundant memory circuit 18 is bad and should be discarded or not used.

To verify if the programmable decoder means 56 has been properly programmed so that, for example, RRDL₀ decodes only one row R₀-R₁₂₇, the following procedure should be performed, bit-by-bit. First, line 58 and redundant row RR₀ are selected, as described above, in response to the defective row address A₅-A₁₁. Then, bit A₅ of row address A₅-A₁₁ at AB₅-AB₁₁ used to select row RR₀ is complemented. If row RR₀ is still selected, as sensed by sense amplifier 174 of circuit 70A and sense amplifier 174 of circuit 70B, this indicates that RRDL₀ is decoding more than one address, which is improper. If, upon complementing bit A₅ of this row address A₅-A₁₁ the row RR₀ is not driven on, then RRDL₀ may be good, depending on bits

A₆-A₁₁.

Therefore, in order to complete this verification, only one bit of address A₅-A₁₁ may be complemented at a time. Thus, after bit A₅ of this row address A₅-A₁₁ is complemented, it must be switched back to its former, uncomplemented state to select row RR₀. Then, bit Ag of this row address A₅-A₁₁ is complemented. Again, if row RR₀ is still selected, this indicates that RRDL₀ is decoding more than one address, which is improper. If, upon complementing bit A₆ of this row address A₅-A₁₁ the row RR₀ is not driven on, then RRDL₀ may be good, depending on the remaining bits A₇-A₁₁. This verification process continues through the remaining bits A₇-A₁₁.

A similar procedure can be used to verify the proper programming of decoder line RRDL₁.

The foregoing description of a preferred embodiment of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The embodiment was chosen and described in order to best explain the principles of the invention and its practical application to thereby enable otherπ πkillod in the art to best utilize the invention in various embodiments and with various modification as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto.

Claims

1. Apparatus for accessing information, comprising: a) a memory for storing the information, said memory having a matrix of a plurality of rows and a plurality of columns and having a redundant row; b) row address decoder means and column address decoder means for receiving and decoding, respectively, row and column addresses to access said plurality of rows and said plurality of columns to store the information in said memory and to deselect a defective row of said plurality of rows, said defective row having a row address; c) programmable decoder means, coupled to said redundant row, for receiving and decoding any one of the row addresses to select said redundant row; and d) means, coupled to said column address decoder means, for programming said programmable decoder means to decode said row address of said defective row.

2. Apparatus, according to claim 1, wherein said row address decoder means and said column address decoder means access said memory to disconnect said defective row from all of said plurality of columns.

3. Apparatus, according to claim 2, wherein said row address decoder means accesses said defective row while said column address decoder means sequentially accesses said plurality of columns to disconnect said defective row from said all of said plurality of columns.

4. Apparatus, according to claim 2, wherein said row address decoder means is non-programmable to prevent disconnecting a non-defective row of said plurality of rows from said plurality of columns.

5. Apparatus, according to claim 1, wherein said column address decoder means and said means for programming have a common pin.

6. Apparatus, according to claim 5, wherein said common pin receives a programming voltage to program said programmable decoder means.

7. Apparatus, according to claim 1, wherein said programmable decoder means comprises: a) a plurality of decoder columns having programmable decoder elements; and b) a decoder line extending across and coupled to said plurality of decoder columns.

8. Apparatus, according to claim 7, wherein said means for programming sequentially accesses each of said plurality of decoder columns to program said programmable decoder elements.

9. Apparatus, according to claim 8, wherein said programmable decoder elements are decoder fuses.

10. Apparatus, according to claim 1, wherein said means for programming comprises means for gating programming current to said programmable decoder means.

11. Apparatus, according to claim 1, further comprising means for verifying the selection of said redundant row.

12. Apparatus, according to claim 1, further comprising means for verifying the programming of said programmable decoder means.

13. Apparatus, according to claim 1, further comprising means for verifying the selection of said redundant row and for verifying the programming of said programmable decoder means.

14. A redundant memory circuit, comprising: a) a programmable memory having a matrix of a plurality of rows and a plurality of columns, and having a redundant row extending across said plurality of columns; b) row address decoder means, coupled to said plurality of rows, for receiving and decoding row addresses to access said plurality of rows; c) column address decoder means, coupled to said plurality of columns, for receiving and decoding column addresses to access said plurality of columns, said row address decoder means accessing a defective row having a row address and said column address decoder means sequentially accessing said plurality of columns to disconnect said defective row from said plurality of columns; d) programmable decoder means, coupled to said row address decoder means and to said redundant row, for receiving and decoding any one of the row addresses to said plurality of rows; and e) means, coupled to said column address decoder means, for programming said programmable decoder means to decode said row address to said defective row.

15. A redundant memory circuit, according to claim 14, wherein said programmable decoder means comprises: a) a plurality of decoder columns each including a first programming current line having a first programmable decoder element and a second programming current line having a second programmable decoder element; and b) a decoder line extending across said plurality of decoder columns and having, for each of said plurality of decoder columns, a first diode connected to said first programming current line and a second diode connected to said second programming current.

16. A redundant memory circuit, according to claim

15, wherein said means for programming comprises means for sequentially coupling programming current to said plurality of decoder columns.

17. A redundant memory circuit, according to claim

16, wherein the programming current is coupled to said first programming current line or said second programming current line in response to the defective row address.

18. A redundant memory circuit, according to claim 16, wherein said means for sequentially coupling comprises means for gating the programming current to said plurality of decoder columns.

19. A redundant memory circuit, according to claim 16, wherein said first programmable decoder element and said second programmable decoder element are decoder fuses.

20. A redundant memory circuit, according to claim 14, further comprising means for verifying the selection of said redundant row and the programming of said programmable decoder means.

21. An integrated circuit, comprising: a) a programmable read-only memory having a matrix of a plurality of rows and a plurality of columns, a first redundant row extending across said plurality of columns and a second redundant row extending across said plurality of columns; b) row address decoder means, coupled to said plurality of rows, for receiving and decoding row addresses; c) column address decoder means, coupled to said plurality of columns, for receiving and decoding column addresses, said row address decoder means accessing at least one defective row and said column address decoder means accessing sequentially said plurality of columns to disconnect said defective row from said plurality of columns; d) programmable redundant row address decoder means, coupled to said first redundant row and said second redundant row, for decoding any one of the row addresses corresponding to said plurality of rows, said programmable redundant row address decoder means including, for said first redundant row and said second redundant row, respectively, i) a first and second plurality of decoder columns coupled to said row address decoder means and each including a first programming current line having a first programmable decoder fuse and a second programming current line having a second programmable decoder fuse; and ii) first and second decoder lines extending across said plurality of first and second decoder columns and having, for each of said first and second plurality of decoder columns, a first diode connected to said first programming current line and a second diode connected to said second programming current line; and e) means, coupled to said column address decoder means, for programming said programmable redundant row address decoder means to decode at least one row address to said one defective row, said programming means including means for sequentially gating programming current to said plurality of decoder columns, respectively, to program said first programmable decoder fuse or said second programmable decoder fuse in response to a row address.

22. An integrated circuit according to claim 21 further comprising means for verifying the selection of the first redundant row and the second redundant row and for verifying the programming of said programmable redundant row address decoder means.

23. A method of substituting, in a memory having a matrix of a plurality of rows and a plurality of columns and a redundant row, a defective row of the plurality of rows with the redundant row, the memory being accessible in response to row addresses and column addresses, comprising: a) disconnecting entirely the defective row from the plurality of columns in response to a row address to the defective row and the column addresses; and b) programming, in response to the defective row address and the column addresses, a programmable means with the defective row address being used to access the redundant row.

24. A method, according to claim 23, wherein the step of disconnecting comprises: a) accessing the defective row in response to the defective row address; b) sequentially accessing the plurality of columns in response to the column addresses; and c) programming the defective row at each sequential accessing of the plurality of columns.

25. A method, according to claim 24, wherein the plurality of rows and the plurality of columns are interconnected by programmable elements, and wherein the step of programming comprises opening the programmable elements interconnecting the defective row and the plurality of columns.

26. A method, according to claim 23, wherein the step of programming a programmable means comprises: a) providing the defective row address to the programmable means, the defective row address having a plurality of bits; b) sequentially accessing the programmable means for each bit of the plurality of bits in response to the column addresses; and c) programming the programmable means at each sequential accessing to decode the defective row address.

27. A method, according to claim 26, wherein the step of programming at each sequential accessing comprises: a) supplying a programming voltage; and b) gating programming current to the programmable means at each sequential accessing in response to the programming voltage.

28. A method, according to claim 23, further comprising verifying the substitution of the defective row with the redundant row.

29. A method, according to claim 23, further comprising verifying the programming of the programmable means.

30. A method of programming a redundant memory circuit having a memory including a matrix of a plurality of rows and columns and one redundant row, one of the plurality of rows being defective, row address decoder means for accessing the plurality of rows in response to row addresses, column address decoder means for accessing the plurality of columns in response to column addresses, and programmable redundant row address decoder means for accessing the redundant row, comprising: a) accessing the defective row with the row address decoder means in response to a defective row address; b) sequentially accessing the plurality of columns with the column address decoder means in response to the column addresses; c) programming the addressed defective row at each sequential accessing of the plurality of columns to disconnect entirely the defective row from the plurality of columns; d) providing the defective row address to the programmable redundant row address decoder means; e) sequentially accessing the programmable redundant row address decoder means in response to the column addresses; and f) programming the programmable redundant row address decoder means at each sequential accessing of the programmable redundant row address decoder means to decode the defective row address.

31. A method, according to claim 30, wherein the plurality of rows and columns are interconnected by programmable fuses, and wherein the step of programming the addressed defective row comprises opening the programmable fuses connected across the plurality of columns and the defective row.

32.. A method, according to claim 30, wherein the row addresses have a plurality of bits and the programmable redundant row address decoder means includes a decoder line and a plurality of decoder columns coupled to the decoder line and associated with the plurality of bits of the row addresses, respectively, and wherein the step of sequentially accessing the programmable redundant row address decoder means comprises sequentially accessing the plurality of decoder columns.

33. A method, according to claim 32, wherein the stop of programming the programmable redundant row address decoder means comprises: a) supplying a programming voltage; and b) gating programming current to the plurality of decoder columns at each sequential accessing of the plurality of decoder columns in response to the programming voltage.

34. A method, according to claim 30, further comprising: a) verifying the substitution of the defective row by the redundant row; and b) verifying the proper programming of the programmable redundant row address decoder means.

35. A redundant memory circuit, comprising: a) a memory having a matrix of a plurality of rows and columns and having a redundant row for storing information, the redundant row replacing a defective row of said plurality of rows; b) row address decoder means and column address decoder means for receiving row and column address to access said plurality of rows and columns to store and read the information; c) programmed decoder means, coupled to said redundant row, for receiving and decoding a row address to said defective row to select said redundant row; and d) means for sensing if said redundant row has replaced said defective row and if said programmed decoder means is responsive to a row address in addition to said row address to said defective row.

36. A redundant memory circuit, according to claim 35, wherein said defective row address has a plurality of bits, wherein said programmed decoder means receives said defective row address and has a plurality of pairs of programmable decoder elements, each of said pairs being associated with one of said bits, and wherein said means for sensing senses if said redundant row is deselected by said programmed decoder means in response to complementing, bit-by-bit, said received defective row address.

37. A method of determining, in a memory having a matrix of a plurality of rows and columns and a redundant row, and having a programmed decoder means for accessing the redundant row, if the programmed decoder means is accessing a row of said plurality of rows in addition to said redundant row, comprising: a) inputting to the programmed decoder means an address to the defective row, the defective row address having a plurality of bits; b) complementing the inputted defective row address, bit-by-bit; and c) sensing if the redundant row is not accessed in response to complementing any bit of the inputted defective row address.