EP0128396A1 - Integrated bus-oriented communication system - Google Patents

Abstract

A monolithically integratable transmission system for binary information has at least one address source which is connected to at least one address sink via an address bus. The address sink is respectively allocated to a register means connected to a data bus. A clock generator generates a first clock signal and a non-overlapping, phase-shifted second clock signal. The address bus and the data bus are precharged during the first clock signal and access of an addressed register means to the data bus occurs during the second clock signal. In the time span between the two clock signals, the address bus is charged with the address signals by discharging.

Description

The invention relates to a monolithically integrable transmission system for binary information, consisting of at least one address source which is connected to at least one address sink via an address bus, and of at least one transmitting / receiving device which is assigned to an address sink and can be activated via a selection line and is connected to a data bus. from a clock generator for generating two phase-shifted, non-overlapping clock signals, a first precharging unit for precharging the data bus being driven in the course of a first clock signal, and a transmitting / receiving device being addressed in the course of a second clock signal.

When building data processing systems, it is known to provide bus-oriented transmission systems which have an address bus and a data bus. A first bus structure is characterized, for example, by a central address bus, which is connected to several decentralized decoders for selecting a transceiver. Another typical system structure has a central address decoder, from which control lines lead in a star shape to a plurality of transmitting / receiving units.

Depending on their length, all signal lines of the transmission system have an undesirable transient response when signals are applied. To ensure that all settling processes are completed when address and data signals are applied, the output and reception of signals requires a strictly synchronous clocking.

A stable signal level can be achieved in a short time by precharging the corresponding signal line at a high level, which can possibly be discharged in a short time according to the signal pattern. In a two-cycle system, the data bus is precharged in a first clock phase, while the address is switched to the address bus. The control signals decoded from this must be stable until the end of the first phase. In the second phase, the data pattern is switched to the precharged data bus, while the address bus remains stable.

In order to increase the switching speed, the shortest possible unloading or charging time of the address bus is sought. The time available for this when changing the address is the same for both processes, although in N-MOS technology a charging process takes longer than physical discharging than a discharging process. To compensate for the time difference, a charging transistor must be of relatively large dimensions. This results in a correspondingly larger space requirement and power consumption, which has an effect particularly in the case of a system structure with multiple address sources. In addition, there is a risk that signals from several transmitters overlap, and that high current peaks occur.

The invention was therefore based on the object of increasing the switching speed in a data transmission system of the type mentioned at the outset and of avoiding the disadvantages of a large space requirement and power consumption.

This object is achieved in accordance with the characterizing part of claim 1.

The invention has the advantage that both control lines or the address bus and the data bus can be precharged in a two-phase clock system. The charging takes place in a time-uncritical phase. It is also ensured that there is no risk of overlap of address signals generated by multiple address sources within the transmission system. The settling behavior of the control line is taken into account by the control loop, so that multiple addressing is excluded.

Further developments of the invention result from the subclaims.

In the following, the invention is further described using two exemplary embodiments.

• 1 schematically shows a first data transmission system
• 2 shows details of the first data transmission system
• FIG. 3 shows the time profile of line levels from FIG. 2
• 4 schematically shows a second data transmission system
• 5 shows details of the second data transmission system
• FIG. 6 shows the time profile of line levels according to FIG. 5.

As described below with reference to FIGS. 1-6, address and data bus 2.12 can be acted upon with address or data signals under strictly synchronous clocking. It is an essential feature of the data transmission system that both the address bus 2 and the data bus 12 are precharged in one of two predetermined clock phases Phi 1 Phi 2.

Precharging is understood to mean that the corresponding line in a defined initial state with a log. Level 1 is applied, and that subsequently to generate a data pattern by discharging a log if necessary. Level 0 is brought about.

The transmission system in FIGS. 1 and 2 is characterized by a central address bus 2 and by decentralized address sinks 3. This structure is used, for example, when there are several address sources 1 on the address bus 2, or when an address source 1 from one or more groups of address sinks 3 is removed. Because of its length, the address bus has a parasitic transit time T1, which is represented schematically by a first RC element 15.

The address sinks 3 each contain a decoder, which emits a selection signal CS to an assigned formatting stage 5 when the corresponding transceiver 6 is addressed. All formatting stages 5, which in the examples shown consist of an AND gate, are on the input side together on a clock line 18 (second clock line) which can be acted upon by a clock signal (second clock signal Phi 2). In this way, a control signal RD / WR is switched on a control line 13 to the associated transceiver 6 with synchronous timing. The control signal is used depending on the application RD / WR to read data from data bus 12 or read data from data bus 12.

As shown in FIG. 2, a first and second precharging device 9, 10 is provided for precharging the data bus 12 and the address bus 2. The charging takes place in a time-controlled manner via a first clock line 17 by means of a first clock signal Phi 1.

The first clock signal Phi1 and the second, phase-shifted clock signal Phi 2, which does not overlap with the first clock signal, are derived by a clock generator 7 from an input clock Ck. The second clock signal Phi 2 is fed to the formatting stages 5 via a second clock line 18.

The address bus 2, which has been precharged to logic level 1 during the duration of the first clock signal Phi 1, is then acted upon by one of the address sources 1 with an address until the start of the second clock signal Phi 2. The corresponding address combination is obtained in that one or more of the address lines AB1 to ABn are possibly discharged by a control signal AD1 to ADn depending on an output signal AS1 to ASn by means of first discharge devices. These discharge devices consist, for example, of MOS-FETs 11, the controlled paths of which are connected to ground potential. A synchronous connection to the address bus 2 takes place via blocking elements 8, which in the example shown consist of NOR elements. Each address source 1 is assigned a blocking stage 8 which is connected on the input side to the address source and to the first clock line 17 and on the output side to the associated MOSFET 11.

Before the control signal RD / WR is switched to the transceiver, all transients, on the address bus and subsequent stages to prevent multiple addressing. The transmission system therefore has a control circuit 20, the output signal of which is led via a control line 26 to a control input of the clock generator 7. The control circuit 20 represents a replica of the address signal path from the output of the address sources 1 to the output of the formatting stages 5.

It consists of a third precharging device 22 and a delay unit, which consists of a second and third RC element 24, 25. The time constant of the second RC element 24 corresponds to the time constant T _{1 of} the first RC element 15 of the address bus 2, and the time constant T _{2 of} the third RC element 25 corresponds at least to the delay time T _{3 of} the address sinks 3.

The first, second and third precharging devices preferably consist of HOS-FETs, the controlled routes of which connect the lines to be precharged with an operating potential.

The delay line 26 and the address bus 2 are precharged for the duration of the first clock signal Phi 1. At the end of the first clock signal Phi 1, the delay line is discharged via a second discharge device 23, which consists of a MOS-FET, the control input of which is connected to the first clock line 17 via an inverter 21. The level change is delayed by the running times T ₁ , T ₂ to the clock generator 7. This control signal CF enables the start of the second clock signal Phi 2 and thus access to the data bus 12. In order to ensure the validity of the address on the address bus 2, the time between the first and second clock phases Phi 1, Phi 2 is thus possibly extended.

The function of the first transmission system is further described below together with FIG. 3.

In Fig. 3 over the time axis t the courses of the first clock signal Phi1, the output signals AS1 to ASn, the control signals AD1 to ADn for the MOS-F ₇ ETs 11, the address bus lines AB1 to ABn, the selection signal CF, the control signal CF, the second clock signal Phi2 and the control signal RD / WR recorded. A level change between one of the logic levels 0 and 1 takes place, if appropriate, at one of the seven successive times t ₁ to t ₇ . The first clock signal Phi1 is effective between times t ₁ to t ₃ with a logic level 1. The second clock signal Phi2 is phase-shifted between the times t ₆ and t ₇ with the logic level 1, whereby a time shift ensures that the two clock signals do not overlap.

At the beginning of the first clock signal Phi1, one of the address sources 1 is controlled by a sequence control, not shown. The output signal AS1 to ASn of the corresponding address source 1 oscillates until time t2 before it reaches a defined level. Depending on this undefined state, the assigned output signals AD1 to ADn of the blocking stage 8 are clearly defined at the latest at time t ₃ , so that a triggering of the MOS-FETs 11 is effective. The discharge of the address bus lines AB1 to ABn, which are precharged to level 1 from t ₁ to t ₃ , only takes effect at time t ₄ because of the parasitic transit time T ₁ . To this first delay time T _{1 is} added a second delay time T ₃ , which depends on the address sink 3.

The second clock phase Phi 2, with which the control signal RD / WR becomes effective at the transceiver 6, may only begin when the assigned control signal has reached a defined state in order to prevent multiple addressing of the transceivers 6. Therefore, in the control loop 20, in addition to the runtime simulation of the address bus 2 by the second RC element 24 takes into account any further settling processes that may occur due to the running time of the third RC element 25. The discharge of the control line 26 is delayed at least until time t ₅ until all transient processes have subsided. The second clock signal Phi 2 is then started at time t ₆ - triggered by the logic level 0 on the control line 26 - via the clock generator 7. Switching on the addressed transceiver 6 on the data bus at the beginning of the second clock phase Phi 2 thus takes place safely after the addresses have been stabilized.

The structure of the second data transmission system is characterized by a central address sink 3 'with an address decoder, from which control lines 4 ^{1 are distributed} to a plurality of transmitting / receiving devices 6. This structure can be used when the transceivers 6 are distributed, for example, in a star shape around the address sink 3 ¹ . In this case, because of their length, the control lines 4 'have an undesirably long transit time, against which the transit time of the relatively short address bus 2' is negligible.

All control lines 4 'are connected to the first precharging device 9'. The delay line of the control circuit 20 is also connected to the first precharging device 9 '. To compensate for the signal propagation times T _{1 of} the control lines 4 ', which depend on the schematically represented fourth RC element 16, the delay line of the control circuit 20 has a fifth RC component 27, by means of which the signal propagation time in the control circuit 20 is at least increased by the delay time T' 1 is delayed.

6 shows the example that a transceiver 6 is selected via a first selection signal CS1. Therefore, the corresponding control line, which, like the other control lines to which the selection signals CS2 to CSn can be applied, is precharged at the logic level 1 for the duration of the first clock signal Phi 1, is not discharged via the associated MOS-FET 11. The control lines with the control signals CS2 to CSn are discharged to the logic level 0 after the delay time T ' ₁ at the time t ₄ . Depending on the total delay time T ' _{2 of} the control circuit 20, the control signal CF assumes the logic level 0 at the time t ₅ . This change causes the start of the second clock signal Phi 2.

Claims (5)

1. Monolithically integrable transmission system for binary information, consisting of at least one address source, which is connected via an address bus to at least one address sink, from at least one, each associated with an address sink, which can be activated via a selection line and is connected to a data bus, from one Clock generator for generating two phase-shifted, non-overlapping clock signals, wherein in the course of a first clock signal a first precharging device is activated for precharging the data bus, and in which a transceiver is addressed in the course of a second clock signal, characterized in that the address bus (2) and / or the selection lines (4, 4 ') are connected to a second precharging device (9) in the course of the first clock signal (Phi 1), and that they are connected in the time between the first and second clock signals (Phi 1, Phi 2) Address or selection signals can be applied. 2. Transmission system according to claim 1, characterized by a blocking circuit (8) at each output of the address sources (1) for blocking an address signal (AS1-ASn) during the duration of the first clock signal (Phi1). 3. Transmission system mach one of claims 1 or 2, characterized by the blocking circuit (8) at the output of the address sinks (3) for blocking a selection signal (CS) during the duration of the first clock signal (Phil). 4. Transmission system according to one of claims 1 or 2, characterized in that the blocking circuit (8) consists of a NOR gate, the input side with the associated address source (1) or address sink (3,3 ') and with a first clock line ( 17) is connected. 5. Transmission system according to one of the preceding claims, characterized by a clock generator (7), in which the start of the second clock signal (Phi2) can be influenced depending on a control signal (CF), and by a control circuit (20) for emitting the control signal (CF ), consisting of a control line (26) which can be precharged by means of a third precharging device (22) in the course of the first clock signal (Phi 1), which has at least one delay unit in its runtime behavior to the address bus (2) or a control line (4 , 4 ') and which is provided with a second discharge device (23) for discharging the control line (26) at the end of the first clock signal (Phi1).

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