EP0127639A1

EP0127639A1 - Clock driver circuit

Info

Publication number: EP0127639A1
Application number: EP19830903654
Authority: EP
Inventors: Jerry Dale Moench
Original assignee: Motorola Inc
Current assignee: Motorola Solutions Inc
Priority date: 1982-12-03
Filing date: 1983-10-06
Publication date: 1984-12-12
Also published as: WO1984002238A1

Abstract

Un circuit d'attaque d'horloge (40) utilise de manière avantageuse des transistors naturels (41) pour coupler un signal à un noeud d'amorçage (54) suivant une configuration succédant à la source dans un système de 5 volts seulement. Un circuit d'amorçage (40) avec un circuit d'attaque (44) de sortie d'un transistor naturel (51) possède une entrée couplée au noeud d'amorçage (54) et une seconde entrée de réception d'un signal retardé. Le signal retardé est reçu en provenance d'un circuit de temporisation (43) qui possède une entrée pour détecter une augmentation de la tension au niveau du noeud d'amorçage (54).A clock driver (40) advantageously uses natural transistors (41) to couple a signal to a trigger node (54) in a successor to source configuration in a 5 volt system only. A priming circuit (40) with a driving circuit (44) for output of a natural transistor (51) has an input coupled to the priming node (54) and a second input for receiving a delayed signal. . The delayed signal is received from a timing circuit (43) which has an input for detecting an increase in voltage at the priming node (54).

Description

CLOCK DRIVER CIRCUIT

Background of the Invention

This invention relates to driver circuits, and more particularly to MOS clock driver circuits having a bootstrap circuit.

In many high speed dynamic circuits a large number of clock signals, for example, 60, may be used for various timing needs. A high density dynamic random access memory (DRAM) is an example of such a circuit. In modern technology, these circuits typically are restrained to require only a 5 volt power supply. Because these clock signals are desirably a full 5 volt signal, bootstrap circuits have been required to obtain the full 5 volts for N channel MOS circuits, which are typical for high density DRAMs. Each clock signal is generated to have a timing relationship to other clock signals. A clock signal is frequently generated in response to another clock signal. There are a number of reasons why it is desirable to minimize the loading effect on a clock signal. The clock signal must have a relatively fast rise time which is adversely effected if it must drive into a large input capacitance. The input of a clock driver circuit is typically on the drain of a self-bootstrapping transistor which couples the input clock signal received on its drain to a bootstrap node coupled to its source. The self-bootstrapping transistor has a gate precharged to an enhancement threshold voltage below 5 volts so that when the input clock signal is received on the drain, the voltage on the gate will rise due to the drain to gate capacitance. The consequent rise in voltage on the source also aids in raising the voltage on the gate due to the source to gate capacitance. The voltage on the gate is thus driven more than a threshold voltage of this transistor above 5 volts so that the full 5 volts of the input signal is coupled to the bootstrap node by its source. Because the bootstrap node has a relatively large capacitor connected to it, the input clock signal receives a relatively large capacitive loading due to being directly coupled to the bootstrap node via the self-bootstrapping transistor.

A bootstrap circuit causes the voltage on the bootstrap node to be increased above the 5 volts so that a source-follower transistor can provide an output clock signal at a full 5 volts. The bootstrap circuit causes the voltage on the bootstrap node to increase in response to receiving a delayed signal which is delayed in time from the 5 volts appearing on the bootstrap node. This has been achieved by providing a delay circuit which receives the input clock signal on an input and then provides the delayed signal to the bootstrap circuit after a predetermined time delay. This establishes a race condition in that the self-bootstrapping transistor must provide the 5 volts on the bootstrap node before the delayed signal is received. The point of origination of the input clock signal may be some distance on the integrated circuit silicon chip from the clock driver circuit. Consequently the routing of the signal path to the self-bootstrapping transistor must be carefully compared to the routing to the delay circuit to ensure that the input clock signal to the self-bootstrapping transistor is not delayed relative to the delay circuit receiving the input clock signal. Additionally a pair of transistors of the bootstrap circuit have their gains in a particular ratio to help ensure that the effect on the bootstrap circuit of receiving the delayed signal is also delayed. Brief Summary of the Invention

An object of the present invention is to provide an improved clock driver circuit. Another object of the invention is to provide a clock driver with reduced input capacitance.

Yet another object of the invention is to provide a clock driver with a bootstrap circuit which operates with a higher degree of predictability. These and other objects of the invention are provided by a clock driver circuit which has a coupling transistor with a first current electrode coupled to a first power supply terminal, a control electrode for receiving an input signal, and a second current electrode coupled to a first node. The clock driver circuit also has a bootstrap circuit and a delay circuit. The bootstrap circuit increases a voltage level present on the first node in response to receiving the input signal on the first node via the coupling transistor and to subsequently receiving a delayed signal on a second node. The delay circuit is coupled between the first and the second node to provide the delayed signal on the second node in response to receiving the input signal via the coupling transistor on the first node.

Brief Description of the Drawings

FIG. 1 is a timing diagram of signals relevant to a clock driver circuit; FIG. 2 is a circuit diagram of a clock driver circuit of the prior art; and

FIG. 3 is a circuit diagram of a clock driver circuit according to a preferred embodiment of the invention. Detailed Description of the Drawings

Shown in FIG. 1 are three signals relating to a clock driver. These signals are an input signal V_I, a precharge signal P, and an output signal V_O. AS shown, the input signal V_I rises at a time t_O from 0 volt (logic low) to 5 volts (logic high). In response the output signal V_O rises from 0 volt to 5 volts at a subsequent time t₁. The time delay between time t_O and time t₁ is desirable. Input signal V_I drops from 5 volt to 0 volt at a time t₂ while output signal V_O remains at 5 volts. Precharge signal P switches from 0 to 5 volts at time t₃ causing output signal V_O to switch from 5 volts to 0 volt. It should be noted that the fall of input signal V_I may also occur at essentially the same time as the rise of precharge signal P without effecting output signal V_O, i.e., time t₂ may be essentially the same as time t₃. The purpose of a clock driver is to provide signal V_O at a full power supply voltage in response to and delayed from the rising edge of input signal V_I and to provide signal V_O at ground potential in response to the rising edge of precharge signal P, all of which is shown in FIG. 1.

Shown in FIG. 2 is a clock driver 10 of the prior art which generates signal V_O as shown in FIG. 1 and which is comprised generally of a delay circuit 11, a bootstrap circuit 12, a buffer circuit 13, a coupling transistor 14, a transistor 16, and a transistor 17. Delay circuit 11 comprises transistors 18, 19, 20 and 21. Bootstrap circuit 12 comprises a transistor 22, a transistor 23, and a capacitor 24. Buffer circuit 13 comprises a transistor 26 and a transistor 27. The transistors of FIG. 2 are, for example, N channel, enhancement mode, insulated gate field effect transistors having a threshold voltage of 0.5 to 1.0 volt. Transistor 16 has a drain connected to a positive power supply terminal V_DD for providing a positive voltage, for example, 5 volts, a gate for receiving precharge signal P, and a source. Coupling transistor 14 has a drain for receiving input signal V_I, a gate connected to the source of transistor 16, and a source connected to a bootstrap node 28. Transistor 17 has a drain connected to the source of transistor 16, a gate for receiving signal V_I , and a source connected to a node 29. Transistor 18 has a drain connected to V_DD, a gate for receiving signal V_I , and a source. Transistor 19 has a drain connected to the source of transistor 18, a gate for receiving signal P, and a source connected to a negative power supply terminal for receiving current, shown as ground. Transistor 20 has a drain connected to V_DD' a gate for receiving signal P, and a source connected to node 29. Transistor 21 has a drain connected to node 29, a gate connected to the source of transistor 18, and a source connected to ground. Transistor 22 has a drain connected to V_DD, a gate connected to node 28, and a source connected to a node 30. Transistor 23 has a drain connected to node 30, a gate connected to node 29, and a source connected to ground. Capacitor 24 has a first terminal connected to node 28 and a second terminal connected to node 30. Transistor 26 has a drain connected to V_DD' a gate connected to node 28, and a source for providing output signal V_O . Transistor 27 has a drain connected to the source of transistor 26, a gate connected to node 29, and a source connected to ground. Circuit 10 is precharged in preparation for receiving signal V_I while signal P is a logic high. With signal P a logic high transistors 16, 19, and 20 are turned on. Transistor 16, in a source-follower configuration, couples to the gate of transistor 14 a voltage equal to the power supply voltage less one enhancement threshold voltage because signal P is a full power supply voltage signal. Transistor 14 is consequently turned on ensuring that node 28 is discharged to ground potential because signal Vj is at ground potential during precharge. This ensures that transistors 22 and 26 are turned off. Transistor 19 being turned on causes transistor 21 to be turned off. Transistor 20, in a source-follower configuration, couples to node 29 the power supply voltage less one enhancement threshold voltage. Node 29 and the gate of transistor 14 are consequently at the same voltage. Transistors 23 and 27 are turned on causing node 30 and signal V_O to be at ground potential. Delay circuit 11 thus provides a logic high to transistors 23 and 27 in response to receiving precharge signal P which causes node 30 and output signal V_O to be a logic low.

When precharge signal P switches to ground potential, transistors 16, 19 and 20 are turned off. The gate of transistor 21 remains at ground potential so that transistor 21 remains turned off. Node 29 and the gate of transistor 14 remain at the supply voltage less one enhancement threshold which maintains each transistor 14, 23 and 27 in a conductive state. Accordingly, node 28, node 30 and signal V_O remain at ground potential.

When input signal V_I switches from a logic low to a logic high, signal V_I is coupled to bootstrap node 28 via coupling transistor 14. Although the voltage on the gate of transistor 14 begins at the power supply voltage less one enhancement threshold voltage, it is brought to a higher voltage by the self-bootstrapping effect caused by the drain to gate and source to gate capacitance. With the gate of transistor 14 at a sufficiently high voltage, the full voltage of signal V_I can be coupled to node 28. Due to the relatively large capacitance on node 28, there is some delay in reaching the full voltage of signal V_I. All of the charging of the capacitance of node 28 is achieved by signal V_I. Node 28 thereby presents a significant capacitive load to signal V_I . Signal V_I at a logic high causes transistor 18 to turn on which in turn causes transistor 21 to turn on. There is some time delay from when signal V_I switches to a logic high to when transistor 21 turns on. The voltage on node 29 is consequently reduced to ground potential to turn off transistors 23 and 27. Delay circuit 11 thereby provides a delay signal which is complementary to and delayed from input signal V_I . Node 30 is held at ground potential while node 28 is increasing in voltage which charges capacitor 24. When transistor 23 turns off, node 30 increases in voltage which, via capacitor 24, causes node 28 to increase in voltage. The object is for node 28 to be at least one enhancement threshold voltage above the power supply voltage so that transistor 26 can provide signal V_O at the power supply voltage. For a threshold voltage of 1.0 volt and a 5 volt power supply, node 28 must be charged to at least 6 volts. For any significant load on signal V_O it is desirable for the voltage on node 28 to be higher.

A potential problem is that node 28 will not reach a sufficiently high voltage before transistor 23 turns off. Due to this uncertainty, the gain of transistor 22 is reduced so that transistor 23 can hold node 30 at ground potential for a little longer. It should be noted that node 30 could be used as an output node of circuit 10 for providing signal V_O . The reason it is not is that transistor 22 is reduced to be too small in gain to be provide a clock output. If transistor 22 were increased in gain, the commensurate increase in gain of transistor 23 would result in transistor 23 being so large that it would be more economical to add buffer circuit 13 instead. Transistor 26 of added buffer circuit 13 does provide the adverse effect of adding capacitance to node 28. Another reaction to signal V_I switching to a logic high is that transistor 17 couples the gate of transistor 14 to node 29 as node 29 is brought to ground potential by delay circuit 11. Transistor 17 is no more than marginally turned on until the voltage on node 29 is reduced so that transistor 17 does not adversely effect the voltage build up on the gate of transistor 14.

That the gate of transistor 14 is brought to ground potential is significant because when V_I is then subsequently brought to a logic low, node 28 is not discharged so that transistor 26 maintains signal V_O at the power supply voltage. When signal V_I switches to a logic low, transistors 17 and 18 are turned off. This leaves node 29 at ground potential which keeps transistors 23 and 27 turned off. Signal V_O consequently remains at the power supply voltage until the next rising edge of precharge signal P at which time signal V_O switches to a logic low and precharge begins again. For the case where the fall of signal V_I is at essentially the same time as the rise of signal P, transistor 27 may turn on before transistor 14 can discharge node 28. The voltage on the gate of transistor 14 must be at least a threshold voltage above the voltage of signal V_I before transistor 14 can begin discharging node 28. This may not occur until after transistor 27 turns on in which case there is disadvantageously a relatively large current path between V_DD and ground through transistors 26 and 27 as well as a somewhat smaller current path through transistors 22 and 23. Shown in FIG. 3 is a clock driver circuit 40 according to a preferred embodiment of the invention which generates output signal V_O as shown in FIG. 1 and which is comprised generally of a natural transistor 41, an enhancement transistor 42, a delay circuit 43, and a bootstrap circuit 44. Enhancement transistors used in circuit 40 have the same characteristics as those of circuit 10 of FIG. 2. Natural transistors used in circuit 40 are substantially the same as the enhancement transistors except they have a characteristic threshold voltage range of 0.1 to 0.3 volt. Delay circuit 43 comprises a natural transistor 46, an enhancement transistor 47, a natural transistor 48, and an enhancement transistor 49. Bootstrap circuit 44 comprises a natural transistor 51, an enhancement transistor 52, and a capacitor 53.

Transistor 41 is a coupling transistor having a drain connected to V_DD, a gate for receiving input signal V_I, and a source connected to a bootstrap node 54. Transistor 42 has a drain connected to node 54, a gate for receiving precharge signal P, and a source connected to ground. Transistor 46 has a drain connected to V_DD, a gate connected to node 54, and a source. Transistor 47 has a drain connected to the source of transistor 46, a gate for receiving signal P, and a source connected to ground. Transistor 48 has a drain connected to V_DD, a gate for receiving signal P, and a source connected to a node 55. Transistor 49 has a drain connected to node 55, a gate connected to the source of transistor 46, and a source connected to ground. Transistor 51 has a drain connected to V_DD, a gate connected to node 54, and a source for providing output signal V_O . Transistor 52 has a drain connected to the source of transistor 51, a gate connected to node 55, and a source connected to ground. Capacitor 53 has a first terminal connected to the drain of transistor 52 and a second terminal connected to node 54.

Circuit 40 is precharged in response to signal P switching to a logic high while signal V_I is a logic low. With signal P at a logic high transistors 42, 47 and 48 are turned on. With transistor 42 turned on, node 54 is coupled to ground ensuring transistors 46 and 51 are turned off. With transistor 47 turned on, transistor 49 is turned off. Transistor 48, in a source-follower configuration, turns on trans istor 52 which in turn causes signal V_O to be at ground potential. When signal P switches to a logic low, node 54 remains at ground potential keeping transistors 46 and 51 turned off whereas node 55 remains charged so that transistor 52 remains turned on, maintaining signal V_O at a logic low. When signal V_I switches to a logic high, transistor 41, in a source-follower configuration, begins quickly charging node 54. Because signal V_I is a full power supply signal, transistor 41 charges node 54 to the power supply voltage less one natural threshold voltage. For a 5 volt power supply and a worst case natural threshold voltage of 0.3 volt, node 54 will charge toward 4.7 volts. As node 54 is rising in voltage, transistor 46 will turn on which will cause transistor 49 to turn on. Transistor 52 will turn off in response to transistor 49 turning on. Because delay circuit 43 is tied directly to node 54, a time delay between the rise in voltage on node 54 and transistor 52 turning on will be very consistent. In effect, transistor 41 couples signal V_I to node 54. In response to node 54 receiving signal V_I via transistor 41, delay circuit 43 provides a delayed signal to bootstrap circuit 44 at node 55. The delayed signal is delayed in time from node 54 receiving signal V_I via transistor 41. The delayed signal is complementary to signal V_I when it is received by bootstrap circuit 44 because the delayed signal switches from a logic high to a logic low in response to signal V_I switching from a logic low to a logic high. Because transistor 52 does not turn off until a time delay from node 54 being charged, capacitor 53 becomes charged because signal V_O is held at logic low by transistor 52 until the delayed signal is received. After transistor 52 turns off, signal V_O begins rising in voltage. Due to capacitor 53 and a gate to source capacitance of transistor 51, node 54 rises in voltage in response to signal V_O rising in voltage. Because transistor 51 may have a threshold voltage of 0.3 volt, node 54 must be at at least 5.3 volts for signal V_O to be 5.0 volts. This is substantially lower than would be required if transistor 51 were an enhancement transistor as was the case in the prior art as shown in FIG. 2 with analogous transistor 22. It should also be noted that circuit 40 requires only one input node, the gate of transistor 41, for receiving input signal V_I.

For a combination of reasons, an extra buffer circuit such as buffer circuit 13 of FIG. 2 is not required for circuit 40 of FIG. 3 to provide signal V_O . Because node 54 does not have to rise to as high of a voltage due to transistor 51 being a natural transistor, because node 54 will rise at a rapid rate due to source-follower transistor 41, and because of the predictable time delay due to an input of delay circuit 43 being connected to node 54, transistor 52 need not have a higher gain than transistor 51 to ensure that signal V_O will stay at ground potential sufficiently long to ensure that capacitor 53 is sufficiently charged. Because the gain of transistor 51 need not be reduced, transistor 51 can be made sufficiently large to be an output transistor. Consequently, bootstrap circuit 44 provides output signal V_O . Of course if an additional buffer circuit is required, a buffer circuit such as buffer circuit 13 of FIG. 2 can easily be added. It should be noted that transistor 41 is advantageously chosen to be a natural transistor instead of an enhancement transistor so that node 54 will rise toward the power supply voltage less one natural threshold voltage instead of less the substantially larger enhancement threshold voltage. The time delay of delay circuit 43 could be increased by choosing transistor 46 to be an enhancement transistor because it would take a higher rise in voltage on node 54 before transistor 46 would turn on although the time delay would become somewhat less predictable due to the greater variation in threshold voltage of the enhancement transistors. Transistor 48 is chosen to be a natural transistor to increase the voltage to transistor 52 and thereby reduce precharge time. When signal V_I switches to a logic low, node 54 remains charged and node 55 remains at ground potential, ensuring that signal V_O remains at the power supply voltage. Transistor 41 is turned off. Signal P subsequently switches to a logic high to begin precharge again, causing transistors 42, 47 and 48 to turn on. Transistor 42 discharges 54 to ground potential, transistor 47 causes transistor 49 to turn off, and transistor 48 to turn on. With node 54 at ground potential transistor 51 is turned off so that transistor 52 turning on causes signal V_O to be a logic low. For the case where the fall of signal V_I is at essentially the same time as the rise of signal P, transistors 41 and 42 will be on at the same time to reduce the voltage on node 54 to some level between that of V_DD and ground before transistor 52 turns on. Although current paths are established between V_DD and ground through transistors 51 and 52, current flow through these paths is relatively small because transistors 41 and 42 are of relatively small gain and because transistor 51 is not turned on very hard due to the reduction in voltage on node 54. Circuit 40 of FIG. 3 thus provides the required signal sequence of FIG. 1 in a substantially improved manner.

While the invention has been described in a preferred embodiment, it will be apparent to those skilled in the art that the disclosed invention may be modified in numerous ways and assume many embodiments other than that specifically set out and described above. Accordingly, it is intended by the appended claims to cover all modifications of the invention which fall within the true spirit and scope of the invention.

Claims

1. A clock driver circuit requiring only a 5 volt power supply for providing a 5 volt output signal in response to receiving a 5 volt input signal, comprising: a coupling transistor having a first current electrode coupled to the 5 volt power supply terminal, a control electrode for receiving the 5 volt input signal, and a second current electrode coupled to a bootstrap node; and a bootstrap circuit coupled between the 5 volt power supply terminal and a ground terminal for increasing a voltage level on the bootstrap node in response to receiving the input signal on the bootstrap node via the coupling transistor and to subsequently receiving a delayed signal.

2. The clock driver circuit of claim 1 wherein the coupling transistor is a natural transistor having a threshold voltage which is less than or equal to 0.3 volt.

3. The bootstrap circuit of claim 2 wherein the bootstrap circuit comprises: a first transistor having a first current electrode coupled to the 5 volt power supply terminal, a control electrode coupled to the bootstrap node, and a second current electrode; a capacitor having a first terminal coupled to the bootstrap node and a second terminal coupled to the second current electrode of the first transistor; and a second transistor having a first current electrode coupled to the second current electrode of the first transistor, a control electrode for receiving the delayed signal, and a second current electrode coupled to the ground terminal.

4. The clock driver circuit of claim 3 further comprising delay means having an input coupled to the bootstrap node for providing the delayed signal in response to receiving the input signal on the bootstrap node via the coupling transistor.

5. The clock driver circuit of claim 4 further characterized as providing an output signal at the second current electrode of the first transistor.

6. The clock driver circuit of claim 3 wherein the first transistor is a natural transistor having a threshold voltage which is less than or equal to 0.3 volt.

7. A clock driver circuit, comprising: coupling means for coupling an input signal to a first node; a bootstrap circuit coupled between first and second power supply terminals for increasing a voltage level on the first node in response to receiving the input signal on the first node via the coupling means and to subsequently receiving a delayed signal on a second node; and delay means coupled between the first and the second node for providing the delayed signal on the second node in response to receiving the input signal via the coupling means on the first node.

8. The clock driver circuit of claim 7 wherein the coupling means is a first transistor having a first current electrode coupled to the first power supply terminal, a control electrode for receiving the input signal, and a second current electrode coupled to the first node.

9. The clock driver circuit of claim 8 wherein the bootstrap circuit comprises: a second transistor having a first current electrode coupled to the first power supply terminal, a control electrode coupled to the first node, and a second current electrode; a capacitor having a first terminal coupled to the bootstrap node and a second terminal coupled to the second current electrode of the second transistor; and a third transistor having a first current electrode coupled to the second current electrode of the second transistor, a control electrode coupled to the second node, and a second current electrode coupled to the second power supply terminal.

10. The clock driver circuit of claim 10 wherein the first and second transistors are natural transistors each having a threshold voltage which is less than or equal to 0.3 volt.