EP0123169B1 - Hybrid-associative memory comprising a non associative base memory and an associative surface - Google Patents

Hybrid-associative memory comprising a non associative base memory and an associative surface Download PDF

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Publication number
EP0123169B1
EP0123169B1 EP84103500A EP84103500A EP0123169B1 EP 0123169 B1 EP0123169 B1 EP 0123169B1 EP 84103500 A EP84103500 A EP 84103500A EP 84103500 A EP84103500 A EP 84103500A EP 0123169 B1 EP0123169 B1 EP 0123169B1
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store
units
sub
address
data
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EP0123169A1 (en
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Gerhard Dipl.-Ing. Wolf
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Siemens AG
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Siemens AG
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/22—Arrangements for sorting or merging computer data on continuous record carriers, e.g. tape, drum, disc
    • G06F7/24—Sorting, i.e. extracting data from one or more carriers, rearranging the data in numerical or other ordered sequence, and rerecording the sorted data on the original carrier or on a different carrier or set of carriers sorting methods in general
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0207—Addressing or allocation; Relocation with multidimensional access, e.g. row/column, matrix
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
    • G06F16/90—Details of database functions independent of the retrieved data types
    • G06F16/903—Querying
    • G06F16/90335—Query processing
    • G06F16/90339—Query processing by using parallel associative memories or content-addressable memories

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  • the invention relates to a hybrid associative memory, according to the features of the preamble of claim 1.
  • hybrid associative memories allow the combination of an associative user interface with a conventional access memory as a basic memory in a simple manner to increase the storage capacity in almost any way, which is a prerequisite for processing large amounts of data, for example.
  • the associative surface consists of a number of comparators corresponding to the number of bits of the data bits to be checked simultaneously, the output signals of which are monitored by a hit evaluation control.
  • An additional mask control means that bit positions that do not correspond to the specified search criteria are excluded from the check.
  • the memory width generally corresponds to a data record of a predetermined length that is to be checked uniformly, the data records stored in the base memory being fed and checked one after the other individually to the associative surface.
  • test options for the simultaneous checking of a predetermined number of data records are provided in a two-dimensional associative surface by corresponding multiplication, and the base memory is correspondingly three-dimensionally constructed in such a way that the simultaneously testable Number of data records can be read simultaneously and switched through to the associative interface - see, for example, data report 11 (1976) issue 2, pages 29 to 34, EP-AI-00036148.
  • the associative memory 100 of the arrangement according to DE-OS 32 16 905 also works according to the same principle of the two-dimensional associative surface, if the registers 101 associated with each associative memory cell 110 are filled with data units from the register module and all associative memory cells simultaneously check the data units provided .
  • the operation unit 105 of each memory cell 110 instead of individual comparators consists of a universally operating combination unit, each of which covers the entire data unit, for executing any associative and other combination functions.
  • hybrid associative memories of this type are generally used as a component of more extensive data processing systems, so that the basic memory must be able to be connected to the data line system of the data processing system without difficulty, which means that the memory sections are structured in accordance with the width of a data unit to be transferred required, which is often not as suitable for associative linking as a different data width.
  • associative processors are known in which, by means of special measures, either a word with N bits or a predetermined bit of N words can be read simultaneously from a word-oriented normal access memory.
  • This requires the memory to be subdivided into matrices or fields of N x N bits, the individual bit columns having to be able to be controlled separately from one another, so that with a single normal word address in each bit column, one bit in a different row within a matrix can be controlled simultaneously and with each of the possible word addresses a different data word or the bit combination of a different bit position of the N data words is obtained depending on the specified operating mode.
  • the respective relevant line in the field is determined by the last 1092 N bits of the word address, while the high-order bits specify the pitch.
  • the last 1 092 N bits are then converted into N column-specific row addresses by address reordering.
  • the N bits of the individual data words have to be shifted cyclically from line to line so that the N bits for each bit position are in different columns and can be selected at the same time. This cause additional shifters during storage and release depends also from last 1092 N bits of each effective word address - you see, for example PROCEEDINGS OF THE FALL JOINT COMPUTER CONFERENCE, San Francisco, 09 to 11 December 1968, pages 949-955.
  • bit combination read in each case in an output register is then processed in connection with other registers by mutually shifting and logically combining the various register information in accordance with a predetermined command sequence, the individual bit columns of a field being checked one after the other with corresponding repetition of the command sequence.
  • the associated bit-serial work takes time, like all pushing operations.
  • all the bit combinations read are each processed as a coherent unit. If, in addition, a larger word length of 64 or 128 bits is considered to be expedient, this means a considerable effort for the necessary address reorderers and the bit shifting devices.
  • the object of the invention is to design hybrid associative memories of the type mentioned at the outset in such a way that, with greater adaptability to various associative tasks, they have a significantly higher performance without the properties of a normal device connected to a data line system of a data processing system with a predetermined transmission width Access memory will be lost. This object is achieved by the characterizing features of patent claim 1.
  • the invention uses the staggered arrangement in the field with the known storage technology, with the option of row or column-oriented access, so that regardless of the data width of the transmission system, the data records of any length can be logically stored in the form of vertical strings in a memory column.
  • the memory width of each column is not limited to one bit of the data unit, however, but comprises sub-units with several bits, for example eight bits. On the one hand, this reduces the number of rows and columns per matrix or field, which requires much less effort for the necessary address and data reordering.
  • the formation of subunits enables a better adaptation to the search criteria, which generally have more bits, since these can no longer be checked bit-by-bit, but rather the associated bits can be checked at the same time.
  • the universal linking units provided for each subunit of a data unit in the associative surface can work together in the conventional manner, check a data unit with appropriate masking in parallel, or a correspondingly large number of corresponding subunits of data units of different data records can be checked simultaneously separately.
  • the hybrid associative memory shown in FIG. 1 is conventionally divided into a normal access memory as the basic memory B-SP and an associative surface ASS-FL with a hit evaluation control T-AUSW.
  • the basic memory B-SP has a working width corresponding to a data unit, the data units being able to be written to and read from one another in the form of a column, and each memory line being individually controllable for selecting a data unit.
  • Each data unit is divided into subunits; in the present case, words with 4 bytes each with 8 bits are used as data units. Depending on the working width of the connected data line system, double words with 8 bytes each could also be used.
  • the basic memory B-SP is divided into a corresponding number of vertical byte columns which are simultaneously controlled by the selection of a data unit or a word by a line-oriented access address AD, for example the data unit AOi with the 4 bytes AOO, A01, A02, A03 in the first line of memory.
  • the individual words are not arranged in the same way in the individual memory lines, but the arrangement follows a predetermined classification scheme, according to which it is possible to access either the 4 bytes of a word in a conventional manner or with each other during memory access read the corresponding bytes of several vertically consecutive words simultaneously in the form of a word.
  • the corresponding bytes of all words in the field i.e. e.g. AOO, BOO, COO and D00 for field F0, cyclically offset by 1 byte, so that the corresponding bytes of all words in the field are each on a diagonal, with the individual diagonals circulating cyclically.
  • Figure 2 shows the basic structure of a double field FO / 1 in the base memory with 4 memory blocks as byte column modules BSP-MDO to BSP-MD3.
  • Each of these blocks has a capacity of 8 bytes, for example, which is divided into two groups of 4 byte rows BZO to BZ3, and each block is coupled to a byte row selection controller BZ-AW, which controls when reading or writing a byte. If the 4 bytes forming a word are in a data unit level, for example in the byte line BZO, then the same line address Z-AD (BSP ...) is supplied to all memory modules BSP-MD ...
  • 2 bits, namely X and Y, which form the row address Z-AD in the field, are sufficient to differentiate between the four rows of memory, each forming a memory field F ... in the base memory B-SP: these together with the field address F-AD in one Address register AD-REG stored row address bits are supplied to an address reorder AD-UM, which provides the required individual addresses Z-AD (BSP %) depending on the selected operating mode MOD.
  • FIG. 3 shows in the form of a block diagram an address reorder AD-UM, as can be used in FIG. 2.
  • This address reorderer consists of 4 modulo-4 working 2-bit subtractors SUB1 to SUB4, to which the output line address Z-AD is supplied as a subtrahend.
  • the Minuend consists of one of the four possible base addresses «0», «1», «2» or «3», the activation of which is controlled by the M UX multiplexer in accordance with the two mode types MOD.
  • the minuend in the form of the base address “0” is the same for all subtractors, so that the same row addresses Z-AD (BSP ...) result for all byte columns.
  • the row address Z-AD is subtracted from one of the possible base addresses, so that there are four different row addresses Z-AD (BSPO) to Z-AD (Ex. 3) corresponding to the modulo 4 shift.
  • BSPO row address
  • Z-AD Z-AD
  • Ex. 3 Z-AD
  • the start of the data unit is shifted in cyclical order by one byte width, as shown in FIG. 1 with the field FO.
  • adders can also be used in a manner known per se.
  • FIG. 4 shows a second exemplary embodiment of the address reorder AD-UM in FIG. 2 with a four-stage shift register S-REG, which ranks one of the usual 4 base addresses “0”, “1”, “2” and “3” in each stage »Saved contains.
  • the row address Z-AD is either fed directly to all 4 OR gates OD via the selection switch DEMUX if the same row is to be controlled in all byte columns, or else it is corresponding to the value of the row address Z -AD via the shift control Z, the content of the shift register S-REG is cyclically shifted in one direction or the other from the starting position and the outputs of the shift register are released via the gate circuit TS.
  • FIG. 5 shows a third exemplary embodiment of the address reorder AD-UM in FIG. 5.
  • the shift register S-REG is provided by 4 selection switches MUX, each with 4 input groups for the 4 different base addresses “0”, “1”, “ 2 »and « 3 »replaced.
  • the effective output line address Z-AD one of the 4 base addresses is switched through to the output in each of the selection switches MUX, the assignment of the base addresses being selected in accordance with the respective classification scheme.
  • All three explained embodiments of the address folder AD-UM are block diagrams in which, with the exception of the operating mode signal MOD, all control paths in the present case each comprise two wires for representing two-digit binary numbers.
  • the control paths would consist of 3 wires, each of which must be switched through.
  • the classification scheme on which the field Fn of the base memory B-SP in FIG. 1 is based works in comparison to that of the field FO according to the opposite principle, i.e. the bytes forming a data unit in normal operation, e.g. AnO, An1, An2 and An3 are each arranged in the diagonal, while the corresponding bytes, e.g. AnO, BnO, Cn0 and DnO, each lie in one plane.
  • the address reorderers Ad-UM explained with reference to FIG. 3 to FIG. 5 can therefore be used in the same way for this reordering scheme, only the operating mode signals MOD must be interchanged accordingly.
  • both classification schemes result in the formation of strings of related data units, e.g. AOi to Ani, with a serial sequence of the individual bytes along the vertical access direction for the basic memory, whereby four parallel data strings, namely AOi to Ani, BOi to Bni, COi to Cni and DOi to Dni, are formed in accordance with the number of bytes in a data level in the present case can be.
  • AOi to Ani with a serial sequence of the individual bytes along the vertical access direction for the basic memory
  • the correct byte sequence e.g. AOO, A01, A02, A03 or AnO, BnO, CnO, DnO.
  • the data units are routed via reordering devices D-UM-EG or D-UM-AG both during the storage and the retrieval and through one dependent on the row address Z-AD cyclical shifting of the respective byte series creates the required sequence.
  • the data reorderers can be constructed in a similar manner to the address reorderers in FIG. 4 or better in FIG.
  • a single data folder D-UM can also be provided, as shown in FIG.
  • the DEMUX and MUX path switches the data flow paths must be switched depending on the EG / AG control signals for input or output so that they always lead via the D-UM data reorderer.
  • the direction of movement of the data folder must be specified based on the input / output control signal EG / AG so that the data folder can work properly.
  • the processing power of the hybrid associative memory can be increased significantly if an address mask is connected to the address control AD-ST, so that, for example, the entire basic memory is not checked in the vertical direction during a search, but only a selected area and / or that not every data unit level, but only certain data unit levels are controlled in each field in the selected area.
  • This can the data flow to the associative interface ASS-FL is in many cases specifically limited to the data that is required for the associative checking process, so that a check can be carried out much faster in many cases.
  • Such an address masking control is shown in FIG. 7. It essentially consists of an encoded address counter AD-Z for identifying a memory area in the basic memory B-SP based on the address part AD1 and a mask register M-REG with one bit position per data line in the memory area defined by the address part AD1.
  • the outputs of the mask register M-REG are monitored with a priority circuit PRIO, which delivers the associated coded partial address AD2, which forms the respective access address AD together with the partial address AD1, for each marked input sequentially clocked by the memory cycle clock T Sp.
  • the individual data lines in the selected memory area of the base memory can thus be controlled successively in any combination or data lines in any combination can be excluded from the control.
  • the address counter AD-Z and the mask register M-REG are preset from an address memory AD-SP which, when activated with the signal lad after recognition of the last marked register output by the priority circuit PRIO, the next address entry in the form of the partial address AD1 and the line mask Z -MASK provides.
  • the width of the line mask Z-MASK is expediently chosen in such a way that for the majority of the application cases there is an optimal relationship between the amount of memory on the one hand and the control or time required on the other. If necessary, you can also work with variable field lengths for the address part AD1 and the mask part Z-MASK.
  • FIG. 8 shows the expansion of the basic memory B-SP from FIG. 1 with a single memory group to, for example, 16 memory groups MDO to MD15, which can be arranged one behind the other in the form of a three-dimensional memory or next to one another in the form of a two-dimensional memory and can each be controlled separately.
  • the field and row selection takes place in parallel in the individual storage groups, so that - as shown - the effort for the address reorder AD-UM does not increase.
  • a base memory B-SP designed according to FIG. 8 is also particularly suitable for loading and unloading in streaming mode if the data are processed in such a way that data units can be entered one after the other in separate memory groups. This preparation is done by an upstream buffer memory.
  • Figure 9 shows a corresponding basic circuit.
  • only four memory groups MDO to MD3 are provided for the base memory B-SP and only one field Fn is shown, so that a total of 16 vertical strings A to P of 4 bytes each correspond to 16 data units.
  • each storage group MDO to MD3 in the basic memory B-SP there is one individual memory for each storage group MDO to MD3 in the basic memory B-SP, that is to say the four individual memories E-SP1 to E-SP4 in total.
  • Each single memory E-SP ... has a capacity corresponding to the number of strings or data units per storage group MD ...
  • These individual memories are loaded continuously one after the other from the periphery PE via the selection switch MUX1, the row address Z-AD of the individual memories being identical to that of the basic memory B-SP.
  • the data units identified by the same row address Z-AD are successively forwarded from all individual memories E-SP1 to E-SP4 to the associated memory groups MDO to MD3 of the base memory B-SP. These are therefore the data units A, E, I and M for the first line of all individual memories E-SP1 to E-SP4, which are stored in the base memory B-SP with the same line address setting. Accordingly, when outputting from the base memory B-SP, the individual data units, e.g. A, E, 1, M are successively written into the corresponding memory sections of the individual memories E-SP1 to E-SP4, and progressively from line to line until the buffer memory P-SP is filled.
  • the individual memories, e.g. E-SP1 before switching to the following individual memory, e.g. E-SP2, each completely empty.
  • memory areas of a uniform memory can be used.
  • the individual memory sections for example for data unit A, can be replaced by a number of memory sections lying one below the other corresponding to the respective string length ten are replaced so that, for example, 16 data words AOi to A15i can be stored in succession as a string with 64 bytes and in the same arrangement, the strings A to P can be stored one after the other.
  • the invention enables a very powerful hybrid associative memory that can be easily adapted to different operating cases, the universal linking elements ALV ... of the associative surface ASS-FL and the hit evaluation device T-AUSW based on the DE-OS 3216905 already mentioned at the beginning known arrangement can be formed.

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Abstract

1. A hybrid associative store, comprising a non-associative base store (B-SP) with write- and read devices for the selected input and output of data units via an input/output transmission system (DEG/D-AG) which corresponds to the length of the data units and comprising an associative area (ASS-FL) for testing the data units supplied from the base store (B-SP), characterised in that - each data unit (e.g. A0) is sub-divided into a given number (e.g. 4) of sub-units (e.g. bytes A00 to A03), each of which comprises a plurality of bits (e.g. 8 bits), - that the base store (B-SP) is sub-divided into arrays (e.g. F0 to Fn), each of which can be activated by an array address (e.g. F-AD0) of an address control unit (AD-ST) and each of which is formed by a number of data unit store sections - corresponding to the number of sub-units per data unit - in various data unit levels, where a row address (Z-AD), which supplements the respective array address (F-AD) to form a standard access address (AD), specifies the respective data unit store section within the respective array, - that in dependence upon an address reclassifier (AD-UM), which analyses the row address (Z-AD), in the address control unit (AD-ST), the sub-unit store sections within the array (F0), which correspond to the sub-units of the data units (e.g. A0, B0, C0 and D0) which each form an array (e.g. F0), are separated and can be activated, distributed in accordance with a given classification plan, in such manner that the mutually-corresponding sub-units (e.g. A00, B00, C00 and D00) of all the data units (A0 to D0) of the array (F0) can each be stored in different sub-unit store sections of the individual data unit levels and, in dependence upon the selected operating mode (MOD), either the purposive, simultaneous selection of the sub-units (e.g. A00, A01, A02 and A03) which form a data unit is possible in the case of normal store operation or the purposive, simultaneous selection of the mutually corresponding sub-units (e.g. A00, B00, C00 and D00) of all the data units of an array (F0) is possible in the case of associative store operation, - that in the address control unit (AD-ST), not only the access address (AD) but also the array address (F-AD), when the row address (ZAD) is constant, can be changed in stepped fashion so that consecutive data units (e.g. AO to An) which are directly linked on the basis of the selected classification plan can each be allocated to the data unit levels, specified by the constant row address (Z-AD), f consecutive arrays (F0 to Fn), - that in dependence upon reclassification devices (D-UM-EG, D-UM-AG) which likewise analyse the row address (Z-AD), the sub-units of the group of sub-units which is to be input or output, corresponding to a data unit, can be regrouped in accordance with the selected classification plan for the arrays (e.g. F0 to Fn) prior to input or prior to output in order to ensure the necessary storage sequence during input and in order to ensure the original sequence following output and - that in respect of each sub-unit, the associative area (ASS-FL) is assigned a universal logic-linking unit (e.g. ALV1 to ALV4) which carries out parallel processing of the bits of the supplied sub-unit and whose result outputs are coupled to the associated hit analysis control unit (T-AUSW.).

Description

Die Erfindung betrifft einen Hybrid-Assoziativspeicher, entsprechend den Merkmalen des Oberbegriffes des Patentanspruches 1.The invention relates to a hybrid associative memory, according to the features of the preamble of claim 1.

Hybrid-Assoziativspeicher ermöglichen im Gegensatz zu reinen Assoziativspeichern durch die Kombination einer assoziativen Oberfläche mit einem konventionellen Zugriffsspeicher als Basis- speicher in einfacher Weise eine fast beliebige Erhöhung der Speicherkapazität, die beispielsweise Voraussetzung für die Bearbeitung grosser Datenmengen ist.In contrast to pure associative memories, hybrid associative memories allow the combination of an associative user interface with a conventional access memory as a basic memory in a simple manner to increase the storage capacity in almost any way, which is a prerequisite for processing large amounts of data, for example.

Die assoziative Oberfläche besteht bei einer überwiegenden Anzahl von bekannten Hybrid-Assoziativspeichern aus einer der Bitzahl der gleichzeitig zu prüfenden Datenbits entsprechenden Anzahl von Vergleichern, deren Ausgangssignale von einer Trefferauswertesteuerung überwacht werden. Durch eine zusätzliche Maskensteuerung werden dabei den vorgegebenen Suchkriterien nicht entsprechende Bitstellen von der Überprüfung ausgeschlossen. Die Speicherbreite entspricht dabei in der Regel einem einheitlich zu prüfenden Datensatz vorgegebener Länge, wobei die im Basisspeicher gespeicherten Datensätze im einfachsten Fall einzeln nacheinander der assoziativen Oberfläche zugeführt und geprüft werden.In a predominant number of known hybrid associative memories, the associative surface consists of a number of comparators corresponding to the number of bits of the data bits to be checked simultaneously, the output signals of which are monitored by a hit evaluation control. An additional mask control means that bit positions that do not correspond to the specified search criteria are excluded from the check. The memory width generally corresponds to a data record of a predetermined length that is to be checked uniformly, the data records stored in the base memory being fed and checked one after the other individually to the associative surface.

Vielfach sind daher, um die Prüfdauer für alle im Basisspeicher gespeicherten Datensätze zu verringern, in einer zweidimensional ausgebildeten assoziativen Oberfläche durch entsprechende Vervielfachung Prüfmöglichkeiten für die gleichzeitige Prüfung einer vorgegebenen Anzahl von Datensätzen vorgesehen, und der Basisspeicher ist entsprechend dreidimensional so aufgebaut, dass die gleichzeitig prüfbare Anzahl von Datensätzen gleichzeitig gelesen und zur assoziativen Oberfläche durchgeschaltet werden können - man siehe zum Beispiel data report 11 (1976) Heft 2, Seiten 29 bis 34, EP-AI-00036148.In order to reduce the test duration for all data records stored in the base memory, test options for the simultaneous checking of a predetermined number of data records are provided in a two-dimensional associative surface by corresponding multiplication, and the base memory is correspondingly three-dimensionally constructed in such a way that the simultaneously testable Number of data records can be read simultaneously and switched through to the associative interface - see, for example, data report 11 (1976) issue 2, pages 29 to 34, EP-AI-00036148.

Nach dem gleichen Prinzip der zweidimensional ausgebildeten assoziativen Oberfläche arbeitet auch der Assoziativspeicher 100 der Anordnung nach der DE-OS 32 16 905, wenn die jeder Assoziativspeicherzelle 110 zugehörigen Register 101 mit Dateneinheiten aus dem Registermodul gefüllt sind und alle Assoziativspeicherzellen gleichzeitig die zur Verfügung gestellten Dateneinheiten überprüfen. Das Operationswerk 105 jeder Speicherzelle 110 besteht anstelle von einzelnen Vergleichern aus einem jeweils die gesamte Dateneinheit erfassenden universell arbeitenden Verknüpfungswerk zur Ausführung von beliebigen assoziativen und sonstigen Verknüpfungsfunktionen.The associative memory 100 of the arrangement according to DE-OS 32 16 905 also works according to the same principle of the two-dimensional associative surface, if the registers 101 associated with each associative memory cell 110 are filled with data units from the register module and all associative memory cells simultaneously check the data units provided . The operation unit 105 of each memory cell 110 instead of individual comparators consists of a universally operating combination unit, each of which covers the entire data unit, for executing any associative and other combination functions.

Von Nachteil bei beiden Lösungen ist, dass von den einheitlich zu prüfenden Dateneinheiten vielfach nur ein Teil jeweils zur Prüfung benötigt und der nicht benötigte Teil durch die Maskensteuerung abgedeckt werden muss. Die Arbeitskapazität der assoziativen Oberfläche wird daher vielfach nur unzureichend genutzt.A disadvantage of both solutions is that often only a part of the data units to be tested is required for testing and the part that is not required must be covered by the mask control. The working capacity of the associative surface is therefore often underused.

Ein weiteres Problem ergibt sich daraus, dass derartige Hybrid-Assoziativspeicher in der Regel als Bestandteil von umfassenderen Datenverarbeitungsanlagen eingesetzt werden, so dass der Basisspeicher an das Datenleitungssystem der Datenverarbeitungsanlage ohne Schwierigkeiten anschliessbar sein muss, was eine Strukturierung der Speicherabschnitte entsprechend der zu übertragenden Breite einer Dateneinheit erfordert, die vielfach für die assoziative Verknüpfung nicht so geeignet ist, wie eine davon abweichende Datenbreite.Another problem arises from the fact that hybrid associative memories of this type are generally used as a component of more extensive data processing systems, so that the basic memory must be able to be connected to the data line system of the data processing system without difficulty, which means that the memory sections are structured in accordance with the width of a data unit to be transferred required, which is often not as suitable for associative linking as a different data width.

Andererseits sind assoziative Prozessoren bekannt, bei denen durch gesonderte Massnahmen aus einem wortorientierten normalen Zugriffsspeicher entweder ein Wort mit N Bits oder aber ein vorgegebenes Bit von N Wörtern gleichzeitig gelesen werden können. Dies setzt eine Unterteilung des Speichers in Matrizen oder Felder von N x N Bits voraus, wobei die einzelnen Bitspalten getrennt voneinander ansteuerbar sein müssen, so dass mit einer einzigen normalen Wortadresse in jeder Bitspalte ein Bit in jeweils einer anderen Zeile innerhätb einer Matrix gleichzeitig ansteuerbar ist und mit jeder der möglichen Wortadressen jeweils ein anderes Datenwort oder die Bitkombination jeweils einer anderen Bitstelle der N Datenwörter abhängig vom vorgegebenen Betriebsmodus erhalten wird. Die jeweils massgebliche Zeile im Feld wird dabei durch die letzten 1092N Bits der Wortadresse bestimmt, während die höherwertigen Bits das Feld festlegen. Durch Adressenumordner werden die letzten 1092N Bits dann in N spaltenindividuelle Zeilenadressen umgesetzt. Ausserdem müssen die N Bits der einzelnen Datenwörter noch von Zeile zu Zeile zyklisch verschoben werden, damit die N-Bits für jede Bitstelle in verschiedenen Spalten liegen und gleichzeitig ausgewählt werden können. Dies bewirken zusätzliche Schiebeeinrichtungen beim Ein- und Ausspeichern abhängig ebenfalls von den letzten 1092N Bits der jeweils wirksamen Wortadresse - man siehe z.B. PROCEEDINGS OF THE FALL JOINT COMPUTER CONFERENCE, San Francisco, 09. bis 11. Dezember 1968, Seiten 949 bis 955.On the other hand, associative processors are known in which, by means of special measures, either a word with N bits or a predetermined bit of N words can be read simultaneously from a word-oriented normal access memory. This requires the memory to be subdivided into matrices or fields of N x N bits, the individual bit columns having to be able to be controlled separately from one another, so that with a single normal word address in each bit column, one bit in a different row within a matrix can be controlled simultaneously and with each of the possible word addresses a different data word or the bit combination of a different bit position of the N data words is obtained depending on the specified operating mode. The respective relevant line in the field is determined by the last 1092 N bits of the word address, while the high-order bits specify the pitch. The last 1 092 N bits are then converted into N column-specific row addresses by address reordering. In addition, the N bits of the individual data words have to be shifted cyclically from line to line so that the N bits for each bit position are in different columns and can be selected at the same time. This cause additional shifters during storage and release depends also from last 1092 N bits of each effective word address - you see, for example PROCEEDINGS OF THE FALL JOINT COMPUTER CONFERENCE, San Francisco, 09 to 11 December 1968, pages 949-955.

Die in ein Ausgaberegister jeweils gelesene Bitkombination wird dann in Verbindung mit weiteren Registern durch gegenseitiges Verschieben und logisches Verknüpfen der verschiedenen Registerinformationen entsprechend einer vorgegebenen Befehlsfolge verarbeitet, wobei gegebenenfalls die einzelnen Bitspalten eines Feldes nacheinander bei entsprechender Wiederholung der Befehlsfolge überprüft werden. Das damit verbundene bitserielle Arbeiten kostet Zeit, wie überhaupt alle Schiebevorgänge. Ausserdem werden wie bei den vorgenannten Hybrid-Assoziativspeichern alle gelesenen Bitkombinationen jeweils als zusammenhängende Einheit verarbeitet. Wenn dabei ausserdem eine grössere Wortlänge von 64 oder 128 Bits als zweckmässig angesehen wird, so bedeutet das einen erheblichen Aufwand für die erforderlichen Adressenumordner und die Bitverschiebeeinrichtungen.The bit combination read in each case in an output register is then processed in connection with other registers by mutually shifting and logically combining the various register information in accordance with a predetermined command sequence, the individual bit columns of a field being checked one after the other with corresponding repetition of the command sequence. The associated bit-serial work takes time, like all pushing operations. In addition, as with the aforementioned hybrid associative memories, all the bit combinations read are each processed as a coherent unit. If, in addition, a larger word length of 64 or 128 bits is considered to be expedient, this means a considerable effort for the necessary address reorderers and the bit shifting devices.

Aufgabe der Erfindung ist es, ausgehend von Hybrid-Assoziativspeichern der eingangs genannten Art diese so zu gestalten, dass sie bei grösserer Anpassungsfähigkeit an verschiedene assoziative Aufgaben eine wesentlich höhere Leistungsfähigkeit aufweisen, ohne dass die Eigenschaften eines an ein Datenleitungssystem einer Datenverarbeitungsanlage mit vorgegebener Übertragungsbreite angeschlossenen normalen Zugriffsspeichers dadurch verlorengehen. Diese Aufgabe wird durch die kennzeichnenden Merkmale des Patentanspruches 1 gelöst.The object of the invention is to design hybrid associative memories of the type mentioned at the outset in such a way that, with greater adaptability to various associative tasks, they have a significantly higher performance without the properties of a normal device connected to a data line system of a data processing system with a predetermined transmission width Access memory will be lost. This object is achieved by the characterizing features of patent claim 1.

Die Erfindung nutzt dabei die durch die bekannte Speichertechnik der versetzten Anordnung im Feld mit der wahlweisen Möglichkeit des zeilen- oder spaltenorientierten Zugriffs, damit unabhängig von der Datenbreite des Übertragungssystems die Datensätze beliebiger Länge logisch in Form von vertikalen Strings in einer Speicherspalte gespeichert werden können. Die Speicherbreite jeder Spalte ist aber nicht auf ein Bit der Dateneinheit beschränkt, sondern umfasst Subeinheiten mit mehreren Bits, zum Beispiel acht Bits. Dadurch wird einerseits die Zeilen- und Spaltenzahl je Matrix oder Feld verringert, was einen wesentlich geringeren Aufwand für die notwendigen Adressen- und Datenumordner erfordert. Ausserdem ermöglicht die Bildung von Subeinheiten eine bessere Anpassung an die in der Regel mehr Bit umfassenden Suchkriterien, da diese nicht mehr bitseriell zu überprüfen sind, sondern die zugehörigen Bits gleichzeitig überprüft werden können. Entsprechend können die je Subeinheit einer Dateneinheit in der assoziativen Oberfläche vorgesehenen universellen Verknüpfungseinheiten in der herkömmlichen Weise zusammenarbeitend, eine Dateneinheit mit entsprechender Maskierung parallel überprüfen, oder aber es können entsprechend viele einander korrespondierende Subeinheiten von Dateneinheiten verschiedener Datensätze voneinander getrennt gleichzeitig überprüft werden.The invention uses the staggered arrangement in the field with the known storage technology, with the option of row or column-oriented access, so that regardless of the data width of the transmission system, the data records of any length can be logically stored in the form of vertical strings in a memory column. The memory width of each column is not limited to one bit of the data unit, however, but comprises sub-units with several bits, for example eight bits. On the one hand, this reduces the number of rows and columns per matrix or field, which requires much less effort for the necessary address and data reordering. In addition, the formation of subunits enables a better adaptation to the search criteria, which generally have more bits, since these can no longer be checked bit-by-bit, but rather the associated bits can be checked at the same time. Accordingly, the universal linking units provided for each subunit of a data unit in the associative surface can work together in the conventional manner, check a data unit with appropriate masking in parallel, or a correspondingly large number of corresponding subunits of data units of different data records can be checked simultaneously separately.

Die Kombination der Merkmale des Patentanspruches 1 ergibt daher insgesamt einen wesentlich verbesserten und leistungsfähigeren Hybrid-Assoziativspeicher als Funktionseinheit zur Durchführung von vielfältigen Assoziationsfunktionen, dessen Leistungsfähigkeit zudem durch eine modulartige Erweiterung zu einer dreidimensionalen Anordnung bei gleichzeitiger Ausnutzung der vorhandenen Adressenumordner vervielfacht werden kann, da alle Subeinheiten einer Speicherebene gleichzeitig zur assoziativen Oberfläche übertragen werden können und nicht erst nacheinander bereitgestellt werden müssen. Diese und andere Weiterbildungen der Erfindung ergeben sich aus den übrigen Patentansprüchen.The combination of the features of claim 1 therefore results overall in a significantly improved and more powerful hybrid associative memory as a functional unit for carrying out diverse association functions, the performance of which can also be multiplied by a modular extension to a three-dimensional arrangement with simultaneous use of the existing address reorderer, since all subunits a storage level can be transferred simultaneously to the associative surface and do not have to be made available one after the other. These and other developments of the invention result from the remaining claims.

Einzelheiten der Erfindung seien nachfolgend anhand von in der Zeichnung dargestellten Ausführungsbeispielen näher erläutert. Im einzelnen zeigen

  • Fig. 1 ein Prinzipschaltbild des Hybrid-Assoziativspeichers gemäss der Erfindung,
  • Fig. 2 ein Prinzipschaltbild der zugehörigen Adressensteuerung,
  • Fig. 3 bis 5 drei Ausführungsbeispiele für den Adressenumordner in Form von Prinzipschaltbildern,
  • Fig. 6 ein Prinzipschaltbild zur Erläuterung der Einfügung des Datenumordners von Fig. 1 in die verschiedenen Datenflusswege,
  • Fig. 7 ein Prinzipschaltbild der mit der Adressensteuerung von Fig. 2 koppelbaren Adressenmaskensteuerung
  • Fig. 8 den prinzipiellen Aufbau eines Basisspeichers von Fig. 1 aus mehreren Speichergruppen mit gemeinsamem Adressenumordner und
  • Fig. 9 die Kopplung eines Pufferspeichers mit dem Basisspeicher von Fig. 8 in prinzipieller Darstellung.
Details of the invention are explained in more detail below with reference to exemplary embodiments shown in the drawing. Show in detail
  • 1 is a schematic diagram of the hybrid associative memory according to the invention,
  • 2 shows a basic circuit diagram of the associated address control,
  • 3 to 5 three embodiments for the address reorderer in the form of block diagrams,
  • 6 shows a basic circuit diagram for explaining the insertion of the data folder of FIG. 1 into the different data flow paths,
  • FIG. 7 shows a basic circuit diagram of the address mask control that can be coupled to the address control of FIG. 2
  • Fig. 8 shows the basic structure of a base memory of Fig. 1 from several memory groups with a common address reorder and
  • Fig. 9 shows the coupling of a buffer memory with the base memory of Fig. 8 in a basic representation.

Der in Figur 1 gezeigte Hybrid-Assoziativspeicher gliedert sich in herkömmlicher Weise in einen normalen Zugriffsspeicher als Basisspeicher B-SP und eine assoziative Oberfläche ASS-FL mit einer Trefferauswertesteuerung T-AUSW.The hybrid associative memory shown in FIG. 1 is conventionally divided into a normal access memory as the basic memory B-SP and an associative surface ASS-FL with a hit evaluation control T-AUSW.

Der Basisspeicher B-SP hat eine einer Dateneinheit entsprechende Arbeitsbreite, wobei in herkömmlicher Weise die Dateneinheiten säulenförmig untereinander einschreibbar und auslesbar sind und jede Speicherzeile zur Auswahl einer Dateneinheit einzeln ansteuerbar ist. Jede Dateneinheit ist in Subeinheiten unterteilt; im vorliegenden Falle sind als Dateneinheiten Wörter mit je 4 Byte zu je 8 Bit zugrundegelegt. Abhängig von der Arbeitsbreite des angeschlossenen Datenleitungssystems könnten es auch Doppelwörter mit je 8 Byte sein.The basic memory B-SP has a working width corresponding to a data unit, the data units being able to be written to and read from one another in the form of a column, and each memory line being individually controllable for selecting a data unit. Each data unit is divided into subunits; in the present case, words with 4 bytes each with 8 bits are used as data units. Depending on the working width of the connected data line system, double words with 8 bytes each could also be used.

Entsprechend gliedert sich der Basisspeicher B-SP in eine entsprechende Anzahl von vertikalen Bytespalten, die bei der Auswahl einer Dateneinheit oder eines Wortes durch eine zeilenorientierte Zugriffsadresse AD gleichzeitig angesteuert werden, beispielsweise die Dateneinheit AOi mit den 4 Bytes AOO, A01, A02, A03 in der ersten Speicherzeile.Correspondingly, the basic memory B-SP is divided into a corresponding number of vertical byte columns which are simultaneously controlled by the selection of a data unit or a word by a line-oriented access address AD, for example the data unit AOi with the 4 bytes AOO, A01, A02, A03 in the first line of memory.

Nun sind aber aus noch zu erläuternden Gründen die einzelnen Wörter nicht in gleicher Weise in den einzelnen Speicherzeilen angeordnet, sondern die Anordnung folgt einem vorgegebenen Einordnungsschema, demzufolge es möglich ist, bei einem Speicherzugriff entweder die 4 Bytes eines Wortes in herkömmlicher Weise oder aber die miteinander korrespondierenden Bytes mehrerer vertikal aufeinanderfolgender Wörter gleichzeitig in Form eines Wortes auszulesen.Now, for reasons to be explained, the individual words are not arranged in the same way in the individual memory lines, but the arrangement follows a predetermined classification scheme, according to which it is possible to access either the 4 bytes of a word in a conventional manner or with each other during memory access read the corresponding bytes of several vertically consecutive words simultaneously in the form of a word.

Entsprechend den gewählten 4 Bytes in jeder Speicherzeile bilden daher entsprechend viele Dateneinheiten oder Wörter jeweils ein Speicherfeld F, z.B. die Wörter AOi, BOi, COi und DOi für das Feld F0, das durch einen Feldadressteil F-AD = 0 innerhalb der Zugriffsadresse AD ansteuerbar ist. Von Speicherzelle zu Speicherzeile werden dabei die miteinander korrespondierenden Bytes aller Wörter im Feld, also z.B. AOO, BOO, COO und D00 für das Feld F0, zyklisch um 1 Byte versetzt angeordnet, so dass die miteinander korrespondierenden Bytes aller Wörter im Feld jeweils auf einer Diagonale liegen, wobei die einzelnen Diagonalen zyklisch umlaufen.Corresponding to the 4 bytes selected in each memory line, a corresponding number of data units or words therefore form a memory field F, e.g. the words AOi, BOi, COi and DOi for the field F0, which can be controlled by a field address part F-AD = 0 within the access address AD. The corresponding bytes of all words in the field, i.e. e.g. AOO, BOO, COO and D00 for field F0, cyclically offset by 1 byte, so that the corresponding bytes of all words in the field are each on a diagonal, with the individual diagonals circulating cyclically.

Damit dennoch der herkömmliche Zugriffmechanismus zu den einzelnen Dateneinheiten in den einzelnen Dateneinheitsebenen oder Speicherzeilen nach aussen aufrecht erhalten werden kann, ist für den Zeilenadressteil Z-AD als weiterer Bestandteil der Zugriffsadresse AD neben dem Feldadressteil F-AD eine Umordnung innerhalb der Adressensteuerung AD-ST erforderlich, indem jede Bytespalte des Feldes gesondert mit einer gesonderten Zeilenadresse angesteuert wird. Dies lässt sich ohne Schwierigkeit realisieren, wenn man für die einzelnen Bytespalten getrennte Speicherbausteine verwendet, was für einen Basisspeicher B-SP grösserer Speicherkapazität ohnehin unumgänglich ist.So that the conventional access mechanism to the individual data units in the individual data unit levels or memory lines can still be maintained externally, a further reorganization within the address control AD-ST is required for the line address part Z-AD as a further component of the access address AD in addition to the field address part F-AD by controlling each byte column of the field separately with a separate row address. This can be achieved without difficulty if separate memory modules are used for the individual byte columns, which is essential for a basic memory B-SP with a larger memory capacity.

Figur 2 zeigt den prinzipiellen Aufbau eines Doppelfeldes FO/1 im Basisspeicher mit 4 Speicherbausteinen als Bytespaltenmodule BSP-MDO bis BSP-MD3. Jeder dieser Bausteine hat ein Fassungsvermögen von z.B. 8 Byte, die in zwei Gruppen zu je 4 Bytezeilen BZO bis BZ3 gegliedert sind, und jeder Baustein ist mit einer Bytezeilenauswahlsteuerung BZ-AW gekoppelt, über die die Ansteuerung beim Lesen oder Schreiben eines Bytes erfolgt. Liegen die ein Wort bildenden 4 Bytes in einer Dateneinheitsebene, z.B. in der Bytezeile BZO, dann wird allen Speicherbausteinen BSP-MD ... dieselbe Zeilenadresse Z-AD(BSP ...) zugeführt. Liegen die ein Wort bildenden Bytes jedoch diagonal versetzt in unterschiedlichen Dateneinheitsebenen, dann erhalten alle Speicherbausteine unterschiedliche Zeilenadressen Z-AD(Bspo)bis Z-AD(BSP3), wobei in beiden Fällen die Gruppenauswahl je Speicherbaustein durch die gesamte oder einen Teil der Feldadresse F-AD gesteuert wird.Figure 2 shows the basic structure of a double field FO / 1 in the base memory with 4 memory blocks as byte column modules BSP-MDO to BSP-MD3. Each of these blocks has a capacity of 8 bytes, for example, which is divided into two groups of 4 byte rows BZO to BZ3, and each block is coupled to a byte row selection controller BZ-AW, which controls when reading or writing a byte. If the 4 bytes forming a word are in a data unit level, for example in the byte line BZO, then the same line address Z-AD (BSP ...) is supplied to all memory modules BSP-MD ... However, if the bytes forming a word are diagonally offset in different data unit levels, then all memory modules receive different row addresses Z-AD ( Bs p o ) to Z-AD ( BSP3 ), in both cases the group selection per memory module by all or part of the Field address F-AD is controlled.

Beim gewählten Ausführungsbeispiel genügen zur Unterscheidung der vier jeweils ein Speicherfeld F... im Basisspeicher B-SP bildenden Speicherzeilen 2 Bit, nämlich X und Y, die die Zeilenadresse Z-AD im Feld bildet: Diese zusammen mit der Feldadresse F-AD in einem Adressenregister AD-REG gespeicherten Zeilenadressbits werden einem Adressenumordner AD-UM zugeführt, der abhängig vom gewählten Betriebsmodus MOD die benötigten Einzeladressen Z-AD(BSP ...) bereitstellt.In the selected exemplary embodiment, 2 bits, namely X and Y, which form the row address Z-AD in the field, are sufficient to differentiate between the four rows of memory, each forming a memory field F ... in the base memory B-SP: these together with the field address F-AD in one Address register AD-REG stored row address bits are supplied to an address reorder AD-UM, which provides the required individual addresses Z-AD (BSP ...) depending on the selected operating mode MOD.

Bei dem sich aus dem Speicherfeld FO des Basisspeichers B-SP in Figur 1 ergebenden Einordnungsschema liegen alle eine Dateneinheit bildenden Bytes in einer Ebene, nur die Reihenfolge der Bytes innerhalb der einzelnen Wörter ist zyklisch vertauscht. Insbesondere beim normalen Speicherbetrieb sind daher jeweils alle in einer Zeile liegenden Bytes anzusteuern, was ein und dieselbe Zeilenansteueradresse Z-AD(BSP ...) in Figur 2 erfordert, während beim Lesen bzw. Schreiben von Dateneinheiten, die aus den miteinander korrespondierenden Bytes aller Wörter im Feld zusammengesetzt werden, für jede Bytespalte unterschiedliche Zeilenadressen Z-AD(Bspo) bis Z-AD(BSP3) zur Verfügung zu stellen sind, und zwar abhängig von dem die zugehörige Dateneinheitsebene im Basisspeicher B-SP kennzeichnenden Zeilenadressteil Z-AD der Zugriffsadresse AD.In the arrangement scheme resulting from the memory field FO of the basic memory B-SP in FIG. 1, all the bytes forming a data unit lie on one level, only the order of the bytes within the individual words is cyclically interchanged. In normal memory operation in particular, all the bytes in a line must therefore be driven, which requires one and the same line drive address Z-AD (BSP ...) in FIG. 2, while when reading or writing data units, all of the bytes corresponding to each other Words are put together in the field, different row addresses Z-AD ( Bs p o ) to Z-AD (BSP3) are to be provided for each byte column, depending on the row address part Z-AD characterizing the associated data unit level in the base memory B-SP the access address AD.

Figur 3 zeigt in Form eines Prinzipschaltbildes einen Adressenumordner AD-UM, wie er in Figur 2 verwendet werden kann. Dieser Adressenumordner besteht aus 4 Modulo-4 arbeitenden 2-Bit-Subtrahierern SUB1 bis SUB4, denen als Subtrahend die Ausgangszeilenadresse Z-AD zugeführt wird. Der Minuend besteht jeweils aus einer der möglichen 4 Basisadressen «0», «1», «2»-oder «3», deren Zuschaltung entsprechend den beiden Modusarten MOD durch Multiplexer M UX gesteuert wird. Im Normalbetrieb des Basisspeichers B-SP ist der Minuend in Form der Basisadresse «0» für alle Subtrahierer gleich, so dass sich für alle Bytespalten gleiche Zeilenadressen Z-AD(BSP ... ) ergeben. Bei der anderen Betriebsart wird dieZeilenadresse Z-AD jeweils von einer der möglichen Basisadressen abgezogen, so dass sich vier unterschiedliche Zeilenadressen Z-AD(BSPO) bis Z-AD(Bsp3) entsprechend der Modulo-4-Verschiebung ergeben. Mit fortlaufender Zeilenadresse Z-AD im Feld verschiebt sich also der Beginn der Dateneinheit in zyklischer Folge um jeweils eine Bytebreite, wie in Figur 1 anhand des Feldes FO gezeigt ist. Anstelle der Subtrahierer können in an sich bekannter Weise auch Addierer verwendet werden.FIG. 3 shows in the form of a block diagram an address reorder AD-UM, as can be used in FIG. 2. This address reorderer consists of 4 modulo-4 working 2-bit subtractors SUB1 to SUB4, to which the output line address Z-AD is supplied as a subtrahend. The Minuend consists of one of the four possible base addresses «0», «1», «2» or «3», the activation of which is controlled by the M UX multiplexer in accordance with the two mode types MOD. In normal operation of the base memory B-SP, the minuend in the form of the base address “0” is the same for all subtractors, so that the same row addresses Z-AD (BSP ...) result for all byte columns. In the other operating mode, the row address Z-AD is subtracted from one of the possible base addresses, so that there are four different row addresses Z-AD (BSPO) to Z-AD (Ex. 3) corresponding to the modulo 4 shift. With a continuous row address Z-AD in the field, the start of the data unit is shifted in cyclical order by one byte width, as shown in FIG. 1 with the field FO. Instead of the subtractors, adders can also be used in a manner known per se.

Figur 4 zeigt ein zweites Ausführungsbeispiel für den Adressenumordner AD-UM in Figur 2 mit einem vierstufigen Schieberegister S-REG, das in jeder Stufe im Rang steigend eine der üblichen 4 Basisadressen «0», «1 », «2», und «3» gespeichert enthält. Abhängig von der Ausgangszeilenadresse Z-AD und dem Betriebsmodus MOD wird über den Auswahlschalter DEMUX die Zeilenadresse Z-AD entweder direkt allen 4 ODER-Gliedern OD zugeleitet, wenn dieselbe Zeile in allen Bytespalten anzusteuern ist, oder aber es wird entsprechend dem Wert der Zeilenadresse Z-AD über die Verschiebesteuerung Z der Inhalt des Schieberegisters S-REG jeweils von der Ausgangsstellung aus zyklisch in der einen oder anderen Richtung verschoben und die Ausgänge des Schieberegisters über die Torschaltung TS freigegeben.FIG. 4 shows a second exemplary embodiment of the address reorder AD-UM in FIG. 2 with a four-stage shift register S-REG, which ranks one of the usual 4 base addresses “0”, “1”, “2” and “3” in each stage »Saved contains. Depending on the output row address Z-AD and the operating mode MOD, the row address Z-AD is either fed directly to all 4 OR gates OD via the selection switch DEMUX if the same row is to be controlled in all byte columns, or else it is corresponding to the value of the row address Z -AD via the shift control Z, the content of the shift register S-REG is cyclically shifted in one direction or the other from the starting position and the outputs of the shift register are released via the gate circuit TS.

Ein drittes Ausführungsbeispiel für den Adressenumordner AD-UM in Figur 2 zeigt schliesslich Figur 5. Gegenüber dem von Figur 4 ist das Schieberegister S-REG durch 4 Auswahlschalter MUX mit jeweils 4 Eingangsgruppen für die 4 verschiedenen Basisadressen «0», «1 », «2» und «3» ersetzt. Unabhängig von der wirksamen Ausgangszeilenadresse Z-AD wird in jedem der Auswahlschalter MUX eine der 4 Basisadressen zum Ausgang durchgeschaltet, wobei die Zuordnung der Basisadressen dem jeweiligen Einordnungsschema entsprechend gewählt ist.Finally, FIG. 5 shows a third exemplary embodiment of the address reorder AD-UM in FIG. 5. Compared to that of FIG. 4, the shift register S-REG is provided by 4 selection switches MUX, each with 4 input groups for the 4 different base addresses “0”, “1”, “ 2 »and« 3 »replaced. Regardless of the effective output line address Z-AD, one of the 4 base addresses is switched through to the output in each of the selection switches MUX, the assignment of the base addresses being selected in accordance with the respective classification scheme.

Bei allen drei erläuterten Ausführungsformen des Adressenumordners AD-UM handelt es sich um Prinzipschaltbilder, bei denen mit Ausnahme des Betriebsartensignales MOD alle Steuerwege im vorliegenden Fall jeweils zwei Adern zur Darstellung von zweistelligen Binärzahlen umfassen. Bei Verwendung von Dateneinheiten in Form von Doppelwörtern mit 8 Byte und entsprechend 8 Zeilen im Feld würden die Steuerwege aus 3 Adern bestehen, die jeweils durchzuschalten sind.All three explained embodiments of the address folder AD-UM are block diagrams in which, with the exception of the operating mode signal MOD, all control paths in the present case each comprise two wires for representing two-digit binary numbers. When using data units in the form of double words with 8 bytes and corresponding 8 lines in the field, the control paths would consist of 3 wires, each of which must be switched through.

Das dem Feld Fn des Basisspeichers B-SP in Figur 1 zugrundegelegte Einordnungsschema arbeitet im Vergleich zu dem des Feldes FO nach dem umgekehrten Prinzip, d.h. die im Normalbetrieb jeweils eine Dateneinheit bildenden Bytes, z.B. AnO, An1, An2 und An3, sind jeweils in der Diagonale angeordnet, während die miteinander korrespondierenden Bytes, z.B. AnO, BnO, Cn0 und DnO, jeweils in einer Ebene liegen. Es können daher die anhand von Figur 3 bis Figur 5 erläuterten Adressenumordner Ad-UM in gleicher Weise für dieses Umordnungsschema verwendet werden, nur sind die Betriebsmodussignale MOD entsprechend zu vertauschen.The classification scheme on which the field Fn of the base memory B-SP in FIG. 1 is based works in comparison to that of the field FO according to the opposite principle, i.e. the bytes forming a data unit in normal operation, e.g. AnO, An1, An2 and An3 are each arranged in the diagonal, while the corresponding bytes, e.g. AnO, BnO, Cn0 and DnO, each lie in one plane. The address reorderers Ad-UM explained with reference to FIG. 3 to FIG. 5 can therefore be used in the same way for this reordering scheme, only the operating mode signals MOD must be interchanged accordingly.

Aus der Sicht des Benutzers bedeutet die Wahl zwischen den beiden Einordnungsschemen für den Basisspeicher B-SP keinen Unterschied. Beide Einordnungsschemen bewirken aber bei konstantem Zeilenadressenteil und schrittweise fortgeschaltetem Feldadressenteil der Zugriffsadresse AD die Bildung von Strings zusammengehöriger Dateneinheiten, z.B. AOi bisAni, mitserieller Folge der einzelnen Bytes entlang der vertikalen Zugriffsrichtung für den Basisspeicher, wobei entsprechend der Anzahl der Bytes in einer Datenebene im vorliegenden Fall vier parallele Datenstrings, nämlich AOi bis Ani, BOi bis Bni, COi bis Cni und DOi bis Dni, gebildet werden können. Dies wird besonders deutlich beim Einordnungsschema für das Feld Fn in Figur 1, wenn man die erste Zeile dieses Feldes als Ausgangspunkt nimmt und dasselbe Einordnungsschema auch dem Feld FO zugrundeliegt. Eine solche Stringbildung eröffnet verschiedene Möglichkeiten der Einordnung von aus vielen Dateneinheiten zusammengesetzten Dateien in den Basis- speicher, nämlich die Bildung einer Datei durch einen einzigen solchen String, so dass im vorliegenden Fall vier verschiedene Dateien gleichzeitig durch die assoziative Oberfläche ASS-FL überprüft werden können, oder aber die Verteilung einer Datei auf die parallelen Strings durch Serienschaltung der parallelen Strings in einem vorgegebenen Speicherbereich des Basisspeichers, so dass Teile der Datei parallel und damit die Datei als solche schneller überprüft werden kann.From the user's point of view, the choice between the two classification schemes for the B-SP basic storage means no difference. With a constant row address part and step-by-step field address part of the access address AD, both classification schemes result in the formation of strings of related data units, e.g. AOi to Ani, with a serial sequence of the individual bytes along the vertical access direction for the basic memory, whereby four parallel data strings, namely AOi to Ani, BOi to Bni, COi to Cni and DOi to Dni, are formed in accordance with the number of bytes in a data level in the present case can be. This becomes particularly clear in the classification scheme for the field Fn in FIG. 1, if one takes the first line of this field as the starting point and the same classification scheme is also used for the field FO. Such string formation opens up various possibilities for the classification of files composed of many data units in the basic memory, namely the formation of a file by means of a single such string, so that in the present case four different files can be checked simultaneously by the associative surface ASS-FL , or the distribution of a file to the parallel strings by connecting the parallel strings in series in a predetermined memory area of the base memory, so that parts of the file can be checked in parallel and thus the file as such can be checked more quickly.

Wie die Einordnungsschemen der Felder FO und Fn in Figur 1 erkennen lassen, ist jeweils nur für die erste Zeile eines jeden Feldes die ordnungsgemässe Bytefolge, z.B. AOO, A01, A02, A03 bzw. AnO, BnO, CnO, DnO, eingehalten. In den übrigen Zeilen eines jeden Feldes wird jedoch davon abgewichen. Um dennoch auch für diese Zeilen im Feld die ordnungsgemässe Bytereihenfolge sicherzustellen, werden die Dateneinheiten sowohl bei der Einspeicherung als auch bei der Ausspeicherung über Umordnungseinrichtungen D-UM-EG bzw. D-UM-AG geleitet und durch eine von der Zeilenadresse Z-AD abhängige zyklische Verschiebung der jeweiligen Byteserie die jeweils benötigte Reihenfolge hergestellt. Die Datenumordner können in ähnlicher Weise aufgebaut sein wie die Adressenumordner von Figur 4 oder besser Figur 5, jedoch mit dem Unterschied, dass an die Stelle der Basisadressen die einzuschreibenden bzw. gelesenen Bytes treten und die Steuerung durch die Betriebsart MOD entfällt. Weiterhin ist zu berücksichtigen, dass eine bei der Eingabe in der einen Richtung vorgenommene zyklische Verschiebung bei der Ausgabe durch eine in entgegengesetzter Richtung vorzunehmende Verschiebung kompensiert werden muss.As can be seen from the classification schemes of fields FO and Fn in FIG. 1, the correct byte sequence, e.g. AOO, A01, A02, A03 or AnO, BnO, CnO, DnO. However, there are deviations in the remaining lines of each field. In order to ensure the correct byte order for these lines in the field as well, the data units are routed via reordering devices D-UM-EG or D-UM-AG both during the storage and the retrieval and through one dependent on the row address Z-AD cyclical shifting of the respective byte series creates the required sequence. The data reorderers can be constructed in a similar manner to the address reorderers in FIG. 4 or better in FIG. 5, but with the difference that the bytes to be written or read take the place of the base addresses and the control by the operating mode MOD is omitted. Furthermore, it must be taken into account that a cyclical shift made in the input in one direction must be compensated for in the output by a shift to be carried out in the opposite direction.

Beim Betrieb des Basisspeichers B-SP gemäss Figur 1 werden alle Dateneinheiten vom Eingabeleitungssystem D-EG zunächst über einen Datenumordner D-UM-EG geleitet, der abhängig von der anstehenden Zeilenadresse Z-AD die benötigte Bytefolge entsprechend dem gewählten Einordnungsschema herstellt. Die so bereitgestellte Bytefolge wird dann in das angesteuerte Feld F ... im Basisspeicher B-SP unter Mitwirkung des Adressenumordners AD-UM in der Adressensteuerung AD-ST eingespeichert. Beim Auslesen aus dem Basisspeicher wird die Dateneinheit ebenfalls über einen Datenumordner D-UM-AG geleitet und die benötigte Bytefolge hergestellt. Erst dann erfolgt die Weiterleitung der gelesenen Dateneinheiten, und zwar bei normalem Speicherbetrieb an das Ausgabeleitungssystem D-AG und beim assoziativen Betrieb an die assoziative Oberfläche ASS-FL, wie es durch die Ausgabewegesteuerung WS-AG anhand des Steuersignales AG vorgegeben wird.When operating the basic memory B-SP according to FIG. 1, all data units are first routed from the input line system D-EG via a data reorder D-UM-EG, which, depending on the line address Z-AD, produces the required byte sequence in accordance with the selected classification scheme. The byte sequence provided in this way is then stored in the controlled field F ... in the base memory B-SP with the participation of the address folder AD-UM in the address control AD-ST. When reading from the basic memory, the data unit is also routed via a data reorder D-UM-AG and the required byte sequence is established. Only then is the data units read forwarded, namely during normal memory operation to the output line system D-AG and during associative operation to the associative surface ASS-FL, as is specified by the WS-AG output route control on the basis of the control signal AG.

Anstelle von getrennten Datenumordnern für die Ein- und Ausgabe, wie in Figur 1 dargestellt, kann auch ein einziger Datenumordner D-UM vorgesehen sein, wie Figur 6 zeigt. Durch Wegeschalter DEMUX und MUX sind dann die Datenflusswege abhängig von Steuersignalen EG/AG für die Eingabe oder die Ausgabe so umzuschalten, dass diese immer über den Datenumordner D-UM führen. Ebenso muss die Verschieberichtung des Datenumordners anhand des Ein/Ausgabesteuersignals EG/AG vorgegeben werden, damit der Datenumordner richtig arbeiten kann.Instead of separate data folders for input and output, as shown in FIG. 1, a single data folder D-UM can also be provided, as shown in FIG. With the DEMUX and MUX path switches, the data flow paths must be switched depending on the EG / AG control signals for input or output so that they always lead via the D-UM data reorderer. Likewise, the direction of movement of the data folder must be specified based on the input / output control signal EG / AG so that the data folder can work properly.

Bei einem Basisspeicher B-SP der in Figur 1 gezeigten Art können unabhängig vom normalen oder assoziativen Speicherbetrieb die gleichen Datenumordner D-UM verwendet werden. Es können aber auch getrennte Datenumordner für den assoziativen Betrieb vorgesehen werden, was in Figur 6 mit dem gestrichelten Datenflusspfeil zur assoziativen Oberfläche ASS-FL am Ausgang des Basisspeichers B-SP angedeutet ist. Hierauf wird später noch eingegangen werden.In the case of a basic memory B-SP of the type shown in FIG. 1, the same data reorder D-UM can be used, regardless of the normal or associative memory operation. However, separate data reorderers can also be provided for associative operation, which is indicated in FIG. 6 by the dashed data flow arrow to the associative surface ASS-FL at the output of the base memory B-SP. This will be discussed later.

Für viele Anwendungsfälle kann die Verarbeitungsleistung des Hybrid-Assoziativspeichers merklich gesteigert werden, wenn mit der Adressensteuerung AD-ST eine Adressenmaskierung verbunden ist, so dass z.B. bei einem Suchlauf nicht der gesamte Basisspeicher in vertikaler Richtung überprüft wird, sondern nur ein ausgewählter Bereich und/oder dass in dem ausgewählten Bereich nicht jede Dateneinheitsebene, sondern in jedem Feld nur bestimmte Dateneinheitsebenen angesteuert werden. Dadurch kann der Datenfluss zur assoziativen Oberfläche ASS-FL in vielen Fällen gezielt auf die Daten beschränkt werden, die für den assoziativen Prüfvorgang benötigt werden, so dass eine Überprüfung vielfach wesentlich schneller ausgeführt werden kann.For many applications, the processing power of the hybrid associative memory can be increased significantly if an address mask is connected to the address control AD-ST, so that, for example, the entire basic memory is not checked in the vertical direction during a search, but only a selected area and / or that not every data unit level, but only certain data unit levels are controlled in each field in the selected area. This can the data flow to the associative interface ASS-FL is in many cases specifically limited to the data that is required for the associative checking process, so that a check can be carried out much faster in many cases.

Eine derartige Adressenmaskiersteuerung ist in Figur 7 gezeigt. Sie besteht im wesentlichen aus einem codiert arbeitenden Adressenzähler AD-Z zur Kennzeichnung eines Speicherbereiches im Basispeicher B-SP anhand des Adressenteils AD1 und einem Maskenregister M-REG mit jeweils einer Bitstelle je Datenzeile in dem durch den Adressenteil AD1 festgelegten Speicherbereich. Die Ausgänge des Maskenregisters M-REG werden mit einer Prioritätsschaltung PRIO überwacht, die für jeden markierten Eingang nacheinander- getaktet durch den Speicherzyklustakt T Sp - die zugehörige codierte Teiladresse AD2 liefert, die zusammen mit der Teiladresse AD1 die jeweilige Zugriffsadresse AD bildet. Entsprechend der Voreinstellung des Maskenregisters M-REG können also in dem ausgewählten Speicherbereich des Basisspeichers die einzelnen Datenzeilen in beliebiger Kombination aufeinanderfolgend angesteuert bzw. Datenzeilen in beliebiger Kombination von der Ansteuerung ausgenommen werden. Die Voreinstellung vom Adressenzähler AD-Z und dem Maskenregister M-REG erfolgt aus einem Adressenspeicher AD-SP, der bei Ansteuerung mit dem Signal lad nach Erkennung des letzten markierten Registerausganges durch die Prioritätsschaltung PRIO den jeweils nächsten Adresseneintrag in Form derTeiladresse AD1 und der Zeilenmaske Z-MASK zur Verfügung stellt.Such an address masking control is shown in FIG. 7. It essentially consists of an encoded address counter AD-Z for identifying a memory area in the basic memory B-SP based on the address part AD1 and a mask register M-REG with one bit position per data line in the memory area defined by the address part AD1. The outputs of the mask register M-REG are monitored with a priority circuit PRIO, which delivers the associated coded partial address AD2, which forms the respective access address AD together with the partial address AD1, for each marked input sequentially clocked by the memory cycle clock T Sp. Corresponding to the default setting of the mask register M-REG, the individual data lines in the selected memory area of the base memory can thus be controlled successively in any combination or data lines in any combination can be excluded from the control. The address counter AD-Z and the mask register M-REG are preset from an address memory AD-SP which, when activated with the signal lad after recognition of the last marked register output by the priority circuit PRIO, the next address entry in the form of the partial address AD1 and the line mask Z -MASK provides.

Die Breite der Zeilenmaske Z-MASK wird zweckmässig so gewählt, dass für den überwiegenden Teil der Anwendungsfälle ein optimales Verhältnis zwischen Speicheraufwand einerseits und Steuerungs- bzw. Zeitaufwand andererseits gegeben ist. Gegebenenfalls kann auch mit veränderbaren Feldlängen für den Adressenteil AD1 und den Maskenteil Z-MASK gearbeitet werden.The width of the line mask Z-MASK is expediently chosen in such a way that for the majority of the application cases there is an optimal relationship between the amount of memory on the one hand and the control or time required on the other. If necessary, you can also work with variable field lengths for the address part AD1 and the mask part Z-MASK.

Figur 8 zeigt die Erweiterung des Basisspeichers B-SP von Figur 1 mit einer einzigen Speichergruppe auf beispielsweise 16 Speichergruppen MDO bis MD15, die hintereinander in Form eines dreidimensionalen Speichers oder nebeneinander in Form eines zweidimensionalen Speichers angeordnet sein können und jeweils getrennt ansteuerbar sind. Die Feld- und Zeilenauswahl erfolgt dagegen in den einzelnen Speichergruppen parallel, so dass sich - wie gezeigt - der Aufwand für den Adressenumordner AD-UM nicht erhöht. Gleiches gilt für die nicht gezeigten Datenumordner, wenn für den assoziativen Betrieb gesonderte Umordner vorgesehen werden, da beim normalen Speicherbetrieb immer nur eine Dateneinheit eingeschrieben oder gelesen wird.FIG. 8 shows the expansion of the basic memory B-SP from FIG. 1 with a single memory group to, for example, 16 memory groups MDO to MD15, which can be arranged one behind the other in the form of a three-dimensional memory or next to one another in the form of a two-dimensional memory and can each be controlled separately. The field and row selection, however, takes place in parallel in the individual storage groups, so that - as shown - the effort for the address reorder AD-UM does not increase. The same applies to the data reorderers, not shown, if separate reorderers are provided for associative operation, since only one data unit is ever written or read during normal storage operation.

Für den assoziativen Betrieb wird dagegen für jede Speichergruppe ein gesonderter Datenumordner benötigt, wenn zur Steigerung der Leistungsfähigkeit des Hybrid-Assoziativspeichers jeweils eine vollständige Byteschicht oder Byteebene BS gleichzeitig zu einer entsprechend grossen assoziativen Oberfläche ASS-FL durchgeschaltet wird. Der Aufwand für die Datenordner lässt sich allerdings verringern, wenn man statt der Datenbytes erst die zugehörigen Trefferausgänge am Ausgang der assoziativen Oberfläche ASS-FL umordnet. Da jede Verknüpfungseinheit ALV ... der assoziativen Oberfläche ASS-FL nur einen Trefferausgang aufweist, verringert sich dann der Gesamtaufwand im Vergleich zu Bytes mit je 8 Bit auf ein Achtel.For associative operation, however, a separate data reordering is required for each storage group if, in order to increase the performance of the hybrid associative memory, a complete byte layer or byte level BS is simultaneously switched through to a correspondingly large associative surface ASS-FL. However, the effort for the data folder can be reduced if instead of the data bytes, the associated hit outputs at the output of the associative ASS-FL interface are rearranged. Since each link unit ALV ... of the associative surface ASS-FL has only one hit output, the total effort is then reduced to one eighth in comparison to bytes with 8 bits each.

Ein gemäss Figur 8 ausgebildeter Basisspeicher B-SP ist auch für ein Laden und Entladen im Streamingbetrieb besonders geeignet, wenn die Daten so aufbereitet werden, dass Dateneinheiten nacheinander in getrennte Speichergruppen eingetragen werden können. Diese Aufbereitung erfolgt durch einen vorgeschalteten Pufferspeicher.A base memory B-SP designed according to FIG. 8 is also particularly suitable for loading and unloading in streaming mode if the data are processed in such a way that data units can be entered one after the other in separate memory groups. This preparation is done by an upstream buffer memory.

Figur 9 zeigt eine entsprechende Prinzipschaltung. Der Einfachheit halber sind dabei für den Basisspeicher B-SP nur vier Speichergruppen MDO bis MD3 vorgesehen und nur ein Feld Fn dargestellt, so dass sich insgesamt 16 vertikale Strings A bis P zu je 4 Byte entsprechend 16 Dateneinheiten ergeben.Figure 9 shows a corresponding basic circuit. For the sake of simplicity, only four memory groups MDO to MD3 are provided for the base memory B-SP and only one field Fn is shown, so that a total of 16 vertical strings A to P of 4 bytes each correspond to 16 data units.

Im Pufferspeicher P-SP ist je Speichergruppe MDO bis MD3 im Basisspeicher B-SP ein Einzelspeicher, insgesamt also die vier Einzelspeicher E-SP1 bis E-SP4 vorgesehen. Jeder Einzeispeicher E-SP ... weist eine Kapazität entsprechend der Anzahl von Strings oder Dateneinheiten je Speichergruppe MD ... auf. Diese Einzelspeicher werden von der Peripherie PE aus fortlaufend nacheinander über den Auswahlschalter MUX1 geladen, wobei die Zeilenadresse Z-AD der Einzelspeicher identisch ist mit der des Basispeichers B-SP.In the buffer memory P-SP there is one individual memory for each storage group MDO to MD3 in the basic memory B-SP, that is to say the four individual memories E-SP1 to E-SP4 in total. Each single memory E-SP ... has a capacity corresponding to the number of strings or data units per storage group MD ... These individual memories are loaded continuously one after the other from the periphery PE via the selection switch MUX1, the row address Z-AD of the individual memories being identical to that of the basic memory B-SP.

Sobald der Pufferspeicher P-SP voll ist, werden die jeweils durch dieselbe Zeilenadresse Z-AD gekennzeichneten Dateneinheiten nacheinander aus allen Einzelspeichern E-SP1 bis E-SP4 an die zugehörigen Speichergruppen MDO bis MD3 des Basisspeichers B-SP weitergeleitet. Es sind dies also für die erste Zeile aller Einzelspeicher E-SP1 bis E-SP4 die Dateneinheiten A, E, I und M, die mit der gleichen Zeilenadresseinstellung im Basisspeicher B-SP eingespeichert werden. Entsprechend werden bei einer Ausgabe aus dem Basisspeicher B-SP zuerst die einzelnen Dateneinheiten, z.B. A, E, 1, M nacheinander in die miteinander korrespondierenden Speicherabschnitte der Einzelspeicher E-SP1 bis E-SP4 eingeschrieben, und das fortschreitend von Zeile zu Zeile, bis der Pufferspeicher P-SP gefüllt ist. Bei der Weiterleitung der im Pufferspeicher P-SP gespeicherten Daten an die Peripherie PE werden dann die Einzelspeicher, z.B. E-SP1, vor der Weiterschaltung auf den jeweils folgenden Einzelspeicher, z.B. E-SP2, jeweils ganz geleert.As soon as the buffer memory P-SP is full, the data units identified by the same row address Z-AD are successively forwarded from all individual memories E-SP1 to E-SP4 to the associated memory groups MDO to MD3 of the base memory B-SP. These are therefore the data units A, E, I and M for the first line of all individual memories E-SP1 to E-SP4, which are stored in the base memory B-SP with the same line address setting. Accordingly, when outputting from the base memory B-SP, the individual data units, e.g. A, E, 1, M are successively written into the corresponding memory sections of the individual memories E-SP1 to E-SP4, and progressively from line to line until the buffer memory P-SP is filled. When the data stored in the buffer memory P-SP is forwarded to the peripheral PE, the individual memories, e.g. E-SP1, before switching to the following individual memory, e.g. E-SP2, each completely empty.

Anstelle von Einzelspeichern können Speicherbereiche eines einheitlichen Speichers verwendet werden. Ebenso können die einzelnen Speicherabschnitte, z.B. für die Dateneinheit A, durch eine der jeweiligen Stringlänge entsprechende Anzahl von untereinander liegenden Speicherabschnitten ersetzt werden, so dass aufeinanderfolgend zum Beispiel 16 Datenwörter AOi bis A15i als, String mit 64 Byte und in gleicher Anordnung die Strings A bis P nacheinander gespeichert werden können.Instead of individual memories, memory areas of a uniform memory can be used. Likewise, the individual memory sections, for example for data unit A, can be replaced by a number of memory sections lying one below the other corresponding to the respective string length ten are replaced so that, for example, 16 data words AOi to A15i can be stored in succession as a string with 64 bytes and in the same arrangement, the strings A to P can be stored one after the other.

Im Streamingverfahren können so ganze Feldschichten des Basisspeichers B-SP ausgetauscht werden. Voraussetzung ist dabei nur, dass der Pufferspeicher P-SP eine der Streaminggeschwindigkeit angepasste Arbeitsgeschwindigkeit aufweist, da der Basisspeicher B-SP langsamer als der Pufferspeicher P-SP arbeiten kann. Dabei kann es zweckmässig sein, dass anstelle des gezeigten einen Pufferspeichers P-SP zwei Pufferspeicher vorgesehen werden, die in an sich bekannter Weise im Wechselbetrieb arbeiten.Whole field layers of the B-SP basic storage can be exchanged in the streaming process. The only requirement is that the buffer memory P-SP has a working speed adapted to the streaming speed, since the basic memory B-SP can work slower than the buffer memory P-SP. In this case, it may be expedient that instead of the one buffer memory P-SP shown, two buffer memories are provided which operate in alternating operation in a manner known per se.

Insgesamt ermöglicht die Erfindung einen sehr leistungsfähigen und an verschiedene Betriebsfälle leicht anpassbaren Hybrid-Assoziativspeicher, wobei die universellen Verknüpfungselemente ALV ... der assoziativen Oberfläche ASS-FL und die Trefferauswerteeinrichtung T-AUSW in Anlehnung an die aus der eingangs bereits genannten DE-OS 3216905 bekannten Anordnung ausgebildet sein können.Overall, the invention enables a very powerful hybrid associative memory that can be easily adapted to different operating cases, the universal linking elements ALV ... of the associative surface ASS-FL and the hit evaluation device T-AUSW based on the DE-OS 3216905 already mentioned at the beginning known arrangement can be formed.

Claims (17)

1. A hybrid associative store, comprising a non- associative base store (B-SP) with write- and read devices for the selected input and output of data units via an input/output transmission system (DEG/D-AG) which corresponds to the length of the data units and comprising an associative area (ASS-FL) for testing the data units supplied from the base store (B-SP), characterised in that
- each data unit (e.g. AO) is sub-divided into a given number (e.g. 4) of sub-units (e.g. bytes AOO to A03), each of which comprises a plurality of bits (e.g. 8 bits),
-that the base store (B-SP) is sub-divided into arrays (e.g. FO to Fn), each of which can be activated by an array address (e.g. F-ADO) of an address control unit (AD-ST) and each of which is formed by a number of data unit store sections - corresponding to the number of sub-units per data unit- in various data unit levels, where a row address (Z-AD), which supplements the respective array address (F-AD) to form a standard access address (AD), specifies the respective data unit store section within the respective array,
- that in dependence upon an address reclassifier (AD-UM), which analyses the row address (Z-AD), in the address control unit (AD-ST). the sub-unit store sections within the array (FO), which correspond to the sub-units of the data units (e.g. A0, BO, C0 and DO) which each form an array (e.g. FO), are separated and can be activated, distributed in accordance with a given classification plan, in such manner that the mutually-corresponding sub-units (e.g. AOO, BOO, COO and DOO) of all the data units (AO to DO) of the array (FO) can each be stored in different sub-unit store sections of the individual data unit levels and, in dependence upon the selected operating mode (MOD), either the purposive, simultaneous selection of the sub-units (e.g. AOO, A01, A02 and A03) which form a data unit is possible in the case of normal store operation or the purposive, simultaneous selection of the mutually corresponding sub-units (e.g. AOO, BOO, COO and DOO) of all the data units of an array (FO) is possible in the case of associative store operation,
- that in the address control unit (AD-ST), not only the access address (AD) but also the array address (F-AD), when the row address (ZAD) is constant, can be changed in stepped fashion so that consecutive data units (e.g. AO to An) which are directly linked on the basis of the selected classification plan can each be allocated to the data unit levels, specified by the constant row address (Z-AD), f consecutive arrays (FO to Fn),
- that in dependence upon reclassification devices (D-UM-EG, D-UM-AG) which likewise analyse the row address (Z-AD), the sub-units of the group of sub-units which is to be input or output, corresponding to a data unit, can be regrouped in accordance with the selected classic fication plan for the arrays (e.g. FO to Fn) prior to input or prior to output in order to ensure the necessary storage sequence during input and in order to ensure the original sequence following output and
- that in respect of each sub-unit, the associative area (ASS-FL) is assigned a universal logic-linking unit (e.g. ALV1 to ALV4) which carries out parallel processing of the bits of the supplied sub-unit and whose result outputs are coupled to the associated hit analysis control unit (T-AUSW.).
2. A hybrid associative store as claimed in claim 1, characterised in that the classification of the data units (e.g. AOi-DOi) in the array (e.g. FO) which they form is carried out in that the sub-units (e.g. AOO, A01, A02, A03), which in each case form a data unit, are all arranged in one data unit level and the corresponding sub-units (e.g. AOO, BOO, COO, DOO) of each data unit are arranged so as to be cyclically offset by one sub-unit section from data unit level to data unit level.
3. A hybrid associative store as claimed in claim 1, characterised in that the classification of the data units (e.g. Ani-Dni) in the array (e.g. Fn) which they form is carried out in that the mutually-corresponding sub-units (e.g. AnO, BnO, CnO, Dn0) of all the data units of the array are arranged in one data unit level and the corresponding sub-units (e.g. AnO, An1, An2, An3) of each data unit are arranged so as to be cyclically offset by one sub-unit section from data unit level to data unit level.
4. A hybrid associative store as claimed in one of the claims 1-3, characterised in that for the selection of the individual sub-unit sections in the selected array (e.g. FO), a common address reclassifier (AD-UM) is provided, which can be controlled by the address (Z-AD) which identifies the governing data unit level, which itself controls the vertical offset in the array, and which as address generator for each sub-unit section column (e.g. BSFO to BSF3) supplies a special drive address (e.g. Z-AD(BSPO) ) in order to select a sub-unit section in each data unit level, so that for the simultaneous selection of the sub-unit sections which in each case form a desired data unit, as in a conventional store, only the row address (Z-AD) which identifies the governing data level within the relevant array (e.g. FO) is required.
5. A hybrid associative store as claimed in claim 4, characterised in that the addresse reclassifier (AD-UM) can be switched over in dependence upon the operating mode (MOD), and in dependence upon the selected operating mode (MOD) and the selected classification plan for the data units either supplies uniform drive addresses (e.g.Z-AD(BSPO) ) for the selection of sub-units of the same data level or supplies different drive addresses (Z-AD(BSP) to Z-AD(BSP3) ) for the selection of vertically offset sub-units.
6. A hybrid associative store as claimed in one of the claims 1 to 5, characterised in that for the reclassification of the sub-units (e.g. C02, C03, COO and C01) within the data units (e.g. COi) which are to be input or output, one single reclassification device (D-UM) is provided which, in dependence upon the direction (e.g. AG) of the data flow, is interposed into the respective data flow path via change-over switches (MUX, DEMUX).
7. A hybrid associative store as claimed in one of the claims 1 to 5 or claim 6, characterised in that separate reclassification devices are provided for normal store operation and for associative store operation.
8. A hybrid associative store as claimed in claim 7, characterised in that the data units which, in the case of associative store operation, are read out from the base store (B-SP) are directly supplied to the associative area (ASS-FL) and that only those results determined by the individual logic-linking units (e.g. ALV1 to ALV4) are reclassified.
9. A hybrid associative store as claimed in one of the claims 1 to 5 or claim 6, characterised in that common reclassification devices (e.g. D-UM) are provided for normal store operation and for associative store operation.
10. A hybrid associative store as claimed in one of the claims 6 to 9, characterised in that the reclassification device (D-UM) comprises a number of distributor switches, which corresponds to the number (e.g. 4) of sub-units per data unit, with a number of output groups - corresponding to the number of sub-units - which forward the sub-units and logic-linking results occurring at the input to the output group in each case identified by the row address for the governing data unit level, where the mutually corresponding output groups are combined via OR-gates.
11. A hybrid associative store as claimed in one of the claims 1 to 10, characterised in that the devices (AD-ST) which serve to select the individual data units in the base store (B-SP) cooperate with a masking control unit (AD-MASK) which specifies the data units which are to be activated consecutively during associative hunting procedures in the desired combination.
12. A hybrid associative store as claimed in claim 11, characterised in that the masking control unit (AD-MASK) comprises a preset address counter (AD-Z) which identifies the start of a selected stores zone in the base store (B-SP) and of a preset mask register (M-REG), containing one bit location in respect of each store row, that the outputs of the mask register (M-REG) are monitored by a priority circuit (PRIO) which, with each store cycle clock signal (Tsp), in a continuous sequence supplies, in coded form, the subsidiary address (AD2) which is assigned to the respective, analysed input and which, together with the subsidiary address (AD1) made available by the address counter (AD-Z), forms the respective drive address (AD), and that when all the outputs of the mask register (MR EG) have been checked by the priority circuit (PRIO), the address counter (AD-Z) and the mask register (M-REG) are reloaded from an address store (AD-SP).
13. A hybrid associative store as claimed in one of the claims 1 to 12, characterised in that the base store (BSP) comprises a plurality of store groups (e.g. MDO to MD15) which each accommodate a vertical column of data units, where the mutually corresponding store sections for the individual sub-units (e.g. AOO, A01, A02, A03) of the data units (e.g. AOi) can be selected in the same way in all the store groups (M DO to MD15) and data units and identified by the same array address and row address (F-AD/ZAD) in the various store groups (MDO to MD15) can be selected by a superordinate store group address component (MD-AD), and that in the case of associative operation, by simultaneously activating all the store groups (DO to MD15), a corresponding number of data units can be simultaneously switched through to the associative area.
14. A hybrid associative store as claimed in claim 13, characterised in that only in the case of associative operation, in respect of each store group (e.g. MDO to MD15), a separate reclassification device is provided for the data and all the reclassification devices operate in parallel.
15. A hybrid associative store as claimed in claim 14, characterised in that the reclassification devices are arranged at the output of the associative area (ASS-FL) and that in place of the sub-units from the base store (B-SP), the hit displays in respect of each logic-linking unit (ALV...) are reclassified whereby the sequence to be adhered to in respect of each data unit is re-established.
16. A hybrid associative store as claimed in claims 13, 14 or 15, characterised in that in order to load and unload the base store (B-SP) by the streaming method, a buffer store (P-SP) is provided which comprises a number of individual stores (e.g. E-SP1 to E-SP4), corresponding to the number of store groups (e.g. MDO to MD3) in the base store (B-SP), where said individual stores are permanently allocated to the store groups (MDO to MD3) in the base store (B-SP) and each thereof receives from or emits to the peripheral (PE) a number (e.g. 4) of data units (e.g. A, B, C, D), corresponding to the number of data units which form an array (e.g. Fn), and where the individual stores (ES-P1 to E-SP4) are loaded or unloaded consecutively, that in traffic with the base store (B-SP), where an identical array address and row address are set up for the base store, the data units (e.g. A, E, I, M) which correspond to one another in the individual stores (E-SP1 to E-SP4) of the buffer store (P-SP) are each fed consecutively to the associated store group (MD ...) of the base store (B-SP) or are consecutively read out from the individual store groups (MDO to MD3) and input consecutively into the associated individual stores (E-SP1 to E-SP4) of the buffer store (P-SP) so that when data transfer takes place between the base store (B-SP) and the buffer store (P-SP) the data units are exchanged for a complete array level (Fn) of the base store (B-SP).
17. A hybrid associative store as claimed in claim 16, characterised in that two buffer stores are provided which operate in alternation.
EP84103500A 1983-03-30 1984-03-29 Hybrid-associative memory comprising a non associative base memory and an associative surface Expired EP0123169B1 (en)

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AT84103500T ATE28005T1 (en) 1983-03-30 1984-03-29 HYBRID ASSOCIATIVE MEMORY, CONSISTING OF A NON-ASSOCIATIVE BASIC MEMORY AND AN ASSOCIATIVE INTERFACE.

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DE3311665 1983-03-30
DE19833311665 DE3311665A1 (en) 1983-03-30 1983-03-30 HYBRID-ASSOCIATIVE MEMORY, CONSISTS OF A NON-ASSOCIATIVE BASE MEMORY AND AN ASSOCIATIVE SURFACE

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EP0123169A1 EP0123169A1 (en) 1984-10-31
EP0123169B1 true EP0123169B1 (en) 1987-06-24

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DE3827172A1 (en) * 1987-08-13 1989-03-16 Peter Elsner MESSAGE IDENTIFICATION DEVICE
EP0859366A1 (en) * 1997-02-12 1998-08-19 STMicroelectronics S.r.l. Associative memory device with optimized occupation, particularly for the recognition of words

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US4257110A (en) * 1977-04-19 1981-03-17 Semionics Associates, Inc. Recognition memory with multiwrite and masking
IT1084325B (en) * 1977-06-30 1985-05-25 Elsag PROCEDURE AND APPARATUS FOR THE ROTATION OF A MATRIX OF DATIBINARIES, PARTICULARLY INTENDED FOR USE AS A MEMORY UTILITY WITH TWO-WAY ACCESS FOR ELECTRONIC CALCULATORS.
DE3009317C2 (en) * 1980-03-11 1981-11-26 SIEMENS AG AAAAA, 1000 Berlin und 8000 München Hybrid associative memory
NL8005136A (en) * 1980-09-12 1982-04-01 Philips Nv DEVICE FOR ASSOCIATIVE SEARCH IN A SEQUENTIAL INFORMATION FLOW CONSTRUCTED FROM INFORMATION BOXES.
US4370732A (en) * 1980-09-15 1983-01-25 Ibm Corporation Skewed matrix address generator

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ATE28005T1 (en) 1987-07-15
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DE3464421D1 (en) 1987-07-30

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