EP0122432A1

EP0122432A1 - Photoelectric smoke detector equipped with smoke detecting function test means

Info

Publication number: EP0122432A1
Application number: EP84102465A
Authority: EP
Inventors: Toshikazu C/O Nohmi Bosai Kogyo Co. Ltd. Morita
Original assignee: Nohmi Bosai Kogyo Co Ltd
Current assignee: Nohmi Bosai Ltd
Priority date: 1983-03-21
Filing date: 1984-03-08
Publication date: 1984-10-24
Also published as: JPH0441396B2; DE3468286D1; JPS59172094A; EP0122432B1

Abstract

This invention relates to a photoelectric smoke detector which is capable of readily and precisely checking by itself whether light intensity reaching the smoke detector is within the normal level at which no false alarm, alarm failure nor delayed alarm is caused on the basis of the signal sent from a control panel through the lines connecting between the smoke detector and the control panel, and of reporting the result to the control panel through the same lines.

Description

It has been known that the operating test of the smoke detector which detects presence of smoke by scattering of light caused by entry of smoke into the light from the light emitting element and falling onto the light receiving element is carried out by increasing, from the control panel, the output of the light emitting element to increase the output of the light receiving element with the-noise light scattered in all directions on the wall surfaces in the labyrinth. Nevertheless, none of the photoelectric smoke detectors of this kind has ever had such a provision for checking, by remote operation from the control panel, the important function the detector, i.e. whether the output of the light receiving element of the detector is within the normal level range which causes no false alarm, alarm failure nor delayed alarm.
The purpose of this invention is to obtain a photoelectric smoke detector equipped with a smoke detecting function test means which, upon receipt of a signal sent from a control panel through lines connecting the smoke detector with the control panel, is capable of automatically, readily and precisely checking whether the output of the light receiving element in the smoke detector is within the normal level range, and of reporting to the control panel on the result of the check through the same lines. This invention is described below with reference to embodiments shown with figures.
Figure 1 is a circuit diagram of an embodiment according to the present invention relating to the light scattering type smoke detector which detects presence of smoke by scattered light. Figure 2 is a circuit diagram of a control panel used for this embodiment.
Shown in Figure 1 are as follows: Two lines 1₁, 1₂ which connect the light scattering type smoke detector shown in the Figure with the control panel shown in Figure 2. Conductors a, b connected with the lines 1₁, 1₂ through a voltage stabilizing circuit CV. A pulse oscillator P0₁ for synchronized signal connected between the conductors a, b. A light emitting part 1 which comprises a light emitting element LE such as light emitting diode, and a drive circuit PD connected between the conductors a, b. A light receiving part 2 comprising a light receiving element SB such as solar cell which receives light emitted by the light emitting element LE and scattered by smoke, and an amplifier AM to amplify the output of the light receiving element SB. A comparison part 3 which comprises a comparator CM with its - terminal on the input side connected with the voltage as operating level at the junction of resistors ri, r₂ of those resistors r₁, r₂, r₃, r₄ connected in series between the conductors a, b, and its + terminal on the input side connected with the output of the amplifier AM of the light emitting part 2. The resistors r₁, r₂, r₃, r₄ are provided to determine a fire level, an upper level of the normal level range as a threshold level at which a false alarm is likely to be produced, and a lower level of the normal level range as a threshold level at which alarm failure or delayed alarm is likely to occur. A fire discriminating part 4 which .comprises an AND gate A₁ and a latch Lt₁ formed by NOR gates NR₁, NR₂. The AND gate A₁ receives outputs of the pulse oscillator PO₁ for synchronized signal, the comparator CM in the comparison part 3 and a NOT gate N₃ to the input terminal of which Q output of a monostable multivibrator MM₂ in a timer circuit 9 described hereafter is applied. The latch Lt₁ is set by output of the AND gate A₁ and cleared by output of the NOT gate N₂ in a reset signal generating circuit 8 which is described hereafter. A signal generating circuit 5 which comprises a pulse oscillator PO₂ and NAND gates NA₁, NAz. The pulse oscillator PO₂ is connected between the conductors a, b and generates pulse outputs with low frequency f₁ and high frequency f₂. The NAND gate NA₁ receives the pulse output with frequency f₁ and the output of the flip-flop circuit FF₂ in a smoke detecting function discriminating circuit 11 described hereafter. The NAND gate NA₂ receives the pulse output with frequency f₂ and the output of the gate NA₁. A signal transmission circuit 6 which comprises NOR gates NR₈, NR₉ and a series circuit connected between the lines 1₁, 1₂, and sends out the pulse signal with frequency f₁, or f₂ to the lines 1₁, 1₂ by controlling the conduction of a transistor T₃ with output of the gate NR₉. The NOR gate NR₈ receives outputs developed when the fire discriminating part 4 has detected a fire and of a latch Lt₃ formed by NOR gates NR₆, NR₇ in the smoke detecting function discriminating circuit 11. The NOR gate NR₉ receives outputs of the NOR gate NR₈ and the NAND gate NAz in the signal generating circuit 5. The series circuit is formed by a diode D₁, resistor r₅ and a transistor T₃ with a resistor r₆ connected between the base and emitter. An additional circuit shown with dotted lines in the signal generating circuit 6 is provided for identifying an alarming detector at the control panel in case plural detectors are connected in parallel between the same lines l₁, l₂. An oscillator PO_s generating pulses which vary with each detector and have far higher frequencies than f₁, f₂ is connected between the conductors a, b. A transistor T₅ is connected between the diode D₁ and the resistor r₅. Resistors r₁₈ and r₁₉ are connected between the conductor a and the base of the transistor T₅, and between the base of the transistor T₃ and the collector of the transistor T₃ respectively. A capacitor C₆ is connected between the oscillator P0₃ and the base of the transistor T₅. With. the pulse signal from the oscillator P0₃, each pulse of the pulse signals with frequencies f₁, f₂ sent from each detector to the lines 1₁, 1₂ is modulated. A signal receiving circuit 7 which receives a single pulse signal with narrow width for test start and a single pulse signal with wide width for resetting which are sent out from the control panel shown in Figure 2. The signal receiving circuit 7 is formed by resistors r₇, r₃ and a capacitor C₂ which are connected in series between the conductors a, b; an output line d which is led from the junction between the resistor r₈ and the capacitor C₂ to a reset signal generating circuit 8 and a timer circuit 9 described hereafter; and a transistor T₄, conduction of which is controlled by voltage at the junction of the resistors r₉, r_io connected in series between the lines 1₁, 1₂ and which shorts the series circuit of the resistor r₈ and the capacitor C2 when became conductive. The reset signal generating circuit 8 confirms receipt of the reset signal from the control panel and transmits the reset signal to the detector. The reset signal generating circuit 8 is equipped with a capacitor C₃ which is charged With output of the signal receiving circuit 7 through a NOT gate N₁ and a resistor r_ll, and produces the reset signal with the voltage of the capacitor C₃ through the resistor r₁₂ and NOT gate N₂. The timer circuit 9 operates when the signal receiving circuit 7 has received the test start signal from the control panel, and comprises a latch Lt₂, resistors r₁₃, r₁₄, a capacitor C₄, monostable multivibrators MM1, MM₂ and AND gates A₂, A₃. The latch Lt₂ is formed by NOR gates NR₃, NR₄ which are set by output of the signal receiving circuit 7. The output of the latch Lt₂ is sent to the monostable multiviblators MM₁, MM₂ having a short and long operating time respectively through the delay circuit formed by the resistor r₁₃, capacitor C₄ and resistor r₁₄ to prevent the timer circuit 9 from operating with the output of the latch Lt₂ when the signal receiving circuit 7 has received the reset signal from the control panel. The output of the monostable multivibrators MM₁, MM₂ are applied to the input terminals of the AND gates A₂, A₃. An operating level changeover circuit 10 which changes over the operating level of the comparator CM in the comparison part 3, and operates as follows. With the output of the AND gate A₂ in the timer circuit 9 transmitted through a diode D₂ and a resistor r₁₅, the transistor T₁ becomes conductive and shorts the series circuit formed by resistors r₃, r₄. With the output of the AND gate As transmitted through a diode D₃ and a resistor r₁₆, the transistor Tz becomes conductive and shorts the resistor r₄ alone. Thus, the voltage applied as operating level to the - terminal on the input of the comparator CM in the comparison part 3 becomes the fire level of the light scattering type smoke detector while the both transistors T₁, T₂ are not conducting. As the transistor T₁ become conductive, the voltage becomes the lower limit of the normal level range as a threshold level of the detector at which alarm failure or delayed alarm is likely to occur. As the transistor T₂ becomes conductive, the voltage becomes the upper level of the normal level range as a threshold level of the detector at which a false alarm is likely to be produced. A smoke detecting function discriminating circuit 11 which comprises AND gates A₄, As, OR gate R₁, R - S flip-flop circuit FF₁, D-type (delayed) flip-flop circuit FF₂, resistors r₁₇, r₁₈, capacitor C₅, NOT gate N₄, NOR gate NR₅ and latch Lt₃ formed by NOR gates NR₆, NR₇.' The AND gates A4, As are connected with the outputs of the pulse oscillator PO₁ for synchronized signal, the comparator CM in the comparison part 3 and AND gates A₂, A₃ in the timer circuit 9. The R - S flip-flop circuit FF₁ receives the output of the AND gate A4 as set input and the output of the OR gate R₁ as reset input which is connected with the outputs of the AND gate As and the reset signal generating circuit 8. The D type flip-flop circuit FF₂ receives Q output of the flip-flop circuit FF₁ as D input, the clock signal as CP input generated by the NOR gate NR_s and the output of the circuit 8 as reset input. The NOR gate NRs serving as clock signal generator is connected with the Q output of the monostable multivibrator MM₂ in the timer circuit 9 and the output of the NOT gate N₄ to which the voltage of the capacitor C_s charged with the Q output through the resistor r₁₇ is applied through the resistor r₁₈. The latch Lt₃ formed by the NOR gates NR₆, NR₇ receives the output of the NOR gate NR₅ as set input and is cleared by output of the reset signal generating circuit 8.
Shown in Figure 2 are; a d.c. power supply E; a detecting circuit M for abnormal signal with frequency f₂ including a fire signal; a detecting circuit N for normal signal with frequency f_l; a relay X which operates when a test start switch SW₁ has closed; a relay Y which operates when a reset switch SW₂ has closed; a test start signal generator TS which operates when the contact x₁ of the relay X has closed; a reset signal generator RS which operates when the contact y₁ of the relay Y has closed; a fire indicator lamp La₁ which is lit through the break contact x₄ of the relay X and the make contact m₁ of the relay M; an abnormal indicator lamp La₂ which is lit through the make contact x_s of the relay X and the make contact m₂ of the relay M; a normal indicator lamp La₃ which is lit through the make contact x₃ of the relay X and the make contact n₁ of the relay N; a timer T which starts operating when the contact x₅ of the relay X has closed; and a trouble indicator lamp La₄ which is operated through the make contact t of the timer T and the break contacts m₃, n₂ of the relays M, N to indicate accidents such as trouble in the detector lines or interruption of the lines 1₁, 1₂.
Firstly, operation of each part of this embodiment during the normal supervisory condition and in case of fire is described with reference to the time charts shown in Figure 3 (A). Shown in Figure 3 (A) are smoke density (1), voltage (2) on the lines 1₁, 1₂. During the normal supervisory condition without smoke, the voltage on the lines 1₁, 1₂ is E volts as shown in the left part of Figure (1) while the voltage on the output line d of the signal receiving circuit 7 is at L level as shown at the left part of Figure (3) because the transistor T4 is conducting. Consequently, in the reset signal generating circuit 8, the output of the NOT gate N₁ becomes H level. With this output the capacitor C₃ is charged, and the output of the NOT gate N₂ becomes L level, thus no reset signal is generated as shown at the left part of Figure (4). In the timer circuit 9, the latch Lt₂ formed by the NOR gates NR₃, NR₄ has the input of L level, and accordingly its output, too, is at L level as shown in the left part of Figure (5), thus no clock signal is generated. As shown in Figures (6), (7), the Q outputs of the monostable multivibrators MM₁, MM₂ are at L level, the Q output of the former MM₁ is at H level, and the outputs of the AND gates A₂, A₃ are at L level. Therefore, the transistors T₁, T₂ in the operating level changeover circuit 10 do not switch on, and as shown with the dotted line in Figure (11) the operating level of the comparator CM in the comparison part 3 is at fire level L₃ which is determined by dividing ratio of the resistance values of the resistors r₁ are r₂+r₃+r₄. The light emitting element LE emits light through the driving circuit PD in the light emitting part 1 each time the pulse oscillator PO₁ generates the synchronizing signal as shown in Figure (10). With the scattered light from the inner wall of the labyrinth the output amplifier AM of the light receiving element SB in the light receiving part 2 gives off an output as shown in Figure (11). Nevertheless, since this output is below the fire level L₃ under the condition without smoke, the comparator CM in the comparison part 3 has no output as shown in the left part of Figure (12). In the fire discriminating part 4 the output of the NOT gate N₃ is at H level because the Q output of the monostable multivibrator MM₂ in the timer circuit 9 is at L level. However, since the output of the comparator CM is at L level, the output of the AND gate A₁ becomes L level, and accordingly the input of the latch Lt₁ formed by NOR gates NR₁, NR₂ and the output of the NOR gate NR₂ are at L level as shown in the left part of Figure (13). In the smoke detecting function discriminating circuit 11 the output of the comparator CM in the comparison part 3 being at L level, the outputs of the AND gates A4, As are at L level. Accordingly the output of the OR gate R₁ is at L level and the Q output of the R - S flip-flop circuit FF₁ is at L level as shown in Figure (14). The Q output of the monostable multivibrator MM₂ in the time circuit 9 is at L level while the output of the NOT gate N₄ is at H level. Accordingly, the outputs of the NOR gate NR₅ serving as clock signal generator, the Q output of the D-type flip-flop circuit FF₂ and the output of the latch Lt₃ formed by NOR gate NR₆, NR₇ are at L level as shown in Figure (16), (15) and (17) respectively. Therefore, in the signal generating circuit 5 the pulse oscillator P0₂ produces pulses with frequencies f₁ and f₂ shown in Figure (18) and (19) respectively. With the pulse having frequency f₁ and the Q output of the circuit FF₂ being at L level, the output of the NAND gate NA₁ becomes continuous H level. With the pulse signal having frequency f₂ and the continued H level output of the NAND gate NA₁, the NAND gate NA₂ generates a pulse signal with a phase opposite to that of the pulse signal having frequency f₂ from the pulse oscillator P0₂ as shown in Figure (20). Since the output of the NOR gate NR₅ in the signal transmission circuit 6 is at H level, the output of the NOR gate NR₉ is at L level as shown in the left part of Figure (21), consequently the transistor T₃ does not become conductive, and no output appears on the lines 1₁, 1₂ as shown in the left part of Figure (2).
When smoke generated by fire enters the labyrinth and its density exceeds the fire level L₃ as shown in the middle part of Figure (1), the amplifier AM for the light receiving element SB generates a pulse signals exceeding the fire level L₃ as shown in Figure (11), and the comparator CM generates a corresponding pulse signal as shown in Figure (12) at the time of light emission from the light emitting element LE. With this pulse signal, the synchronizing signal generated by oscillator PO₁ as shown in Figure (10) and the H level output of the NOT gate N₃, the AND gate A₁ generates a pulse signal corresponding to the output of the comparator CM. This pulse signal sets the output of the latch Lt₂ formed by NOR gates NR₁, NR₂ as shown in Figure (13), and the NOR gate NR₂ generates a fire detecting output. With the fire detecting output from the NOR gate NR₁, the output of the NOR gate NR_e in the signal transmission circuit 6 becomes L level. With this L level output and the pulse signal of frequency f₂ from the NAND gate N₂ in the signal generating circuit 5 as shown in Figure (20), the NOR gate NR₉ generates a pulse signal with frequency f₂ as shown in Figure (21) and sends an abnormal signal with frequency f₂ as fire signal as shown in Figure (2) to the lines 1₁, 1₂ through the transistor T₃. As the abnormal signal detecting circuit M in the control panel shown in Figure 2 detects the fire signal, the contact m₁ closes and the fire indicator lamp La_l lights. In order to reset the alarming detector the reset switch SW₂ on the control panel is closed to operate the relay Y. Then, the contact y₁ closes to operate the reset signal generator RS, which sends out the reset signal as shown with the symbol P₂ in Figure (2) to the lines 1₁, 1₂. With the signal P₂ the transistor T₄ in the signal receiving circuit 7 in the detector stops conducting, and the signal P₂ as shown in Figure 3 (3) is generated in the output line d in the circuit 7, As a result of this, the output of the NOT gate N₁ in the reset signal generating circuit 8 becomes L level, and the charge on the capacitor C₃ is released through the NOT gate N₁. When the input of the NOT gate N₂ becomes L level, the NOT gate N₂ generates the clear signal c as shown in Figure (4). On the other hand, if the output P₂ of the circuit 7 is received by the input terminal of the latch Lt₂formed by NOR gates NR₃, NR₄ in the timer circuit 9 before the NOT gate N₂ generates the clear signal, the latch Lt₂ is set and the NOR gate NR₄ gives an output at H level as shown in Figure (5). With the output of the NOR gate NR₄ the capacitor C₄ is charged as shown with the dotted line in Figure (5) through the resistor r₁₃. Since the circuit 8 generates the clear signal c as shown in Figure (4) before the capacitor voltage reaches such a level as may be judged as a clock signal, the setting of the latch Lt₂ is cleared by this signal c and the charge on the capacitor C4 is released through the resistor r₁₄, thus no clock signal is generated. When resetting the detector in the above manner, if the smoke density is below the fire level L₃ as shown in Figure (1), setting of the latch Lt₁ formed by NOR gates NR₁, NR₂ is cleared by the clear signal c shown in Figure (4), and the fire detecting output of the NOR gate NR₂ stops as shonw in Figure (13). Then the output of the NOR gate NRb in the signal transmission circuit 6 becames H level, and the output of the NOR gate NR₉ stops, thus no fire signal is sent to the lines 1₁, L₂. Consequently, the abnormal signal detecting circuit M in the control panel shown in Figure 2 no longer detects the fire signal, thus the contact mi opens, and the fire indicator lamp La_i extinguishes.
Operation of each part at the time of testing while the output of the amplifier AM in the light receiving part 2 is within the normal level range is described below with reference to the time chart shown in Figure 4 (A).
As the test start switch SW₁ in the control panel shown in Figure 2 is closed, the relay X operates and the contacts x₁ ~ x₃ close.
The test start signal generator TS sends the test start signal shown with a symbol P₁ in Figure 4A (2) to the lines 1₁, 1₂ to interrupt, for a short time, conduction of the transistor T₄ in the signal receiving circuit 7 of the detector shown in Figure 1. The circuit 7 generates the pulse signal P_i' in the output line d as shown in Figure (3). With the signal P₁', the output of the NOT gate N₁ in the reset signal generating circuit 8 becomes L level, and the charge on the capacitor C₃ is released through the NOT gate N₁. Nevertheless, before the voltage of the capacitor C₃ raises the output of the NOT gate N₂ to H level, the output P₁' disappears and the output of the NOT gate N₁ again becomes H level. Therefore, the capacitor C₃ is recharged, thus the NOT gate N₂ maintains the L level output as shown in Figure (4). The output P₁' of the circuit 7 also sets the latch Lt₂ formed by NOR gates NR₃, NR₄ in the timer circuit 9: As the capacitor C₄ is charged with the H level output of the NOR gate NR₄ through the resistor r₁₃ as shown with the dotted line in Figure (5) and its voltage reaches the H level, the clock signal is sent to the CP terminals of the monostable multivibrators MM₁, MM₂ with this voltage. At the Q terminals of the monostable multivibrators MM₁, MM₂, H level outputs develop as shown in Figures (6), (7), and a L level output develops on the Q terminal of the monostable multivibrator MM₁, then the output of the AND gate A₂ becomes H level as shown in Figure (8). The transistor T₁ in the operating level changeover circuit 10 too is conducting while the output of the AND gate A₂ is at H level. Thus, the operating level of the comparator CM in the comparison part 3 becomes the lower level L₁ of the normal level range which is determined by resistance dividing ratio of the resistor r₁, r₂, as shown with the dotted line in Figure (11). Furthermore, since the Q output of the monostable multivibrator MMz is at H level, the output of the NOT gate N₃ becomes L level and inhibits operation of the AND gate Ai. On the other hand the capacitor C₃ in the function discriminating circuit 11 is charged. When its voltage reaches a predetermined value, the output of the NOT gate N₄ becomes L level, but the other input of the NOR gate NRs is at H level. Therefore, the NOR gate NR₅ does not produce the clock signal.
Under this condition, if the pulse output of the amplifier AM in the signal receiving part 2 lies between the lower level L₁ and the upper level L2 of the normal level range as shown in Figure (11), the comparator CM generates detecting pulse signal as shown in Figure (12) because the pulse output of the amplifier AM is above the operating level of the comparator CM. With this pulse output of the comparator CM, synchronized signal generated by the pulse oscillator PO₁ and H level output of the AND gate A₂, the AND gate A4 generates the pulse output similar to that of the comparator CM as shown in Figure (12). This output of the AND gate A4 sets the Q output of the circuit FF₁ in the function discriminating circuit 11 at H level as shown in Figure (14). On the other hand the Q output of the circuit FF₂ remains at L level as shown in Figure (15) because the CP terminal receives no clock signal from the NOR gate NR_s.
After lapse of a predetermined short time the Q output and Q output of the monostable multivibrator MM₁ in the timer circuit 9 become L level and H level respectively as shown in Figure (6). Consequently, the output of the AND gate A₂ becomes L level as shown in Figure (8), inhibiting operation of the AND gate A4 in the circuit 11, and rendering the transistor T₁ in the circuit 10 non conductive. On the other hand, the output of the AND gate A₃ becomes H level as shown in Figure (9), the transistor T₂ becomes conductive, and the operating level of the comparator CM in the comparison part 3 reaches the upper level of the normal level range as shown with the symbol L₂ in Figure (11) which is determined by dividing ratio of the resistors r₁ and r₂+r₃. Under this condition, if the amplifier AM in the light receiving part 2 has the normal output as shown in Figure (11), the output of the comparator CM is at L level as shown in Figure (12) because the output of the amplifier AM is below the level L₂.
When the output of the monostable multivibrator MM₂ becomes L level as shown in Figure (7) after lapse of a predetermined long time, this L level output and the output of the NOT gate N₄ in the function discriminating circuit 11 at L level cause the NOR gate NR₅ to generate the clock signal c as shown in Figure (16). With this signal c, the Q output of the flip-flop circuit FF₂ becomes H level as shown in Figure (-15) because the Q output of the flip-flop circuit FF₁ is at H level as shown in Figure (14). With the H level output of the flip-flop circuit FF₂, the NAND gate NA₁ in the signal generating circuit 5 generates a pulse signal having the phase opposite to that of the pulse signal with frequency f₁ generated by the oscillator P0₂, :and the NAND gate NA₂ generates a pulse signal with frequency f₁ as shown in Figure (20). The clock signal from the NOR gate NR₅ sets the latch Lt₃ formed by NOR gates NR₆, NR₇, and the output of the NOR gate NR₇ becomes H level. With this H level output, the output of the NOR gate NR₆ in the signal transmission circuit 6 becomes L level, and the NOR gate NR₉ generates a pulse signal with frequency f₁ as shown in Figure (21), by which conduction of the transistor T₃ is controlled and the normal signal shown in Figure (2) is sent to the lines l₁, l₂. Lastly, as the signal receiving circuit 7 has received the reset signal P₂ shown in Figure (2) and has an output P₂' shown in Figure (3) on its output line d, the NOT gate N₂ in the reset signal generating circuit 8 generates a clear signal c shown in Figure (4), which resets the latches Lt₂, Lt₃ formed by NOR gates NR₃, NR₄ and NR₆, NR₇ respectivel in the same manner as resetting in case of fire. Then, the outputs of the NOR gates NR₄, NR₇ become L level as shown in Figure (5) and (17) respectively. With the L level output of the NOR gate NR₇, the NOR gate NR₉ no longer generates the pulse signal as shown in Figure (21), and accordingly the signal transmission circuit 6 stops transmitting the normal signal as shown in Figure (2). The clear signal from the NOT gate N₂ resets the flip-flop circuit FF₁ in the function discriminatin circuit 11 through the OR gate R₁, and the flip-flop circuit FF₂ directly. The Q outputs of the beth circuits become L level as shown in Figures (14), (15). With the L level output of the flip-flop circuit FF₂, the output of the NAND gate NA₁ in the signal generating circuit 5 become H level and the NOT gate NA₂ generates the pulse signal with frequency f₂ as shown in Figure (20), thus each part of the detector returns to the original state.
Now, the following describes operation of each part during the test with reference to the time chart shown in Figure 5 (A) in case that the output of the amplifier AM has been reduced below the lower level L₁ of the normal level range due to soiling by dust accumulating over the light receiving surface of the light receiving element SB in the light receiving part 2.
In this case, too, the signal receiving circuit 7 in Figure 1 generates a pulse signal P₁' in the output line d with the test start signal P₁ from the control panel shown in Figure 5 (A) (2). However, due to -narrow pulse width of the pulse signal P₁', the NOT gate N₂ in the reset signal generating circuit 8 generates no clear signal. On the other hand the latch Lt₂ formed by NOR gates NR₃, NR₄ in the timer circuit 9 is set as shown in Figure (5) with the pulse signal P₁'. When the capacitor C₄ is charged with the H level output of the NOR gate NR₄ through the resistor r₁₃ as shown with the dotted line in Figure 5 (A) (5) and the voltage reaches the H level, outputs of H level develop at the Q terminals of the monostable multivibrators MM₁, MM₂ as shown in Figure (6), (7), and the output of the AND gate A₂ becomes H level. Then, the transistor T₁ in the operating level changeover circuit 10 becomes conductive as shown in Figure (8), and the operating level of the comparator CM in the comparison part 3 becomes the lower level L₁ of the normal level range as shown with the dotted line in Figure (11).
With the H level output of the monostable multivibrator MM₂, the output of the NOT gate N₃ in the fire discriminating part 4 becomes L level and inhibits operation of the AND gate A_l, while on the other hand the NOR gate NR₅ in the function discriminating circuit 11 generates no clock signal as shown in Figure (16).
Under this condition, if the output of the amplifier AM in the light receiving part 2 is below the level L₁ as shown in Figure (11), the transistor T₁ in the operating level changeover circuit 10 becomes conductive as shown in Figure (8). Therefore, even if the operating level of the comparator CM in the comparison part 3 becomes the lower level L₁ as shown in Figure (11), no detecting signal is generated in the comparator CM as shown in Figure (12), the AND gate A4 in the function discriminating circuit 11 has no output, and the flip-flop circuit FF₁ is not set as shown in Figure (14).
Then, after lapse of a predetermined time, the Q output of the monostable multivibrator MM₁ in the timer circuit 9 becomes L level as shown in Figure 6, and the Q output becomes H level. The outputs of the AND gates A₂, A₃ become L and H levels respectively as shown in Figures (8), (9), thus rendering the transistor T₁ non-conductive and the transistor T₂ conductive. Consequently the operating level of the comparator CM becomes the level L₂ as shown in Figure (11). Enen at this level L₂, the comparator CM has no output as shown in Figure (12), and the AND gate A,, too, has no output. After further lapse of a predetermined time the Q output of the monostable multivibrator MM₂ becomes L level as shown in Figure (7), and the NOR gate NR_s generates the clock signal c shown in Figure (16), which sets the latch Lt₃.
As the output of the NOR gate NR_a in the signal transmission circuit 6 becomes L level with the H level output of the NOR gate NR₇ shown in Figure (17), the NOR gate NR, generates a pulse signal with frequency f₂ as shown in Figure (21) because the NAND gate NA₂ in the signal generating circuit 5 is generating a pulse signal with frequency f₂ as shown in Figure (20). By the pulse signal from the NOR gate NR₉, conduction of the transistor T₃ is controlled, and the abnormal signal is sent to the control panel through the lines 1₁, 1₂ as shown in Figure (2).
The following describes operation of each part during the test with reference to the time chart shown in Figure 6 (A), which is carried out in case the output of the amplifier AM for the light receiving element SB in the light receiving part 2 has exceeded the upper level L2 of the normal level range due to accumulation of dust in the labyrinth. As in the case of the foregoing, the signal receiving circuit 7 in Figure 1 generates the pulse signal P₁' in the output line d shown in Figure (3) with the test start signal P₁ from the control panel shown in Figure 6 (A) (2). Although the NOT gate N₂ in the reset signal generating circuit 8 does not generate the clear signal, the latch Lt₂ in the timer circuit 9 is set. The capacitor C₄ is charged with the H level output of the NOR gate NR₄ as shown with the dotted line in Figure (5). When the voltage reaches the H level, outputs of H level develop at the Q terminals of the monostable multivibrators MM_i, MM₂ as shown in Figure (6), (7) and the output of the AND gate A₂ becomes H level. Then, the transistor T₁ in the operating level changeover circuit 10 becomes conductive as shown in Figure 6 (8), and the operating level of the comparator CM in the comparison part 3 becomes the lower level L₁ of the normal level range as shown with the dotted line in Figure (11). With the H level output of the Q terminal of the monostable multivibrator MM₂, the output of the NOT gate N₃ in the fire discriminating circuit 4 becomes L level and-inhibits operation of the AND gate A₁, while-on the other hand the NOR gate NR₅ in the function discriminating circuit 11 generates no clock signal.
Under this condition, if the output of the amplifier AM in the light receiving part 2 is over the level L₂ as shown in Figure (11), the transistor T₁ in the operating level changeover circuit 10 become conductive as shown in Figure (8). As the operating level of the comparator CM in the comparison part 3 becomes the level L₁ as shown in Figure (11), the output of the comparator CM becomes the H level. With this output of the comparator CM, the output of the AND gate A4 in the function discriminating circuit 11 becomes H level, and accordingly the Q output of the flip-flop circuit FF₁ is set at H level as shown in Figure (14). However, since the CP terminal of the flip-flop circuit FF₂ receives no clock signal from the NOR gate NR₅, the Q output of the flip-flop circuit remains at L level. After lapse of a predetermined time under this condition, the Q output of the monostable multivibrator MM₁ in the timer circuit 9 becomes L level as shonw in Figure (6) and Q output becomes H level. The outputs of the AND gates A₂, As become L and H levels respectively as shown in Figure (8), (9). Thus, the transistor T₁ becomes non-conductive and the transistor T₂ conductive. Then, the operating level of the comparator CM changes to level L₂ as shown in Figure (11), the output of the comparator CM remains at II level. With this output the AND gate A₅ and the OR gate R₁ generate H level outputs successively. With the output reaching the reset terminal R of the flip-flop circuit FF₁, the Q output of the flip-flop circuit FF₁ is reset at the L level as shown in Figure (14). Even if the comparator CM has an output thereafter, the Q output of the flip-flop circuit FF₁ remains at L level as shown in Figure (14) as long as the operating level of the comparator CM is at the level L₂, because the output of the comparator CM reaches the R terminal of the flip-flop circuit FF₁ through the AND gate As and the OR gate R_l. As in the previous case, after lapse of a predetermined time the Q output of the monostable multivibrator MM₂ becomes L level as shown in Figure (7), and the NOR gate NR₅ in the circuit 11 generates the clock signal c shown in Figure (16), which sets the latch Lt₃. As the NOR gate NR₇ has H level output shown in Figure (17), and the output of the NOR gate NR_s in the signal transmission circuit 6 becomes the L level, the NAND gate NA₂ in the signal generating circuit 5 generates a pulse signal with frequency f₂ as shown in Figure (20), and accordingly the NOR gate NR₉ generates a pulse signal of frequency f₂ as shown in Figure (21) to control conduction of the transistor T₃ and to send an abnormal signal to the control panel through the lines 1₁, 1₂ as shown in Figure (2).
Now, the following describes how the signal receiving circuit 7 operates with the reset signal P₂ shown in Figure 5 (A) and 6 (A) (2) and received from the control panel after the test conducted in case that the output of the amplifier AM has fallen below the lower level L₁ and exceeded the upper level L₂. The signal receiving circuit 7 generates a pulse signal P₂' shown in Figure (3) in the output line d. The NOT gate N₂ in the reset signal generating circuit 8 generates the clear signal c shown in Figure 6 (4), with which the latches Lt₂, Lt₃ formed by NOR gates NR₃, NR₄ and NR₆, NR₇ respectively are reset. Then, the outputs of the NOR gates NR₄, NR₇ become L level as shown in Figures (5) and (17). Because of this L level output of the NOR gate NR₇, the NOR gate NR₉ no longer generates the pulse signal as shown in Figure (21), and the signal transmission circuit 6 stops transmitting the abnormal signal to the lines 1₁, 1₂ as shown in Figure (2), thus each part of the detector resets to the original condition.
Lastly, the following describes operation of the control panel when the test is conducted with the test start signal from the control panel shown in Figure 2. When the switch SW₁ is closed for testing, the relay X operates tu close the contacts x₁ ~ x₃ and open the contact x₄. Therefore, on receipt of the normal signal from the detector shown in Figure 1, the relay N operates and close the contact N₁, and the normal indicator lamp La₃ lights. When the abnormal signal is received, the relay M operates and closes the contacts m_l, m₂ to cause the abnormal indicator lamp La₂ to light up indicating that there is abnormality in the smoke detecting function. As the switch SW₂ is closed to reset the detector, the relay Y operates and closes the contact y₁ and opens the contact y₂ to actuate the reset signal generator RS which sends the reset signal to the lines 1₁, 1₂. At the same time, operation of the relay X is stopped and the contacts x₁, x₂, x₃ are opened to prevent the test signal generator TS from operating and to extinguish the normal indicator lamps La₂, La₃. The contact x₄ is closed to reset the control panel in the normal supervisory condition. Figure 7 is a circuit diagram of another embodiment according to the -present invention relating to a light extinction type smoke detector which detects smoke on light extinction principle. The circuit diagram of the control panel used for this embodiment is the same as Figure 2.
The light extinction type smoke detector shown in Figure 7 only differs from Figure 1 in that the resistors r₁ ~ r₄ are connected in series across the conductors a, b in opposite order to determine the upper level L₁ of the normal level range as threshold level at which alarm failure or delayed alarm is likely to occur, a lower level L₂ as threshold level at which false alarm is likely to be produced, and the fire level Ls, and that the voltage of operating level developing at the junction of the resistors r₁ and r₂ is applied to the + terminal of the comparator CM in the comparison part 3 and the output of the amplifier AM in the light receiving part 2 is led to the - terminal so that the comparator CM generates the detecting output -when the output of the amplifier AM has fallen below the operating level. Therefore, as compared with the time chart of Figure 3 (A) of the embodiment shown in Figure 1, the normal supervisory state of this embodiment and the operating state of each part in case of fire only differs in the outputs of the amplifier AM in the light receiving part 2 and of the comparator CM in the comparison part 3 as shown in Figures (11) and (12). Therefore, these different outputs shown with Figures (11), (12) are extracted and indicated at the lower part of Figure 3 (A) as Figures (B) (11'), (12').
Now, operation of the embodiment is described with reference to Figures 3 (A) but (11), (12), and (B) (11'), (12'). With respect to Figure 3 (A) some descriptions have already been made, and only their summary is given hereunder. In normal supervisory condition without smoke the transistor T₁ in the signal receiving circuit 7 is conducting and its output line d has no output as shown in the left part of Figure (3).
Consequently, the outputs of the reset signal generating circuit 8 and of the AND gates A₂, As in the timer circuit 9 are L level, and the transistors T₁, T₂ in the operating level changeover circuit 10 do not conduct. As the operating level of the comparator CM in the comparison part 3 is at the fire level L₃ (e.g. 85X light transmittivity of the output of the amplifier AM as indication of light transmittivity while no smoke presents), the comparator CM has the L level output shown in Figure (12') and the output of the AND gate A₁ is at the L level when the amplifier AM generates a pulse signal exceeding the level L₃ shown in Figure (11'). Consequently, no signal is sent to the lines 1₁, 1₂. Nevertheless, when the amplifier AM has generated a pulse signal below the fire level as shown Figure (11') as a result of entry of smoke from fire between the light emitting element LE in the light emitting part 1 and the light receiving element SB in the light receiving part 2, the comparator CM has the H level output as shown in Figure (12'), with which and the synchronizing signal from the oscillator PO₁ and the H level output of the NOT gate N_s, the AND gate A₁ in the fire detecting part 4 generates a pulse signal corresponding to the output of the comparator CM. Then, the latch Lt₁ formed by the NOR gates NRi, NR₂ is set as shown in Figure (13). With the H level output of the NOR gate NR₂, a fire signal with frequency f₂ shown in Figure (2) is sent to the lines 1₁, 1₂ through the signal transmission circuit 6. Operation of the control panel after receipt of this fire signal and resetting of the fire detector by reset signal from the control panel are same as in the case of the light scattering type smoke detector.
Operation of each part at the time of the test while the output of the amplifier AM in the light receiving part 2 of this embodiment only differs in Figure (11) showing the output of the amplifier AM in the light receiving part 2 and Figure (12) showing the output of the comparator CM in the comparison part 3 as compared with the time chart, Figure 4 (A) for the embodiment shown in Figure 1. Therefore, only these different outputs shown with Figures (11), (12) are extracted and indicated at the lower part of Figure 4 (A) as Figure (B) (II'), (12').
Now, operation of the embodiments is described with reference to Figures 4 (A) but (11), (12), and (B) (II'), (12'). With the test start signal P₁ shown in Figure (2) from the control panel the signal receiving circuit 7 generates a pulse output P₁,' shown in Figure (3) in its output line d, but the reset signal generating circuit 8 does not generate the clear signal due to the narrow pulse width. The pulse signal P₁' sets the latch Lt₂ formed by NOR gates NR,, NR₄ in the timer circuit 9. With the H level output of the NOR gate NR4 shown in Figure (5) the capacitor C₄ is charged as shown with the dotted line in Figure (5). As the voltage of the capacitor C₄ reaches the H level, the clock signal is transmitted to the CP terminals of the monostable multivibrators MM₁, MM₂. Then, the Q terminals of the monostable multivibrators MM₁, MM₂ have H level outputs as shown in Figures (6), (7), with which the output of the AND gate A₂, too, become the H level as shown in Figure (8), and the transistor T₁ in the operating level changeover circuit 10 becomes conductive. The operating level of the comparator CM in the comparison part 3 becomes the upper level L₁ of the normal-level range (e.g. 105% light transmittivity) as shown with the dotted line in Figure (11'). Under this condition, if the pulse output of the amplifier AM in the light receiving part 2 lies between the upper level L₁ and the lower level L₂ of the normal level range as shown in Figure (11'), the pulse output is below the operating level of the comparator CM. Therefore, the comparator CM has no L level output, but H level output as shown in Figure (12'). With this H level output and the synchronizing signal from the oscillator PO₁ and the H level output of the AND gate A₂, the AND gate A4 generates a pulse output which is similar to that shown in Figure (12). By this pulse signal the output of the Q terminal of the flip-flop circuit FF₁ in the function discriminating circuit 11 is set at H level. However, since no clock signal is transmitted from the NOR gate NR₅ to the CP terminal of the flip-flop circuit FF₂, the output of the Q terminal remains at L level as shown in Figure (15): After lapse of a predetermined time the output of the Q terminal of the monostable multivibrator MM₁ in the timer circuit 9 becomesL level as shown in Figure (6), and the output of the Q terminal becomesH level. The outputs of the AND gates A₂ and As become L and H levels respectively as shown in Figures(8) and (9). In the operating level changeover circuit 10, the transistor T₁ stops conducting and the transistor T₂ become conductive, thus the operating level of the comparator CM in the comparison part 3 becomes the lower level L₂ of the normal level range. Under this condition, the output of the amplifier AM in the light receiving part 2, if generated, is above the level L2, and therefore the output of the comparator CM becomes the L level as shown in Figure (12'). When the output of the monostable multivibrator MM₂ in the timer circuit 9 become L level as shown in Figure (7) after lapse of a predetermined time, this L level output and the L level output of the NOT gate N₄ in the function discriminating circuit 11 cause the NOR gate NR₅ to generate the clock signal c as shown in Figure (16). With this signal c the flip-flop circuit FF₂ has the H level output shown in Figure (15) at the Q terminal. With this H level output and the H level output shown in Figure (17) of the NOR gate NR₇ of the latch Lt₃ which is set by the clock signal c, the normal signal shown in Figure (2) is sent to the lines 1₁, 1₂ through the signal generating circuit 5 and the signal transmission circuit 6. As the signal receiving circuit 7 receives from the control panel the reset signal P₂ shown in Figure (2), each part of the fire detector returns to its original state in the same manner as the light scattering type smoke detector.
Operation of each part at the time of the test in case the output of the light receiving element SB in the light receiving element 2 has increased due to influence of the external light and the output of the amplifier AM has exceeded the upper level L₁ of the normal level range only differs in Figure (11) showing the output of the amplifier AM and Figure (12) showing the output of the comparator CM in the comparison part 3 as compared with the time chart, Figure 5 (A) for the embodiment shown in Figure 1. Therefore, only these different outputs shown in Figures (11), (12) are extracted and indicated at the lower part of Figure 5 (A) as Figure (B) (11'), (12').
Now, operation of the embodiment is described with reference to Figure 5 (A) but (11), (12), and to Figures (B) (II'), (12'). With the test start signal P₁ shown in Figure (2) the signal receiving circuit 7 generates a pulse output P_l' shown in Figure (3) in its output line d, but the reset signal generating circuit 8 does not generate a clear signal due to the narrow pulse width. The pulse signal P₁' sets the latch Ltz formed by NOR gates NR₃, NR₄ in the timer circuit 9. With the H level output of the NOR gate NR₄ shown in Figure (5), the H level outputs shown in Figures (6), (7) appear on the Q terminals of the monostable multivibrators MM₁, MM₂, and the output of the AND gate A₂ becomes H level, and the transistor T₁ in the operating level changeover circuit 10 becomes conductive as shown in Figure (8). Thus, the operating level of the comparator CM becomes the upper level L₁ of the normal level range as shown with the dotted line in Figure (11'). Under this condition, if the output of the amplifier AM in the light receiving part 2 is above the upper level L₁, the comparator CM in the comparison part 3 has no output as shown in Figure (12'), and the transistors T₁, T₂ in the operating level changeover circuit 10 become conductive as shown in Figures (8), (9). Therefore, even if the operating level of the comparator CM has changed from the level L₁ to the level L₂, the comparator CM has no output. After lapse of a predetermined time the output of the Q terminal of the monostable multivibrator MM₂ becomes L level as shown in Figure (7). The NOR gate NR₅ in the smoke detecting function discriminating circuit 11 generates the clock signal c shown in Figure (16), and the NOR gate NR₇ has the H level output as shown in -Figure (17). The output of the NOR gate NR_e in the signal transmission circuit 6 becomes L level. Then, the NOR gate NR₉ generates a pulse output with frequency f₂ as shown in Figure (21) to send the abnormal signal to the lines 1₁, lz as shown in Figure (2).
Operation of each part at the time of the test in case the output of the amplifier AM has fallen below the lower level L₂ of the normal level range due to soiling of the light receiving surface of the light receiving element SB in the light receiving part 2 by dust only differs in Figure (11) showing the output of the amplifier AM and Figure (12) showing the output of the comparator CM as compared with the time chart, Figure 6 (A) for the embodiment shown in Figure 1. Therefore, only these different outputs shown in Figures (11), (12) are extracted and indicated at the lower part of Figure 6 (A) as Figures(B) (11'), (12').
Now, operation of the embodiment is described with reference to Figure 6 (A) but (11), (12), and to Figures (B) (11'), (12'). With the test start signal P₁ shown in Figure (2) the signal receiving circuit 7 generates a pulse output P₁' with narrow width shown in Figure (3) in its output line d, but the reset signal generating circuit 8 does not generate a clear signal. The latch Ltz formed by NOR gates NR₃, NR₄ is set. With the H level output of the NOR gate NR4 shown in Figure (5) the H level outputs shown in Figures (6), (7) appear on the Q terminals of the monostable multivibrators MM₁, MM₂, and the output of the AND gate A₂ becomes H level, and the transistor T₁ in the operating level changeover circuit 10 becomes conductive as shown in Figure (8). Thus, the operating level of the comparator CM becomes the upper level L₄ of the normal level range as shown with the dotted line in Figure (11'). If the output of the amplifier AM in the light receiving part 2 is below the lower level L₂ of the normal level range at this time, the comparator CM has no L level output but the H level output as shown in Figure (12'). With this H level output the AND gate A4 in the function discriminating circuit 11 generates a pulse output similar to that shown in Figure (12).
This pulse output sets the output of the Q terminal of the flip-flop circuit at H level as shown in Figure (14), but the output of the Q terminal of the flip-flop circuit FF₂ remains at L level because no clock signal is transmitted to the CP terminal of the flip-flop circuit FF₂. Under this condition, the transistor T₂ soon becomes conductive in place of the transistor T₁ as shown in Figure (9), and the operating level of the comparator CM changes to the level L₂ as shown in Figure (11'). In this case, too, the output of the comparator CM is at H level, with which the AND gate A₅ and OR gate R₁ successively generate H level outputs to the R terminal of the flip-flop circuit FF₁, the Q output of which becomes the L level as shown in Figure (14). After lapse of a predetermined time as the output of the Q terminal of the monostable multivibrator MM₂ becomes L level as shown in Figure (7), and the NOR gate NR₅ in the function discriminating circuit 11 generates the clock signal c as shown in Figure (16), the latch Lt₃ formed by NOR gates NR₆, NR₇ is set. Then, the NOR gate NR₇ has a H level output as shown in Figure (17), and the abnormal signal is transmitted to the control panel through the signal transmission circuit 6 and the lines 1₁, 12 in the same manner as described with regard to Figure 6 (A) for the light scattering type smoke detector.
Operation of the smoke detector when its signal receiving circuit 7 has received the reset signal P₂ from the control panel after the test in case the output of the amplifier AM exceeded the upper level L₁ of the normal level range and fallen below the lower level L₂, and operation of the control panel when tested with the test start signal from the control panel are same as in the case of the light scattering type smoke detector.
In the both cases of the light scattering type and light extinction type smoke detectors, if there is a trouble in the detector circuit or interruption of the lines 1₁, 1₂, and neither normal signal nor abnormal signal from the detector reaches the control panel despite the lapse of the operating time of the timer T after the test start signal is sent from the control panel shown in Figure 2, the timer T operates and closes its contact t to operate the trouble indicator lamp La₄, by which it is possible to know the trouble in the detector circuit or lines 1₁, 1₂.
In the above embodiments, the descriptions are made with respect to such cases that the smoke detector and the control panel are connected by two lines which are commonly used as power supply lines and signal lines. However, in Figures 1 and 7 the terminal on the right side of the voltage stabilizing circuit CV may be disconnected from the line 1₁ and connected with a third line 1₃ which is exclusively used for power supply so that the power supply lines may be separated from the signal lines to avoid influence of the pulse signal width upon the voltage stabilizing circuit and to get a larger S/N ratio.
As can be seen from the above description, the photoelectric type smoke detector equipped with smoke detecting function test means according to this invention has such as advantage that with proper composition it is capable of automatically, readily and precisely checking, on the basis of the signal sent from the control panel through the lines connecting the smoke detector with the control panel, whether the output of the detector is within the normal level range which cause no false alarm, alarm failure nor delayed alarm, i.e. an important function of this type of detector, and of reporting to the control panel on results of the test through the same lines.

4. Brief Description of Drawings

Figures 1 and 7 are circuit diagrams of embodiments of the light scattering type and light extinction type smoke detectors equipped with smoke detecting function test means according to this invention. Figure 2 is a circuit diagram of a control panel which is common to these two embodiments. Figures 3 through 6 are time charts showing operating status of each part of the embodiments shown with Figures 1 and 7 in different casses, i.e. Figure 3 (A) is the one for the embodiment of Figure 1 in normal condition and in case of fire, Figure 4 (A) is the one at the time of test while the output of the embodiment shown in Figure 1 is within the normal level range, and Figures 5 (A) and 6 (A) are the ones at the time of tests in the cases that the output of the embodiment shown in Figure 1 is below the lower limit and above the upper limit of the normal level-range. Figures 3 (B) through 6 (B) shown only outputs (11') and (12') of amplifier AM and comparator CM respectively which differ from those shown in Figures 3 (A) through 6 (A) in the time charts corresponding to Figures 3 (A) through 6 (A) of the embodiment shown with Figure 7.

1 .................. Light emitting part
2 .................. Light receiving part
3 .................. Comparison part
4 .................. Fire discriminating part
5 .................. Signal generating part
6 .................. Signal transmission circuit
7 .................. Signal receiving circuit
8 .................. Reset signal generating circuit
9 .................. Timer circuit
10 .................. Operating level changeover circuit
11 .................. Smoke detecting function discriminating circuit

Claims

1. A photoelectric smoke detector equipped with smoke detecting function test means which is characterized in that an operating level changeover circuit and a smoke detecting function discriminating circuit are provided to automatically changeover, with test start signal from a control panel, the operating level from the fire level to the upper and lower level of the normal level range of the received light within which no false alarm, alarm failure nor delayed alarm is caused, and to send a normal signal to the control panel when the light received is within the normal level range, and an abnormal signal to the control panel when the light received is out of the normal level range.

2. A photoelectric smoke detector equipped with smoke detecting function test means as set forth in Claim 1 wherein changeover of the operating level is done by changeover of another input value having the equivalent operating level to that uf the comparator to the input side of which the output of the received light is applied.

3. A photoelectric smoke detector equipped with smoke detecting function test means as set forth in Claim 1 wherein the normal signal and abnormal signal are discriminated by difference in pulse frequencies of the pulse signals.