EP0113590B1

EP0113590B1 - Semiconductor timer

Info

Publication number: EP0113590B1
Application number: EP83308013A
Authority: EP
Inventors: Hideki Arakawa; Hiromi Kawashima
Original assignee: Fujitsu Ltd
Current assignee: Fujitsu Ltd
Priority date: 1982-12-29
Filing date: 1983-12-29
Publication date: 1989-11-15
Also published as: DE3380865D1; EP0113590A3; JPS59123320A; JPH035689B2; EP0113590A2; US4584494A

Description

The present invention relates to a semiconductor timer, particularly to a timer circuit formed on a metal oxide semiconductor (MOS) integrated circuit.
In certain MOS integrated circuits, it is necessary to provide a timer circuit which can set a long time interval. For example, an electrically erasable and programmable read only memory (EEPROM) in general requires timer circuits having a time interval of about 10 to 20 msec for erasing and writing operations. According to the prior art, since such a time interval is produced by a time delay of a continuously charged or discharged CR circuit, a capacitor having a very high capacitance, for example, about 5600 pF, is required. Such a capacitor cannot be formed by a semiconductor, so an external capacitor having a very high capacitance is attached to the integrated circuit. However, this requires the integrated circuit to have an additional connecting pin, and adds to the work of the manufacturer.
Furthermore, where the EEPROM has the functions of automatically erasing, writing, and performing verification, timer circuits or delay circuits having a time interval of about 3 to 5 msec are required to produce each control pulse. According to the prior art, since such timer circuits or delay circuits are formed by a continuously charged or discharged CR circuit consisting of a depletion mode transistor and a MOS capacitor in the MOS integrated circuit, the sizes of the depletion mode transistor and MOS capacitor become very large. Particularly, the size of the MOS capacitor becomes extremely large. For example, a timer circuit having a time interval of 3 msec requires a depletion mode transistor having a size of about W/L=5 pm/500 pm and a MOS capacitor having a size of about W/L=500 pm/500 um, where W indicates a channel width and L indicates a channel length of the MOS transistor.
It is therefore an object of the present invention to provide a semiconductor timer which can be constructed in a MOS integrated circuit in a small size.
DE-A-2720492 describes a circuit which produces signals of an amplitude greater than the amplitude of a given periodic signal and which includes a first capacitor; a charge circuit connected to the first capacitor for charging the first capacitor; and a discharge circuit connected to the first capacitor for discharging the first capacitor, the discharge circuit including a transistor connected to the first capacitor in parallel and having a gate. The circuit is used for delivering pulses to a load e.g. an IGFET transistor operating an alphanumeric display or dial of an electronic wristwatch.
According to this invention a semiconductor timer includes such a circuit and is characterised in that the discharge circuit also includes a second capacitor connected to the gate of the transistor, and a second transistor connected either between the gate of the first transistor and earth or to the terminal of the second capacitor opposite the terminal connected to the gate of the first transistor, the second capacitor receiving clock pulses and intermittently turning the transistor ON in response to the clock pulses to gradually discharge the first capacitor in response to the clock pulses and in that the timer includes means for monitoring a voltage across the first capacitor and applying a first electrical signal to the gate of the second transistor to enable the clock pulses to start the discharge operation of the discharge circuit.
In this way a long time interval can be set without increasing the size of the first capacitor. For example, a timer having a time interval of about 3 msec can be constructed with a MOS capacitor having a size smaller than W/L=50 pm/ 50 µm.
The semiconductor timer according to the present invention is useful to set an erasing time period and writing time period of an EEPROM, or to set a time interval of several msec for another job, especially in a computer system.

Figure 1a is a circuit diagram of a discharge circuit used in the present invention;
Figure 1 b is an equivalent circuit diagram of the diagram shown in Figure 1a;
Figure 1c is a wave-form diagram illustrating a relationship between clock pulses and gate voltage;
Figure 2 is a circuit diagram of an embodiment of the present invention;
Figure 3 is a wave-form diagram illustrating an operation of the embodiment shown in Figure 2;
Figure 4 is a circuit diagram of a part of a discharge circuit used in the present invention;
Figure 5 is a circuit diagram of another embodiment of the present invention;
Figure 6 is a wave-form diagram illustrating an operation of the embodiment shown in Figure 5;
Figure 7 is a circuit diagram of a circuit for stabilizing the amplitude of the clock pulses; and
Figure 8 is a circuit diagram of a further embodiment of the present invention.

Figure 1a illustrates an example of a discharge circuit in a semiconductor timer of the present invention. In Figure 1a, reference symbol T_T denotes an enhancement mode transistor. The drain of the transistor T_T is connected to a node N_c whereto a first MOS capacitor (not shown) is connected. The source or the transistor T_T is grounded, and the gate of the transistor T_T is connected to one terminal of a second MOS capacitor T_c. The other terminal of the capacitor T_c is connected to a clock generator (not shown) to receive clock pulses from the clock generator. In response to the clock pulses, the second MOS capacitor T_c applies a voltage V_c, which is higher than the threshold voltage V_th of the enhancement mode transistor T_T, to the gate of the enhancement mode transistor T_T. Thus, the transistor T_T is intermittently turned on to gradually discharge the first MOS capacitor.
Figure 1 b illustrates an equivalent circuit of the discharge circuit shown in Figure 1a. Equivalent capacitors C_TC and C_TT correspond to the second MOS capacitor T_c and the transistor T_T, respectively. A relationship between the clock pulses and the voltage V_G at the gate of the enhancement mode transistor T_T is as shown in Figure 1c. The capacitances C_TC and C_TT of the equivalent capacitors C_TC and C_TT shown in Figure 1b are defined as

where s_ox is the relative permittivity of the gate oxide layer, so is the permittivity of free space, t_ox is the thickness of the gate oxide layer, L_TC and L_TT are the channel length of the transistor constituting the MOS capacitor T_C and of the enhancement mode transistor T_T, and W_TC and W_TT are the channel width of the above transistors. The voltage V_G at the gate of the enhancement mode transistor T_T when the clock pulses become the voltage V_cc is defined as
Therefore, the voltage V_G at the gate of the transistor T_T when the clock pulses become the voltage V_cc can be easily determined to a voltage higher than the threshold voltage V_th of the enhancement mode transistor T_T, by designing the channel length L_Tc and the channel width W_Tc of the MOS capacitor T_c to appropriate values.
The enhancement mode transistor T_T will be turned on when the clock pulses become the voltage V_cc, causing the charge in the first MOS capacitor to discharge very slowly. As a result, the size of the first MOS capacitor can be reduced.
Figure 2 illustrates an embodiment of the present invention, in which the discharge circuit shown in Figure 1a is used. In Figure 2, reference numeral 10 indicates a discharge circuit, and 20 indicates a charge circuit. The discharge and charge circuits 10 and 20 are connected to one terminal (node N_c) of a first MOS capacitor C₁. The other terminal of the first MOS capacitor C₁ is grounded. One terminal of each of the first and second comparators COM₁ and COM₂ is connected to one terminal (node N_c) of the first MOS capacitor C₁. The first comparator COM₁ compares the voltage V_NC at the node N_c with a constant reference voltage of 3 V, and the second comparator COM₂ compares the voltage V_NC with a constant reference voltage of 1 V. The output terminals of the first and second comparators COM₁ and COM₂ are connected to input terminals of a flip-flop FF of a negative edge trigger type, respectively. One output terminal (node N_D) is connected to the discharge circuit 10, and the other output terminal (node N_u) is connected to the charge circuit 20. The output of this timer is obtained, for example, from the node N_D. It is apparent that the output of the timer may be obtained from the node N_u. A transistor T₂ for resetting and starting the timer is connected in parallel with the first MOS capacitor C₁.
The discharge circuit 10 comprises a second MOS capacitor C₂ which corresponds to the second MOS capacitor T_c shown in Figure 1a, an enhancement mode transistor T₃ which corresponds to the transistor T_T in Figure 1a, a transistor T₄ connected between the gate of the transistor T₃ and the earth, and an inverter INV connected between the gate of the transistor T₄ and the node N_D.
The charge circuit 20 comprises a transistor T₁ connected between a voltage supply (not shown), for supplying the power supply voltage V_cc, and the node N_c. The gate of the transistor T₁ is connected to the node N_u.
Figure 3 illustrates wave-forms at various points in the embodiment shown in Figure 2. Hereinafter, the operation of the embodiment in Figure 2 will be described with reference to Figure 3.
During a reset condition, since the transistor T₂ is in an on state, the voltage V_NC at the node N_c, which voltage is equivalent to a voltage across the first MOS capacitor C₁, is zero (0 V). Therefore, the output of the first comparator COM₁ is "H" level (5 V) and the output of the flip-flop, namely the voltage V_NU at the node N_u, is also "H" level (5 V). As a result, the transistor T₁ is in an on state. Furthermore, since the voltage V_ND at the node N_D is "L" level, the transistor T₄ is in an on state and, thus, the transistor T₃ is maintained in an off state during the reset condition.
From the above reset condition, if a reset/start signal Reset/Start changes to "L" level (0 V) and thus the transistor T₂ is turned off, the charging operation of the first MOS capacitor C₁ starts. Namely, current is fed to the first MOS capacitor C₁ via the transistor T₁. Thus, the voltage V_Nc at the node N_c increases, as shown in Figure 3. When the voltage V_NC exceeds 3 V, the output of the first comparator COM₁ changes from "H" level to "L" level, causing the outputs V_ND and V_NU of the flip-flop FF to change from "L" level to "H" level and from "H" level to "L" level, respectively, as shown in Figure 3. As a result, the transistor T₁ is turned off and the transistor T₄ is turned off, causing the discharging operation of the first MOS capacitor C₁ to start. Namely, since the transistor T₁ is turned off, the charging operation of the first MOS capacitor C₁ will stop. On the other hand, since the transistor T₄ is off, the voltage V_G at the gate of the transistor T₃ momentarily increases each time a clock pulse having a predetermined frequency is applied to the second MOS capacitor C₂, causing the transistor T₃ to intermittently turn on in response to the clock pulses. Therefore, the first MOS capacitor C₁ is gradually discharged.
When the voltage V_NC decreases lower than 1 V, the output of the second comparator COM₂ changes from "H" level to "L" level, causing the outputs V_ND and V_NU of the flip-flop FF to change from "H" level to "L" level and from "L" level to "H" level, respectively. As a result, the transistor T₁ is turned on to start the charging operation with respect to the first MOS capacitor C₁, and the transistor T₄ is turned on to ground the gate of the transistor T₃, causing the transistor T₃ to be maintained in an off state.
According to the above embodiment, the voltage V_NC across the first MOS capacitor C₁ gradually changes between +3 V and +1 V. Thus, a long time interval of 3 msec can be obtained for the charging and discharging operations by using a first capacitor C₁ having a small size of about W/ L=50 µm/50 pm.
Figure 4 illustrates a part of another example of the discharge circuit 10 in Figure 2. In this example, a transistor T₄' is inserted between the second MOS capacitor C₂ and the clock generator (not shown), instead of between the transistor T₄ and the inverter INV in the circuit shown in Figure 2. During a reset condition and charging operation, the transistor T₄' is off, and the clock pulses are not applied to the second MOS capacitor C₂, causing the transistor T₃ (Figure 2) to be maintained in an off state.
Figure 5 illustrates another embodiment of the present invention, in which the discharge circuit 10 in Figure 4 is used, and a charge circuit 20' different from that shown in the embodiment in Figure 2 is used. Furthermore, in this embodiment, a high voltage Vpp is used for charging the first MOS capacitor C₁.
The charge circuit 20' is composed of a charge pump circuit which comprises a third MOS capacitor C₃ and transistors T₅, T₆, and T₇. The gate and drain of the transistor T₇ and the source of the transistor T₆ are connected to one terminal of the third MOS capacitor C₃. The other terminal of the third MOS capacitor C₃ is connected to the clock generator (not shown) to receive the clock pulses. The source of the transistor T₇ and the gate of the transistors T₆ are connected to the node N_c. The drain of the transistor T₆ is connected to the source of the transistor T_s, and the gate and drain of the transistor T₅ are connected to a line for supplying a high voltage Vpp of about 19 V. To the first comparator COM_i, a constant reference voltage (Vpp-3) V which is about 16 V is applied. In other respects this embodiment is the same as that of the embodiment shown in Figure 2.
Figure 6 illustrates waveforms at various points in the embodiment in Figure 5. Hereinafter, the operation of the embodiment in Figure 5 will be explained with reference to Figure 6.
In response to the clock pulses, the voltage at the gate of the transistor T₇ momentarily increases and thus the transistor T₇ is intermittently turned on, causing a small charge from the line supplying the high voltage Vpp to be pumped into the first MOS capacitor C₁. Therefore the first MOS capacitor C₁ is gradually charged, as shown in Figure 6. For example, the first MOS capacitor C₁ is charged by △Q₁ in response to the clock pulse. When the voltage V_Nc exceeds (Vpp-3) V, which may be equal to 16 V, the output of the first comparator COM₁ changes from "H" level to "L" level, causing the output V_ND of the flip-flop FF to change from "L" level to "H" level, as shown in Figure 6. As a result, the transistor T₄' is turned on, causing a discharging operation of the first MOS capacitor C₁ to start. The first MOS capacitor C₁ is discharged by △Q₂ in response to the clock pulse by the discharge circuit 10, and is charged by △Q₁ in response to the clock pulse by the charge circuit 20'. Since the circuit is designed so that △Q₂>△Q₁, the first MOS capacitor C₁ in fact is discharged by △Q₂-△Q₁ in response to the clock pulse. Otherwise operation of this embodiment is the same as that of the embodiment shown in Figure 2.
According to the above embodiment, since the charge voltage is high (19 V), a MOS capacitor having a smaller capacitance than that in Figure 2 can be used for forming the timer having the same time interval. Furthermore, since not only the discharging operation but also the charging operation are executed very slowly, by intermittently turning on the transistor for transmitting charge, a timer having a longer time interval than that in Figure 2 can be formed.
In the aforementioned embodiments, however, if the supply voltage V_cc varies, the amplitude of the clock pulses will change, causing the time interval of the timer to change. Figure 7 illustrates an example of a circuit for preventing the above problem from occurring. In this example, a transistor T₈ is inserted between a clock generator 30 and the charge and/or discharge circuits, and a constant voltage of, for example, 4 V, is supplied to the gate of the transistor T₈. Therefore, the amplitude of the clock pulses is always maintained at a voltage of (4-V_th) V irrespective of any change in V_cc, where V_th is a threshold voltage of the transistor T_s.
Figure 8 illustrates a further embodiment of the present invention. This embodiment also prevents the above-mentioned problem from occurring. In this embodiment, variable reference voltages are applied to the first and second comparators COM₁ and COM₂. The variable reference voltages are produced by dividing the power supply voltage V_cc by means of resistors R₁, R₂, and R₃ connected in series to each other. Therefore, the voltage V_NC for switching between the charging and discharging operations changes depending upon the power supply voltage V_cc, causing the change in time periods of the charging operation and the discharging operation owing to the charge in the V_cc to be reduced. Otherwise, the constitution and operation of the embodiment shown in Figure 8 are the same as the those of the embodiment in Figure 2.

Claims

1. A semiconductor timer including: a first capacitor (C₁); a charge circuit (20, 20') connected to the first capacitor (C_i) for charging the first capacitor (C_l); and a discharge circuit (10) connected to the first capacitor (C₁) for discharging the first capacitor (C₁), the discharge circuit (10) including a first transistor (T₃) connected to the first capacitor (C₁) in parallel and having a gate; characterised in that the discharge circuit also includes a second capacitor (C₂) connected to the gate of the first transistor (T₃), and a second transistor (T₄, T'₄) connected either between the gate of the first transistor (T₃) and earth or to the terminal of the second capacitor (C₂) opposite the terminal connected to the gate of the first transistor, the second capacitor (C₂) receiving clock pulses and intermittently turning the first transistor (T₃) ON in response to the clock pulses to gradually discharge the first capacitor (C₁) in response to the clock pulses and in that the timer includes means (COM₁, FF) for monitoring a voltage across the first capacitor (C₁) and applying a first electrical signal to the gate of the second transistor (T₄, T'₄) to enable the clock pulses to start the discharge operation of the discharge circuit (10).

2. A semiconductor timer as claimed in claim 1, wherein the monitoring means (COM₁, COM₂, FF) also produces a second electrical signal used for starting the charging operation of the charge circuit (20, 20').

3. A semiconductor timer as claimed in claim 2, wherein the monitoring means includes means (COM₁, COM₂, FF) for judging whether the voltage across the first capacitor (C₁) becomes higher than an upper limit voltage and for judging whether the voltage across the first capacitor (C₁) becomes lower than a lower limit voltage.

4. A semiconductor timer as claimed in claim 3, wherein the judging means (COM₁, COM₂, FF) includes: a first comparator means (COM,) for comparing the voltage across the first capacitor (C₁) with the upper limit voltage; a second comparator means (COM₂) for comparing the voltage across the first capacitor (C₁) with the lower limit voltage; and a bistable means (FF) connected to the first and second comparator means (COM₁, COM₂) for producing the first and second electrical signals in response to the outputs from the first and second comparator means (COM₁, COM₂).

5. A semiconductor timer as claimed in claim 2, 3 or 4 wherein the charge circuit (20) includes a third transistor (T,), connected in series with the first capacitor (C₁), and wherein the second electrical signal is applied to the gate of the third transistor (T₁) to turn the third transistor (T₁) ON to apply a power supply voltage to the first capacitor (C_l).

6. A semiconductor timer as claimed in claim 1, wherein the charge circuit (20') includes a third transistor (T₇) connected in series with the first capacitor (C₁), and a further capacitor (C₃), the further capacitor (C₃) receiving clock pulses and intermittently turning the third transistor (T₇) ON to charge the first capacitor (C₁) in response to the clock pulses.

7. A semiconductor timer as claimed in claim 6, wherein the charge circuit (20') is operative during both charging and discharging of the first capacitor (C₁) and the discharge circuit (10) is operative only during discharging of the first capacitor (C₁), the increment of discharge per clock pulse being greater than the increment of charge per clock pulse.