EP0112912A1 - Bus de canaux d'entree/sortie - Google Patents

Bus de canaux d'entree/sortie

Info

Publication number
EP0112912A1
EP0112912A1 EP83902485A EP83902485A EP0112912A1 EP 0112912 A1 EP0112912 A1 EP 0112912A1 EP 83902485 A EP83902485 A EP 83902485A EP 83902485 A EP83902485 A EP 83902485A EP 0112912 A1 EP0112912 A1 EP 0112912A1
Authority
EP
European Patent Office
Prior art keywords
bus
data
register
transfer
channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP83902485A
Other languages
German (de)
English (en)
Other versions
EP0112912A4 (fr
Inventor
Kenneth Holly
Gehrard Jim Smith
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Elxsi
Original Assignee
Elxsi
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US06/426,045 external-priority patent/US4564899A/en
Application filed by Elxsi filed Critical Elxsi
Publication of EP0112912A1 publication Critical patent/EP0112912A1/fr
Publication of EP0112912A4 publication Critical patent/EP0112912A4/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G06F13/26Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/36Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4217Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with synchronous protocol

Definitions

  • This invention relates generally to data proces- sing systems, and more specifically to a sub-bus system through which a plurality of peripheral controllers may communicate with other functional units in the overall system.
  • a typical computer system includes a number of peripheral devices (hereinafter often referred to as “pe ⁇ ripherals” or “devices”) that provide mass storage for the system and allow communication outside the system.
  • peripherals include disk drives, tape drives, terminals, a the like.
  • the peripherals typically operate on a time scale that is at least an order of magnitude slower than the operation of other functional units within the system. While it is a known practice to interface peripher al controllers directly to a main system bus, this typicall requires a large amount of overhead associated with each peripheral controller.
  • IOCP intelligent I/O channel processo
  • the peripheral sub-bus will often be referred to simply as the "bus.”
  • Directions on the bus will be designated relative to the IOCP, with terms such as “transmit” and “outbound” referring to communications from the IOCP and terms such as “receive” and “inbound” referring to commu ⁇ nications to the IOCP.
  • addresses are responsible for identification of the data destination, including both the specific device as well as the actual data location within it.
  • the most common prior art system adds separate address lines to the bus and assigns them to the addressing function. This adds to the cost of the bus medium but offers the ability to select individual addresse for each bus operation.
  • Other systems transmit address information on the data bus in a time shared manner. This typically requires extensive control to ensure that the additional burden on the data section does not slow the entire bus down.
  • the present invention provides a very fast bi- directional data bus system that makes highly efficient us of both the bus medium and bandwidth.
  • the invention utilizes a set of tag lin separate from the bi-directional data lines to implement a system of logical transfer channels.
  • a system of logical transfer channels There are a relativel small number of transfer channels (say four) that may be attached or detached by the IOCP to meet the data flow requirements.
  • the system of logical transfer channels provides high data rates (even over long distances) and goo error detection.
  • the basic function of a transfer channel is to enable temporary assignment of some portion of the bu resource to a specific device and then to allow simple. quick addressing of that device by reference to that chan ⁇ nel.
  • the IOCP For a transfer to occur between the IOCP and a device, the IOCP first effects an "attach" operation to assign the device a transfer channel for the duration of t transfer. Thereafter, the IOCP allocates the bus cycles among the currently attached transfer channels according to any desired priority scheme, subject to the constraint that the device on a transfer channel be ready to send or receiv data before that transfer channel may be granted cycles. I one embodiment, all the devices are connected to a plurali of "channel ready" lines corresponding to the plurality of transfer channels. The IOCP effects the attach operation b direct addressing of the device to give it the channel number and to establish a base address for sequential accesses within the device. Thereafter, the device request bus cycles by asserting the appropriate channel ready line.
  • the IOCP responds by placing the binary code responding to the requesting device's transfer channel on the tag lines, signifying that the next bus operation will be a data transfer with respect to that channel.
  • the device may be assumed ready at all times. Such a device need not be connected to the "channel ready" lines, so long as the IOCP knows that such a device, once assigned a transfer channel, is always ready to send or receive data
  • Data transfers occur in units (or "bursts") of a predetermined number of bus words (for example, four 16-bit words) .
  • Each bus interface includes a staging area to contain or receive four words in sequence so that these words may be transferred on or off the bus at the maximum bus speed regardless of the speed of the device.
  • the devic only asserts the channel ready line when it has four words in its staging registers and is thus ready to transmit, or has its staging registers empty and is thus ready to re ⁇ ceive.
  • four words are moved or from the device at the. maximum speed of the bus. Data transfers longer than the four-word data unit occur over a series of such four-cycle bursts.
  • trans fer channels may have been allocated four-cycle blocks in the interim.
  • the channel i detached from the device and made available to other de ⁇ vices.
  • the system of logical transfer channels allows each device to run at its own speed during transfers while allowing the bus to run at its maximum speed. Since the data direction is established during the attach operation, the direction is thereafter implied by the IOCP's issuance of tags, representing a further reduction in control over ⁇ head.
  • the system provides a simple priority scheme by allowing the channel tags to be given in any order, and provides needed flexibility and time sharing through the u of the same mechanisms. Multiple, simultaneous transfers are easily interleaved through the use of the transfer channels, without requiring any complicated overhead to interleave the addresses.
  • the invention thus operates according to a syn ⁇ chronous pipelined control sequence initiated by the IOCP with the tag used by all controllers to define activities for the next cycle.
  • This differs from the most common asynchronous type of bus structure that relies on the exchange of "handshake" signals on the bus to execute and monitor the progress of an exchange of information. While it is a simple task to monitor the sequence of handshake signals in an asynchronous system,-many such systems cannot distinguish between single and plural units since the sequence of the handshake signals would appear correct in either case.
  • the present invention provides selection circuitr to allow the IOCP to determine whether a sequence is pro ⁇ ceeding properly.
  • the selection circuitry comprises a
  • OMPI signal source at each device, a monitor at the IOCP, and a common select line to which the sources and monitor are coupled.
  • the signal source includes elements responsive t the tag and timing signals, and a constant current source coupled to the select line.
  • the monitor at the IOCP in ⁇ cludes a tag decoder and a voltage reference.
  • all devices examine the tag information to determine if the specified tag is uniqu to an individual device. If a device determines that it i being addressed uniquely, it conditions its current source to control the select line. This causes a predetermined amount of current to flow, thus allowing the IOCP to disti guish the situation of no controllers, a single controller, and multiple controllers being selected.
  • the IOCP issu tags on the tag lines, it maintains a pipeline of expected responses for the selection signals. A disagreement betwe the actual and expected conditions of the select lines signifies a selection error.
  • the selection circuitry further includes a history shift register in each device. At the time a device determines how to condition its current source, it also places a code representative of this deter mination in its history shift register.
  • the IOCP detects an error condition, it issues a global tag, desig ⁇ nated the "lock" tag, that causes all controllers to freez the state of their selection history registers to enable t IOCP to determine the source of the error. Reading the history register causes it to unlock so that it may begin again to reflect the true selection history of the device with respect to tags on the bus.
  • FIG. 1 is an overall block diagram of a computer system illustrating the I/O channel bus
  • Fig. 2A is a block diagram of one of the periphe al controller front ends
  • Fig. 2B is a block diagram illustrating the mann in which the controller front ends are coupled to the I/O channel bus;
  • Fig. 3 is a timing diagram of the clock signals the IOCP
  • Fig. 4 is a schematic of the clock input circuit within a peripheral controller port
  • Fig. 5 is a timing diagram of clock signals at t port
  • Fig. 6A is a schematic of the input and data staging circuitry within the port
  • Fig. 6B is a schematic of the output circuitry within the port
  • Fig. 7 is a schematic of the tag decoding circui ry within the port
  • Fig. 8 is a schematic of the circuitry within th port for identifying register operations
  • Fig. 9 is a timing diagram of the register write signals
  • Fig. 10 is a schematic of the port's attention register
  • Fig. 11 is a schematic of the port's pointer register
  • Fig. 12 is a schematic of the port's activity register
  • Fig. 13 is a schematic of the port's DMA address and control registers
  • Fig. 14 is a schematic of the circuitry within th port for driving the ready bus
  • Fig. 15 is a schematic of the circuitry within th port for driving the select line
  • Fig. 16 is a schematic of the port's status register
  • Fig. 17 is a schematic of the circuitry within t port for driving the error line
  • Fig. 18 is a schematic of the circuitry within t port for decoding the mask
  • Fig. 19 is a schematic of the port's end status register
  • Fig. 20 is a schematic of the port's wrap regis- ters
  • Fig. 21 is a schematic of the port's side contro register
  • Fig. 22 is a schematic of circuitry withing the port for initiating extended mode operation
  • Fig. 23 is a schematic of maintenance control circuitry that is shared between the two ports in a contro ler front end;
  • Fig. 24 is a block diagram of the SBA
  • Figs. 25A and 25B are timing diagrams illustrati the sequence of signals between the SBA and the IOCP's ALU;
  • Fig. 26 is a schematic of clock distribution circuitry in the SBA
  • Fig. 27 is a timing diagram of clock signals in the SBA
  • Fig. 28 is a schematic of clock driving circuitr within an SBA sub-bus interface
  • Fig. 29 is a schematic of data and tag output circuitry within the SBA sub-bus interface
  • Fig. 30 is a schematic of input circuitry within the SBA sub-bus interface.
  • Fig. 31 is a schematic of circuitry within the S sub-bus interface for sensing the select line.
  • Fig. 1 is a block diagram of a representative computer system on which the present invention may be implemented.
  • the computer system comprises a central processing unit (CPU) 10, a service processor (SVP 12, a memory controller (MC) 13, and an I/O channel proces sor (IOCP) 15, all of which communicate on a system bus 17 with bus arbitration being carried out by a bus control un (BCU) 18.
  • CPU 10 includes a cache/TLB (translation look ⁇ aside buffer) and an arithmetic logical unit (ALU) , and further communicates with a floating point accelerator (FPA) .
  • Service processor 12 is used for initialization an reconfiguration of the computer system.
  • Memory controller 13 communicates with memory units.
  • IOCP 15 includes a cache/TLB 20, an ALU 22, and a sub-bus adaptor (SBA) 23.
  • SBA 23 is coupled to two I/O sub-buses 25 and 27 and communicates via one or both of the sub-buses with a plurality of peripherals, 30a and 30b being shown.
  • the peripherals are spatially distributed over a significant area so that sub-buses 25 and 27 are relatively long (per ⁇ haps 50' or 100'), extending to respective terminator unit 31 and 32.
  • Each peripheral includes a device 33 (which ma be a tape drive, a disk drive, or the like), an appropriat device controller 34, and a controller front end (sometime called a "CFE") 35 which communicates with controller 34 v a set of data and control lines 36.
  • controller front en 35 has two ports 37 (sometimes referred to as the A and B ports) which couple to respective sub-buses.
  • ports 37 are coupled to sub-buses 25 and 27 but this is not necessary.
  • peripheral 30b is shown as having one of its ports coupled to sub-bus 25 and the other coupled to a sub-bus 27' from another IOCP (not shown) .
  • up to sixteen ports may be coupled to a given sub-bus.
  • Each port is provided with switches to allow the unit number to be defined.
  • Fig. 2A is a block diagram illustrating the major components and communication paths within controller front end 35. Only one port is shown.
  • each port includes clock receiving circuitry, data handling circuitr control circuitry, and a variety of registers.
  • Controller front end 35 also includes control circuitry common to bot ports.
  • the controller front ends are implemented in TTL logic; the particular structure and operation of the various components will be described in detail below with reference to various circuit schematics.
  • the circuit schematics are drawn in a somewhat simplified format. Par numbers are shown in an abbreviated notation with an apos- trophe signifying the omission of the family designator
  • control ler 34 While the nature of an individual device control ler 34 will depend on the nature of the device or devices with which it communicates, the controller front end 35 is the same for all peripherals. It is assumed that controll 34 includes sufficient intelligence and appropriate inter ⁇ face circuitry to communicate on lines 36.
  • the present invention relates to th ⁇ manner in which bus cycles on sub-buses 25 and 27 are allocated amon the devices in order to optimize bus utilization.
  • sub-buses 25 and 27 may be considered substantially the same, and further, the two ports within a given controller front end 35 may be considered the same. Accordingly, much of the discussion that follows will be in terms of a single sub-bus and a single port within controller front end 35.
  • a given sub-bus will usually be referred to simply as a "bus except when required to distinguish it from system bus 17.
  • Fig. 2B is a schematic illustrating the signal paths on which data, control signals, and timing signals a communicated between SBA 23 and controller front end 35.
  • Bus 25 includes a data bus 40, a ready bus 41, a tag bus 42, a select line 43, an interrupt line 44, a firs clock line 45 (TCLK) , a second clock line 47 (RCLK) , a fir frame line 50 (TFRM) , a second frame line 52 (RFRM) , and a error line 53. All the signals on bus 25 (except select) are driven and received by 26S10 open collector quad bus transceivers.
  • Data bus 40 includes lines for sixteen data bits and two parity bits. The parity bits are used to maintain an odd number of bits in each of two groups of eight data bits. In general, the parity of the data bus will be correct, although there are some conditions in which the parity cannot be properly controlled, such as during the poll activity data response cycle to be discussed below.
  • Ready bus 41 includes four lines which correspon to four logical transfer channels.
  • a device operating in the block transfer mode may be attached to any one of the four transfer channels.
  • the IOCP responds t the request by issuing an appropriate tag to grant that transfer channel four consecutive bus cycles sufficient fo the burst.
  • a device that is capable of moving data faster than the bus rate need not use ready bus 41, but rather may be assumed by the IOCP to be ready.
  • Tag bus 42 includes four tag lines, two I/O statu (IOS) lines, and a parity line, and is used to define bus operations.
  • the tag field is used primarily to define the next bus cycle, but also has extended uses as defined by th IOS bits.
  • Select line 43 is controlled by any unit which is involved with a bus cycle, and thus provides an indication whether no units, one unit, or more than one unit has been selected.
  • Interrupt line 44 may be driven by any device tha both has its activity bit set and is allowed to interrupt based on a previously distributed mask.
  • the interrupt line is not used for data transfer (that is the function of read bus 41) , but rather is used to initiate a communication, that is, to start a transfer. The state of the line tells
  • OMPI the IOCP that some device needs service.
  • the IOCP uses th poll activity tag to determine which device.
  • Error line 53 is driven by any device at any tim to inform the IOCP that something is broken. Whenever a controller detects a hardware failure that would inhibit i from proper functioning, it asserts the error line and provides error information in its own status register. In response to the error signal, the IOCP can determine which device on the bus has a problem by reading each device's status register.
  • Data bus 40 is bi-directional in that it may be driven either by SBA 23 or by port 37.
  • Tag bus 42 is only driven by SBA 23.
  • Ready bus 41, selec line 43, interrupt line 44, and error line 53 are driven b the ports. The above lines are resistively terminated at terminator unit 31.
  • TCLK line 45 and TFRM line 50 are driven by SBA and extend to terminator unit 31 where they are resistivel terminated.
  • RCLK line 47 comprises a pair of segments 47(out and 47(in) which are connected at terminator unit 31.
  • the RCLK signal is driven by SBA 23 on segment 47(out) , propa ⁇ gates away from the SBA toward terminator unit 31 where it is turned around and propagates back toward SBA 23 along segment 47(in). Segment 47 (in) is resistively terminated SBA 23.
  • Port 37 is coupled to RCLK segment 47 (in), but no segment 47 (out) .
  • RFRM line 52 similarly comprises a pair of seg ⁇ ments 52 (out) and 52(in) which are connected at terminator unit 31 with port 37 being coupled to RFRM segment 52(in).
  • the primary function of the peripheral system is to move data, and as such, the most basic mode of operatio is the block data transfer mode.
  • Four interleaved data transfers (corresponding to four logical transfer channels may be supported on each sub-bus.
  • rSrE transfer data.
  • the state of tag bus 42 is interpreted by the controller front ends as defining what is to occur on the following bus cycle, and tells the ready device when i is to be granted bus cycles. Data transfers on the bus occur in 4-word units bursts, each of which occupies the bus for four successive bus cycles. There is no intrinsic significance to this number except that the sub-bus handles 16-bit words while system bus 17 handles 64-bit words.
  • the other basic mode is the register transfer in which the IOCP writes into or reads from one of several registers in a device. The significance of the particular registers will be described later, it sufficing for the moment to note that these registers provide a variety of control and status information. Various register operatio must take place before a device is assigned a transfer channel.
  • Fig. 3 is a timing diagram of the TFRM, TCLK, RFRM, and RCLK signals as generated at SBA 23.
  • the sub-bus cycle is 250 ns (by way comparison, system bus 17 operates with a 25-ns cycle) .
  • TCLK is a continuous stream of pulses with leadi edges at 250 ns intervals to define the bus cycles and tim transfers from the IOCP to the device.
  • the TCLK pulses ar 100 ns in duration.
  • TFRM is asserted for 100 ns substan ⁇ tially coincident with the TCLK pulse of the bus cycle (N-l immediately preceding the first cycle of the 4-cycle trans ⁇ fer.
  • TFRM is not asserted again (to signify a new bus operation) until RFRM has cleared the bus.
  • TCLK runs continuously to time transfers from the IOCP to the device.
  • SBA 23 places data on the bus at a leading edge o TCLK while the port logic latches the data on the bus at th trailing edge of TCLK (points A, B, C, D) .
  • the SBA keeps
  • RCLK runs continuously at the same rate as TCLK t time transfers from the device to the IOCP.
  • the leading edge of the RCLK pulses .lags the trailing edge of the TCLK pulses by a 100-ns interval.
  • RFRM is asserted for 100 ns substantially coincident with the next RCLK pulse following the assertion of TFRM.
  • the relative timing between (TCLK, TFRM) and (RCLK, RFRM) differs for devices distributed alon the bus, since the TFRM and TCLK signals are communicated t the devices directly while the RFRM and RCLK signals must b turned around at terminator unit 31.
  • th relative timing is substantially as shown for a device that is located near the terminator unit but the relative delay increases for a device that is located between the IOCP and the terminator.
  • the lag of 100 ns (or more) between the trailing edge of TCLK and the leading edge of RCLK is neede to allow the device most remote from the IOCP enough time t ascertain that it is to place data on the bus and generate the appropriate control signals.
  • the port logic places the first data word on the bus at the leading edge of the RFRM (point A') and removes the last data word slightly after th trailing edge of the 4th RCLK (point B').
  • SBA 23 latches the data at the trailing edge of RCLK (points A", B", C", and D”) .
  • Cycle N-l is the tag cycle which signifies that the following two cycles are to be dedicated to a bus operation
  • Cycle N is the ID cycle during which the unit number, the register number, and the direction of the register transfer are placed on the data bus.
  • Cycle N+l is the cycle during which the data is read from or written into the register previously identified.
  • the IOCP may see that following bus cycle before the response data has propagated back to the IOCP.
  • the RCLK signal overcomes part of this problem since each device latches the bus data at a pre ⁇ determined time relative to TCLK (trailing edge) , and place its * *response data on the bus at a predetermined time rela ⁇ tive to RCLK (leading edge) . Propagation delays can still result in cycle identification confusion.
  • TCLK and RCLK are in almost the same phase relationship as they are at the IOCP.
  • the TFRM and RFRM signals solve the cycle mis- identification problem in a manner that avoids the above undesirable alternatives.
  • the TFRM an RFRM signals provide variable frame cycles controlled in such fashion as to prevent more than one frame being on th bus at any one time.
  • the fixed clock cycles are used to move the data.
  • This system is fully synchronous in nature, with all timing and reference ele ⁇ ments being originated by and therefore referenced to the IOCP master clock. This helps to prevent any metastable data state caused by data changing at a time when it is being sampled or evaluated.
  • Fig. 4 is a circuit schematic of clock receiver circuitry 58 within port 37.
  • TCLK, TFRM, RCLK, and RFRM a communicated to respective receivers 60.
  • the outputs of t TCLK, RCLK, and RFRM receivers are communicated through inverting and non-inverting buffers 62 to provide positive and negative local signals, designated ⁇ TC, ⁇ RC, and ⁇ RF.
  • the outputs of the TFRM and TCLK receivers are communicate to AND and NAND gates 63 to provide local signals ⁇ TF that are more precisely synchronized with the ⁇ TC signals.
  • the TCLK receiver output is also passed through a delay circui 65 to produce a delayed local clock signal -TCD.
  • -TF signal is gated with -TCD to provide delayed local frame signals ⁇ TFD.
  • Fig. 5 is a timing diagram for the above described local timing signals. Only the positive signal shown if both positive and negative signals are provided.
  • Figs. 6A and 6B taken together, provide a logic schematic of the data handling circuitry within port 37.
  • This circuitry includes input circuitry 80, input data staging circuitry 82, output data staging circuitry 85, an output circuitry 87.
  • th tag decoding circuitry generates signals -XW and -XR, signifying a write to or a read from the device.
  • Data staging is required since data transfers occur in 4-word bursts that occupy 4-cycle intervals. Therefore, transfers from the IOCP to the device are only allowed to occur when input staging circuitry 82 is prepar to receive four words into its registers. Similarly, transfers from the device to the IOCP are only allowed to occur when output staging circuitry 85 has four words in i registers and is prepared to transfer these words onto the bus on successive bus cycles.
  • the staging circuitry commu nicates with controller 34 via communication lines 36 whic include data lines 90 (XDATA) , address lines 92, load and unload lines 93, and parity lines 95. Lines that are shar with the other port are marked with an asterisk.
  • Data input circuitry 80 includes receivers 100, latches 102, and parity checking circuitry 103.
  • Latches 1 are controlled by the +TC signal to place the data on internal data lines 105, designated LDIN.
  • Latches 102 are transparent until the trailing edge of +TC, at which point LDIN lines 105 are held for the duration of the cycle. Th transparency allows the incoming data to be communicated t control circuits for the register operation (to be describ below) which are thereby afforded additional time to decod the data.
  • Input staging circuitry 82 includes an array of 4-by-4 register files 110, the data inputs of which are coupled to LDIN lines 105, and the data outputs of which ar coupled to XDATA lines 90.
  • the loading of register files 110 is controlled and timed by signals derived from TCLK and TFRM.
  • the control circuitry includes a counter 115, the output of which controls the register file input address.
  • the data o LDIN are latched into the register files at the trailing edge of +TC and the counter is incremented at the trailing edge of -TCD.
  • the resetting and incrementing of counter 11 are controlled by flip-flops 117 and 118, the first of whic
  • OMPI has the control signal -XW as generated by the tag decodin circuitry at its data input and is clocked by the trailing edge of -TFD.
  • TFRM actually -TFD
  • TCLK times the loading.
  • the transfer of data out of register files 110 to the controll is under the control of the controller and occurs in what ⁇ ever sequence at whatever rate is appropriate for that controller.
  • one of lines 93 controls the output enable of the register files 110 while address line 92 control the output address.
  • Output data staging circuitry 85 includes an arr of 4-by-4 register files 120, the data inputs of which ar coupled to XDATA lines 90, and the data outputs of which a coupled to lines 122, designated DOUT and POUT.
  • the transfer of data from the controller into register files 120 is under the control of the controller means of lines 92 and 93 in analogy to the transfer from register files 110 to the controller.
  • the output addressing of register files 120 is controlled and timed by signals derived from RCLK and RFRM.
  • the control circuitry includes a counter 125 which is incremented at the trailing edge of +RC.
  • the resetting of counter 125 is controlled by a flip-flop 127 which has the control signal -XR at its data input and is clocked by the leading edge of +RF.
  • a flip-flop 128 with the same clock and data inputs generates a +HOLD signal which is asserted by the leading edge of RF and removed when counter 125 has counted four cycles.
  • the output on lines 122 is communicated to outpu circuitry 87 (shown in Fig. 6B) which includes output latches 130 and bus drivers 132.
  • a set of output data line 133 (designated RDATA) communicates the output data to latches 130.
  • a number of control registers, designated collectively 134, are also coupled to RDATA lines 133.
  • Bus drivers 132 are gated by a signal controlled by flip-flops 135 and 137.
  • Flip-flop 135 is se at the leading edge of +RF, and keeps drivers 132 enabled during the 4-cycle transfer.
  • the +HOLD signal keeps flip- flop 137 reset, but when +HOLD is removed, flip-flop 137 c then be set at the next -RC trailing edge, which closes th gate to the drivers.
  • the last data word is removed from the bus at the trailing edge of +RC (actually later b some gate delays).
  • the data at SBA 23 is valid at t trailing edge of RCLK which is slightly earlier.
  • the state of tag bu 42 is used to define the bus activity that is to occur ove the next cycle or group of cycles.
  • the tag definitions an control signal mnemonics for the various hexadecimal state of the tag bus are tabulated below.
  • the IOS bits are used to further define how the tag bits are to be used by the controller.
  • both IOS bits are zero (a high level on the actual bus lines) , in which case the tag field is interpreted normally according to the table set forth above
  • the IOS lines provide two extensions where the tag field carries the unit address of the peripheral controller to be affected.
  • One extended mode is used to write into the shared unit control register of the controller front end while the other extended mode is used for enabling the receivers and inhibiting the drivers (that is, "evicting" a port from the sub-bus) .
  • the other extended mode is used for enabling the receivers and inhibiting the drivers (that is, "evicting" a port from the sub-bus) .
  • - JRl3 tag defines the activity that is to occur on the following cycle(s), the tag field in the extended modes describes activity that is to happen during the present bus cycle.
  • Fig. 7 is a schematic of circuitry 150 for decod ing the tag and IOS signals present on tag bus 42.
  • the circuitry includes receivers 152, parity checking circuitr 155, and the decoding circuitry proper.
  • a comparator 157 and a decoder 160 decode the tag information during the normal mode, and the results are communicated to flip-flop 165.
  • Flip-flops 165 are clocked on the trailing edge of - to provide the control signals tabulated above. This illustrates the manner in which the TFRM signal is used to validate the tag signal.
  • a comparator 166 provides a control signal +OSO indicating that the IOS lines specify extended mode for the particular unit. This will be dis ⁇ cussed below in connection with the shared maintenance controls. Register Operations
  • a register operation occupies the two bus cycles immediately following the cycl in which the tag is issued. These cycles are designated t definition cycle and the register transfer cycle.
  • the dat bus carries a unit identification field for the port, a register identification field for the relevant register, a a direction flag during the definition cycle.
  • the data bu carries the register data during the register transfer cycle.
  • Fig. 8 is a schematic of circuitry that decodes the information that is placed on the bus during the defin tion cycle to determine the particular register operation that is to be carried out.
  • the circuitry is operable to cause the registers tabulated below to be read from the po onto the bus. Also tabulated are the mnemonics of corre ⁇ sponding control signals generated by the circuitry.
  • circuitry of Fig. 8 is also operable to cause the following registers to be loaded from the bus.
  • a comparator 170 com ⁇ pares the 4-bit unit identification field of the data bus with the 4-bit UNIT code from the switches.
  • a gating network 172 senses the direction flag on the data bus to determine whether a register is to be read from the IOCP o written into by the IOCP during the following (register data) cycle.
  • Respective decoders 175 and 180 sense the register identification field on the data bus to generate the appropriate control signals for register reads and writes.
  • TFRM is asserted twice during a register opera ⁇ tion, namely during the tag cycle and again during the definition cycle.
  • a signal from gating network 172 specif ing a register read is clocked on the trailing edge of -TF during the definition cycle to generate a signal -RGR that remains active until the next trailing edge of -TF (that i until the next bus operation) .
  • the particular register re control signal remain asserted for a similar interval.
  • a signal -RGW is asserted at the trailing edge of -TF, and is clocked through to a gate 182 on the next leading edge of +TC which is the start of the
  • Gate 182 is also controlled by -TCD, so that the gate output goes high at the leading edg of -TCD (50 ns later) .
  • This allows a flip-flop 185 to sample the data parity error signal +DPE and clock a low level to enable decoder 180 on the next trailing edge of -TC.
  • the particular register write control signal is then asserted, until -TCD is removed 50 ns later.
  • Fig. 9 shows the timing for these control signals.
  • CFE - Register and Tag Description The following will describe the tags that are issued and the registers that are accessed in order to initiate and effect a communication between the IOCP and a subject port over one of the logical transfer channels.
  • T description will be in terms of the circuitry within the controller front end (primarily within the subject port) , and it will be assumed that the IOCP has sufficient intel ⁇ ligence to effect the sequence described.
  • the basic se ⁇ quence of tags and bus operations may be outlined as fol ⁇ lows.
  • the IOCP in a register operation, transfers an active channel word into the port's attention register.
  • the active channel word carries information that indicates to the controller that a communication is to occur.
  • the controller upon determining that a communication is to occur, constructs a 64-bit mini-message stores it, and places the 15-bit address of the mini-mes ⁇ sage in the port's pointer register. This causes an inter ⁇ rupt to occur.
  • the mini-message which may specify a "receive on channel” or “receive on funnel,” includes the 24-bit address of a message space and the buffer length.
  • the IOCP in order to determine which de ⁇ vice(s) is (are) driving the interrupt line, issues a poll tag.
  • the poll tag specifies a global channel operation wherein all controllers respond during the same bus cycle t provide the IOCP with activity status information.
  • the IOCP determines according to any desired priority regime that it will establish communication with a particular port, and, in a register operation, reads that port's pointer register. This removes the interrupt.
  • the IOCP in order to read the mini-message attaches a transfer channel by writing into the port's DMA address and control registers. In so doing, the IOCP assigns a transfer channel ID and specifies that the trans fer is to be from the controller, starting at the address that the IOCP had previously read from to pointer register
  • the controller loads output staging registe files 120 with the four words starting at the address that the IOCP had loaded into the DMA address register (that is it loads the mini-message) . Once this had been done, the controller causes the port to assert the ready line cor ⁇ responding to the attached transfer channel. 7. The IOCP issues a data transfer tag cor ⁇ responding to the attached transfer channel. During the following four cycles, the controller clocks the contents register files 120 onto the data bus as described in the portion relating to the data handling circuitry. 8. The IOCP, having received the mini-message, detaches the transfer channel and proceeds to act on the mini-message.
  • the IOCP attaches any available transfer channel (no necessarily the transfer channel previously used for the mini-message transfer) .
  • the IOCP specifies that the transfer is to be to the controller, starting at the address that had been provided in the mini-message.
  • the controller in order to receive the communication, clears input staging register files 110, and drives the ready line to signify that four words of the communication may be transferred on the bus during a four ⁇ cycle interval.
  • the IOCP in response to the ready signal, issues a data transfer tag corresponding to the attached transfer channel and places four words of data on the bus during the following four cycles (designated a "burst") .
  • Steps 10 and 11 are repeated as often as necessary for the complete data transfer to occur.
  • the transfer channel remains attached but other bus operations will generally occur between the four-cycle blocks.
  • t IOCP writes a completion code into the por ' s end status register and detaches the transfer channel.
  • the various registers and supporting circuitry will now be described in the order in which they are calle into play during the sequence outlined above.
  • th message passing sequence may be different under some circu stances (such as if the transfer is initiated by the devic rather than the IOCP)
  • the above sequence illustrates all the relevant principles. While the sequence of events tha occur prior to attaching the transfer channel appears at first glance to represent substantial overhead, it should remembered that a page of data comprises (in a representa- tive system) 256 8-byte words or 1024 bus words. Thus the set-up cost is relatively trivial compared to the 1024 bus cycles (256 bursts) that will be taken up in the transfer.
  • Fig. 10 is a schematic of attention register circuitry 200.
  • the circuitry communicates the da on LDIN lines 105 to a set of control lines 205 (to the controller) during the register data cycle in response to the -WATTN signal.
  • the circuitry includes flip-flops 207 having data inputs coupled to LDIN lines 10 and data outputs coupled to control lines 205.
  • Flip-flops 207 are clocked on the trailing edge of -WATTN.
  • the -WATT signal also sets a flip-flop 208, causing a signal ATTN IN to be communicated to the controller.
  • the output buffers flip-flops 207 are enabled by a signal RD ATTN from the controller.
  • Flip-flop 208 may be reset by a signal INT CL from the controller.
  • the actual significance of the activ channel word that is clocked onto control lines 205 relate to the overall computer system architecture, and is not pa of the present invention. It suffices to note that the active channel word carries information signifying that th IOCP has a message for the controller and desires to estab lish communication.
  • Fig. 11 is a schematic of pointer register cir ⁇ cuitry 210 and associated circuitry 212 for driving inter ⁇ rupt line 44. Broadly, circuitry 210 communicates the information on control lines 205 to RDATA lines 133 in response to the assertion of -RDPTR and activates interrup driving circuitry 212.
  • the circuitry includes flip-flops
  • the state of -REQINT is clocked at a trailing ed of ⁇ RC by a flip-flop 217 to define the port's activity bi
  • the activity is gated by a signal -INTA (interrupt allowed) generated by the mask circuitry to be described below.
  • Th interrupt signal is clocked through on the leading edge of +RF by a flip-flop 220, and communicated to a bus driver 22 whose output is coupled to interrupt line 44.
  • Fig. 12 is a schematic of activity register circuitry 230 that provides the information needed by the IOCP to determine which device(s) is (are) driving interrup line 44.
  • the activity register is actually a pseudoregiste in that each port controls only a predetermined one of the data lines.
  • the particular data line controlled is deter ⁇ mined by the 4-bit UNIT code.
  • the UNIT code is provided as the address input to a read only memory that generates an active level on the corresponding one of sixteen bits, so long as the activity bit is set.
  • Fig. 13 is a schematic of low order DMA address register circuitry 240, high order DMA address and control register circuitry 242, and common multiplex circuitry 245. Broadly, the DMA control and address registers are loaded during two register write operations. The result is to attach a transfer channel and provide a 24—bit address for the controller hardware as well as a number of control signals.
  • the low order DMA address information is loaded into a counter array 250.
  • the load input of counter array 250 is brought low when -XLDLO is asserted, and LDIN lines 105 ar loaded at the trailing edge of -XLDLO.
  • the trailing edge -XLDLO also causes the load input to be brought high, but only after the delay of a flip-flop 252.
  • counter 163 may be incremented by the assertion of a signa COUNT from the controller.
  • 8 bits of high order address information are loaded into a counter array 255 in a manner analagous to that described immediately above.
  • 8 bits of control informati are clocked by a flip-flop 257 (actually, only 5 bits of information are needed in the present embodiment) .
  • These include a 2-bit transfer channel code XID, two signals XIN and XOUT utilized by the tag decoding circuitry and the controller, and a signal CHACT indicating that a transfer channel is active.
  • Flip-flop 257 is reset by the assertio of -WESTAT, causing, among other things, the zeroing of XI and CHACT.
  • control signals are generated when t high order address and control information are loaded, it imperative that the low order information be loaded in the first register operation and the high order information in the second.
  • the 16-bit output from counter 250 and the 8-bit output from counter 255 are communicated to one set of inputs of multiplexer circuitry 245 while that from the other port are communicated to the other set of inputs.
  • the controller can select which port it shall take a 24-bit address from.
  • Fig. 14 is schematic of circuitry for driving ready bus 41. Upon ascertaining that the appropriate staging registers are ready to send or receive four words on four consecutive bu cycles, the controller asserts a signal BREQ (burst re ⁇ quest) . The controller operates asynchronously with respe to the bus timing and can assert BREQ at any time relative to the bus clock signals. BREQ is communicated to reset t flip-flops 260 and 262. The resetting of flip-flop 260 causes the assertion of a signal +BRDY which is communicate to the input of a flip-flop 265 and a gate 267.
  • BREQ burst re ⁇ quest
  • flip-flop 265 is also communicated to gate 267.
  • the gat output enables a selector 268 which provides signals to drive the appropriate line of ready bus 41.
  • These signals are communicated to output flip-flops 270 and ready bus drivers 272.
  • Flip-flop 265 is clocked on a trailing edge o -RC, while output flip-flops 270 are clocked on a leading edge of +RF. Accordingly, even if the +BRDY signal was unstable at the -RC transition, flip-flop 265 will have settled by the next leading edge of +RF, so that the ready bus drivers will not be enabled until BRDY has stabilized. Similarly, when +BRDY is withdrawn, the ready bus will reflect this on the next leading edge of +RF, without havin to wait until the trailing edge of -RC.
  • Tag decoding circuitry 150 responds to the data transfer tags b asserting either -XR or -XW which control the data staging circuitry. The assertion of either of these two signals
  • Fig. 15 is a schematic of circuitry for driving select line 43.
  • the signals from the tag decoding circuit indicative of the grant of bus cycles to the particular po are gated together and communicated to a flip-flop 280 whi is clocked on the leading edge of +RF to assert a signal -OURBUS.
  • a current source 282 is coupled through a diode select line 43.
  • -OURBUS is input to a buffer 285 which sinks the current from source 282 when -OURBUS is not asserted. Assertion of -OURBUS steers the current source the select line. Since the data transfer and register operations are unique to a single port on the bus, only one port's current source should drive select line 43 in response to data transfer tag or a register operation. Multiple selec tion would signify an error condition which the IOCP could determine.
  • Fig. 16 is a schematic of status register cir ⁇ cuitry 290 which includes an 8-bit history shift register 292 and an 8-bit error buffer 293 which may be read out by the assertion of -RDERR in a register operation.
  • History register 292 receives +OURBUS at its data input and is clocked on the trailing edge of -RF.
  • a flip-flop 295 is s when the tag decoding circuitry asserts -LOCK, causing shi register 292 to be "frozen.”
  • the lock tag (tag -*-* 4) is a global tag that does not use the data bus, but rather caus all the ports on the bus to freeze their history shift registers.
  • OMPI Fig. 17 is a schematic of circuitry 300 that causes error line 53 to be driven. This occurs when the controller asserts any of four unit error signals (UE1 - UE4) , when tag parity checking circuitry 155 asserts a signal -LTPE (latched tag parity error) , when input parity error checking circuitry 103 asserts a signal -LDPE (latch data parity error) , or when the output circuitry asserts a signal -LIPE (latched internal parity error) .
  • UE1 - UE4 unit error signals
  • tag parity checking circuitry 155 asserts a signal -LTPE (latched tag parity error)
  • input parity error checking circuitry 103 asserts a signal -LDPE (latch data parity error)
  • the output circuitry asserts a signal -LIPE (latched internal parity error) .
  • Fig. 18 is a schematic of circuitry 310 that determines, on the basis of the distributed mask, whether the port shall be allowed to drive interrupt line 44.
  • Each port reads a predetermined one of the data lines, as determined by its UNIT code.
  • Ea port sets its activity mask bit as indicated by the relate bit on the data bus and thus conditions the assertion of -INTA which is used by circuitry 212 to determine whether is proper to drive the interrupt line.
  • Fig. 19 is a schematic of end status register circuitry 320.
  • circuitry 320 communicates the information on LDIN lines 105 to control lines 205 in response to the assertion of -WESTAT.
  • the circuitry in ⁇ cludes flip-flops 322 having data inputs coupled to LDIN lines 105 and data outputs coupled to control lines 205.
  • Flip-flops 322 are clocked on the trailing edge of -WESTAT.
  • the -WESTAT signal also sets a flip-flop 325, causing a signal DONE to be communicated to the controller.
  • the output buffers of flip-flops 322 are enabled by a signal RD ESTAT from the controller, which signal also resets flip- flop 325.
  • the -WESTAT signal also has the effect of de ⁇ taching the transfer channel by resetting flip-flop 257.
  • the particular completion code that is written into the end status register provides information relating.to the comple tion status.
  • the controller front end includes addi ⁇ tional registers and control circuitry which will not be described in detail since they are generally not used exce under abnormal conditions.
  • Fig. 20 illustrates WRAP registers 330 and 332 which enable the IOCP to read the low order DMA address th is written into a port through that port or through the other port in the front end.
  • Fig. 21 is a schematic of side control register
  • Fig. 22 is a schematic of circuitry within each port for decoding the IOS lines and asserting signals -Fl and -F2 denoting special functions (extended mode) .
  • the I lines are communicated to a decoder 336 whose outputs provide the -Fl and -F2 signals.
  • Operation in one of the extended modes (maintenance write for -F2 or "eviction" fo -Fl) occurs only under special conditions, with especially profound results. Accordingly, there is provided a specia timed protocol for ensuring that neither -Fl nor -F2 will asserted spuriously, as for example during power transi ⁇ tions.
  • decoder 336 is not enabled until TFRM (actually the ungated signal +RAWTF) has been asserted for predetermined number of cycles.
  • a chain of counters 337 counts +TC pulses (at 250 ns intervals) and for 12 bits defines a 1-ms interval.
  • +RAWTF releases the counter clear (so long as +OSO is asserted) and the counter output is gated with +RAWTF to enable decoder 336 once +RAWTF has been active for 1 ms.
  • the counter output changes, thereby negati -Fl and -F2.
  • the data, IOS, and tag must be valid at this transition for maintenance writes.
  • a signal -THIS allows for selection to be described below.
  • Fig. 23 is a schematic of shared maintenance control circuitry 340. This circuitry responds to the
  • Circui ry 340 includes receiver control flip-flops 342a and 342b which provide respective pairs of signals ⁇ IN.A and ⁇ IN.B for controlling the receivers in the respective ports.
  • Th circuitry also includes driver control flip-flops 345a and 345b which provide respective pairs of signals ⁇ OUT.A and ⁇ OUT.B for controlling the drivers in the respective ports
  • -F2 (-F2.A or -F2.B) allows the IOCP to use either of the two data sub-buses to communicat maintenance instructions to control the setting of flip- flops 342a-b and 345a-b.
  • the input data lines from both sub-busses are communicated to a first level of multiplexe 350 which provide for selection from one sub-bus or the other, and a second level of multiplexers 352 which allow the desired port to be affected.
  • the need for two levels multiplexing arises from the fact that while the IOCP will know which sub-bus the port to be controlled is on, it wil not know which port within the controller front end is con nected to that sub-bus.
  • the multiplexer selection is effected by the signal -THIS from the A port (-THIS.A) .
  • bits (0-2) control the input, bits (4-6) the output.
  • Bits (8-F) are written into flip-flop 355 which defines a maintenance register that provides control signals for the controller itself.
  • Bit (0 active specifies that the input function is to be affected.
  • Bit (1) active specifies that the receiving port is to have its own input function affected
  • bit (2) active specifies that the other port is to have its input function affected.
  • the output functions are handled analogously.
  • the clocking of the flip-flops occurs when -F2 is withdrawn.
  • a peripheral controller communicates with IOCP 15 by passing structured messages denoted "mini- messages.”
  • mini- messages The IOCP reads the mini-messages by utilizing tne block transfer mechanism described above to determine what operation the controller needs to have performed by t IOCP.
  • the IOC Upon completion of the requested operation, the IOC notifies the controller by writing an appropriately format ted status word into end status register 320.
  • the description made no assumptions regarding IO
  • IO 15 includes cache/TLB 20 and ALU 22 which together consti ⁇ tute a CPU capable of performing the supervisor and messag handling tasks that permit the peripherals coupled to the sub-buses to communicate with devices coupled to system bu 17.
  • the design and implementation details of the lOCP's C represent matters outside the scope of the invention. It suffices to note that in the preferred implementation, the lOCP's CPU is a 64-bit ECL microprogrammed processor with 50-ns cycle time.
  • SBA 23 relates more directly to the invention, a will now be described, albeit at a somewhat lower level of detail.
  • SBA 23 is coupled to a 64-bit interface for commu nication with the lOCP's CPU.
  • SBA 23 when re-* ceiving a 64-bit word from the lOCP's CPU, breaks that dow into 16-bit data and accompanying control information for transmission onto the sub-bus.
  • the SBA When receiving 16-bit data from the sub-bus, the SBA assembles the 16-bit data into 64-bit words and signals the ALU to retrieve the data.
  • Fig. 24 is a block diagram of SBA 23.
  • SBA 23 couples to sub-buses 25 and 27 through respective sub-bus interfaces 350 and 352, receives 64-bit words (72 bits wit parity) from the ALU at an input latch 355, and transmits 64-bit words (72 bits with parity) at an output latch and multiplexer 357.
  • the SBA includes a local store 360 and a control store 362, both of which may be downloaded with information from the ALU.
  • Local store 360 contains a two-word data buffer for each of the eight transfer channels capable of being supported by the SBA (four on each of the two sub-buses) , pointers, channel status words, and a table to provide a priority regime for servicing the transfer channels on each of the two sub-buses.
  • the reason for there being two words dedicated to each transfer channel is that the byte align ⁇ ment from the sub-bus need not correspond to what the ALU requires.
  • sub-bus interfaces 350 and 352 ar respective sequencers 370 and 372 and respective control store data registers 375 and 377.
  • Sequencers 370 and 372 handle a limited number of commands as specified by the ALU and relieve the ALU of any tasks associated with timing dat movement to and from the sub-buses.
  • the bits in a word from control store 362 provide the necessary control signals for the operation of the sequencers and the sub-bus interfaces.
  • Control store data registers 375 and 377 are loaded from control store 362 to provide such control signals.
  • Local store 360 and control store 362 are each time sliced on a 50-50 basis with the tw sequencers running out of phase with one another. Sequence 370 and sub-bus interface 350 are referred to as the "A side"; sequencer 372 and sub-bus interface 352 as the "B side.” These designations need not correspond to the A an B ports in the controller front ends.
  • the SBA further includes an 8-deep channel FIFO stack 380 into which are written the transfer channel numbers in the order that they are serviced.
  • t SBA is implemented in ECL logic due to the relatively high speed required.
  • the data flow and general operation of the SBA m be understood by considering, first, the sequence for a transfer from the ALU onto the sub-bus (as for example to effect a write from memory to disk) , and second, the se ⁇ quence for a transfer from the sub-bus to the ALU (as for example to effect a read from disk to memory) .
  • the ALU When the ALU decides to begin a transfer, it communicates to the SBA the direction, the transfer channe address, and a byte offset.
  • the ALU latches a first 64-bi word from its cache and makes this available at input latc 355.
  • the ALU provides the channel address and an opcode specifying that the first word is to be written to a peri ⁇ pheral controller.
  • the SBA stores this first word in the first of t two locations in local store 360 dedicated to this transfe channel, puts the channel address in channel FIFO 380, and asserts a transfer channel ready flag to the ALU. (Note a this time the first word has not been transferred onto the sub-bus.)
  • the ALU on seeing the transfer channel ready flag, reads the channel address, and uses this channel address to index a channel control word which specifies, among other things, the amount of data left to transfer.
  • the ALU fetches the next word from its cache, makes it available at latch 355, and provides the SBA with the channel address and an opcode specifying a write to a peripheral controller.
  • the SBA stores the second word in the second of the two local store locations dedicated to that transfer channel.
  • the SBA causes eight bytes to be transferred on the sub-bus on four successive sub-bus cycles according to the sequence and timing described above. Depending on the byte offset, the eight bytes may come in part or in whole from the first of the two local store locations. After th eight bytes have been transferred, the SBA puts the channe address in channel FIFO 380, and asserts the transfer channel ready flag.
  • the ALU upon seeing the transfer ready flag, reads the channel address, indexes the channel contr word, fetches the next word from its cache, and communicat this word with accompanying control information to the SBA.
  • the SBA stores this next word in the first local store location and transfers eight bytes as described above. On successive transfers, it will store words from the ALU alternating between the first and second locations.
  • the ALU initiates such a transfer by informing the SBA of the direction, the transfer channel address, the byte offset, and provides the SBA with a transfer channel addres and an opcode specifying a read from peripheral controller.
  • the SBA causes eight bytes to be transferred from the controller on the sub-bus over four successive sub-bus cycles, stores the eight bytes in the first local store location, puts the channel address in the channel FIFO, and asserts the transfer channel ready flag.
  • the ALU upon seeing the transfer channel ready flag, reads the channel address, indexes the channel contro word, and gives the SBA the transfer channel address and th opcode specifying a read from peripheral controller.
  • the SBA then effects a transfer of eight more bytes and stores them in the second location in local store 360, puts the channel address in channel FIFO 380, and asserts the transfer channel ready flag.
  • the SBA Upon seeing the channel address at the head of t FIFO, the SBA reads the appropriate eight bytes out of the two locations for that channel, and transfers these eight bytes to output multiplexer 357.
  • the ALU reads the channe address, uses it to index the channel control word, reads the word from output latch 357 and provides it to its cach
  • the ALU then gives the SBA the transfer channel address an the opcode specifying a read from controller to repeat the above sequence.
  • the SBA alternately stores the eight byte from the sub-bus in the first and second locations as in t case of the transfer from the IOCP to the controller.
  • Figs. 25A and 25B are timing diagrams for contro signals passing between the ALU and the SBA, illustrating the sequence of events for the two directions of transfers outlined above.
  • the gaps illustrated in the sequences signify that the 64-bit data transfer on the sub-bus occur within the interval.
  • Fig. 26 is a schematic of circuitry within SBA 2 that provides various clock signals for sequencers 370 and 372 and for sub-bus interfaces 350 and 352.
  • the circuitry operates to provide a variety of 50-ns and 250-ns clock signals that establish sub-bus timing. These are derived from the basic 25-ns clock signal that defines overall system timing.
  • Complementary system clock signals +SYSCLK and -SYSCLK are gated at a network 400 to produce complementar 25-ns clock signals +GCLK and -GCLK.
  • +GCLK is communicate to a counter 402 which provides frequency divided signals, more particularly a 250-ns clock signal +REF0, and a 50-ns clock signal +(A/B).
  • These signals are communicated to tw sets of circuitry corresponding to the A and B sides of th SBA. Only one set will be described.
  • the suffix ".A” wil denote timing signals for the A side; the suffix ".B” wil denote signals for the B side.
  • REFO is communicated to a chain of cascaded flip-flop stages 405 which, when clocked by a signal deriv from -GCLK, provides a group 407 of 250-ns clock signals.
  • Signals 407 include four subgroups: (+T01.A, +T02.A, +T03.A), +R1.A, (+T21.A, +T22.A, +T23.A), and +R3.A.
  • the subgroups are progressively delayed relative to one anothe by 25-ns increments.
  • a timing diagram of signal group 407 is shown in Fig. 27.
  • the 50-ns signal +(A/B) is inverted to define a signal -(A/B).A which is clocked by the same derived -GCLK signal to generate a group 408 of 50-ns clock signals +T(A/B)1.A, -T(A/B)1.A, +T(A/B)3.A.
  • the signal +(A/B) in its non-inverted state is used to establish a complementar set of signals (not shown) for the B side.
  • Fig. 28 is a schematic of circuitry within sub-b interface 350 for generating the outbound clock signals, t timing of which is illustrated in Fig. 3.
  • the 250-ns sign +R3 is communicated to the data inputs of flip-flops 430 a 431 which are clocked at 50-ns intervals by +T(A/B)1.
  • the outputs of flip-flops 430 and 431 are passed through ECL/T converters 432 and to respective bus drivers 435 and 437 t drive TCLK line 45 and TFRM line 50.
  • TCLK runs continuously while TFRM is only asserted in connection with the issuance of tags.
  • TFRM is controlled b the signal +ETF (enable TFRM) which is one of the bits from control store data register 375. This is effected by havin +ETF, as clocked through a flip-flop 438, control the reset input of flip-flop 431.
  • the 250-ns signal +R1 is com- municated to the data inputs of flip-flops 440 and 431, the outputs of which are passed through ECL/TTL converters 432 and to respective bus drivers 445 and 447 to drive outbound RCLK line segment 47 (out) and outbound RFRM line segment 52(out).
  • RFRM is controlled by the signal +ERF (enable RFRM), as clocked through flip-flops 448 and 449.
  • the extr flip-flop (relative to +ETF) provides a 250-ns delay, so that while +R1 leads +R3 by 50 ns, RFRM lags TFRM by 200 ns IOCP - Data Movement
  • Fig. 29 is a schematic of circuitry within the sub-bus interface for driving data bus 40 and tag bus 42.
  • the four tag bits are passed through ECL/TTL converters 46 and through flip-flops 462 while the IOS bits are just passed through converters 460.
  • the IOS and tag bits are communicated to a parity generator 467, and the resultant seven bits are communicated to bus drivers 468 for driving tag bus 42.
  • the data bits are communicated through ECL/TTL converters 460 and through two flip-flop stages 472 and 47 to bus drivers 477.
  • Flip-flop stage 472 provides a 250-ns delay relative to the tag bits.
  • Flip-flops 472 and 475 (a well as flip-flops 462) are clocked by the leading edge of + ⁇ °3.
  • the output enable of data bus drivers 477 is controlled, in the first instance, by +EDATA (enable data) which is one of the control store data register bits.
  • +EDATA is clocked through two flip-flop stages 480 and 482 to establish the same timing as the data. +T23 and +T01 a combined at a gating network 485.
  • the complement of the output from network 485 is shown on Fig. 28, designated “output enable.” This signal is further delayed somewhat additional gating stages, but, when gated by the clocked +EDATA at a gate 487, defines the basic output timing for the sub-bus interface.
  • the output drivers are enabled over a major portion of the 250-ns cycle, starting generally near the leading edge of TCLK (+R3) and extendin beyond the trailing edge of TCLK.
  • the data is valid when latched by the ports' input latches 102 at the traili edge of TCLK.
  • Fig. 30 is a schematic of circuitry within the sub-bus interface for receiving signals on data bus 40, ready bus 41, interrupt line 44, and error line 53. These signals, as well as the RCLK signal on RCLK line segment 47(in) are communicated through bus receivers 500, to latches 502, and are latched at the trailing edge of RCLK(in). The latch outputs are communicated to flip-flop 505 which are clocked by a TTL signal +TT2 signal derived from +T22, passed through TTL/ECL converters 507 to be mad available to the SBA. It will be appreciated that the incoming data wi not be valid until a certain time interval after the, tag specifying that there will be incoming data to be read is issued.
  • the SBA asserts a signal +RECV (one the bits in the control store data register) when there is to be incoming data associated with this operation.
  • +RECV is clocked at a flip-flop 515, and then through a set of cascaded flip-flop stages 517, the number of such stages being adjustable according to the length of the sub-bus.
  • the dependence on the sub-bus length arises since the incoming data is timed relative to RFRM and RCLK which mus turn around at the sub-bus terminator.
  • the output from cascaded flip-flops 517 is clocked at a flip-flop 520 by t signaj. +T21 to generate a signal DATA VALID once RFRM has turned around.
  • 31 is a schematic of circuitry within the sub-bus interface for determining the state of select line 43.
  • the signal -OURBUS which conditio current source 282 for the select line is clocked at the leading edge of RFRM (+RF in the controller port) .
  • Select line 43 is terminated to ground by 100 ohms at each end.
  • the select line is communicated to the positive input of a first comparator 525 and the negative input of a second comparator 527.
  • the negative input of comparator 525 is held at +1 volt and the positive input of comparator 527 a +4 volts, as established by a voltage divider. Since each current source within a controller port drives 50 ma into the line, a single source driving the line will produce a 2.5 volt signal, and multiple sources will produce a signal in excess of 5 volts.
  • the comparator outputs are clocked a flip-flops 530 by the incoming RFRM signal.
  • the outputs from flip-flops 330 are further clocked at flip-flops 532 b the signal +TT2 (derived from +T22) which is timed to the
  • the SBA can determine whether an error condition exists due to multiple controllers condi- tioning their current sources to drive select line 43. As in the case of the data, the state of the select line must be checked at a time relative to the tag that has allowed the RFRM signal to be turned around. Accordingly, the SBA asserts a signal +RSEL (one of the control store bits) which is clocked at a flip-flop 540 an through cascaded flip-flop stages 542, the number of such stages being adjustable according to the length of the sub-bus (in the manner described above) .
  • the output from stages 542 is clocked at a flip-flop 545 by +T21 to genera a signal +CHECK SELECT once RFRM has turned around.
  • the present inven tion provides the circuitry for implementing a system of logical transfer channels. Once a transfer channel is attached, data transfers occur with minimal overhead (the issuance of the tags) , thereby allowing bus cycles to be granted or denied very flexibly. This permits the various interleaved operations to proceed at their respective spee while the bus runs at full speed. While the above provides a full and complete disclosure of the preferred embodiment of the invention, various modifications, alternate constructions, and equi ⁇ valents may be employed without departing from the true spirit and scope of the invention. For example, while the system shown provides four transfer channels in the contex of up to 16 devices coupled to a sub-bus, these numbers ar not fundamental.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Traffic Control Systems (AREA)

Abstract

Le système de bus de données utilisant des canaux logiques de transfert permet d'obtenir des cadences élevées de transmission de données (même sur de longues distances) et une bonne détection des erreurs comme la fonction de base d'un canal de transfert et d'affecter temporairement d'une partie de la ressource de bus à un dispositif spécifique et de permettre ensuite l'adressage simple et rapide de ce dispositif par référence à ce canal. Il existe un nombre relativement réduit de canaux de transfert (environ 4) qui peuvent être attachés ou détachés par le processeur de canal (IOCP) pour satisfaire aux besoins de circulation de données. Afin d'effectuer un transfert entre l'IOCP (15) et un dispositif (30a, 30b), l'IOCP (15) effectue d'abord une opération d'"attache" pour affecter au dispositif (30a, 30b) un canal de transfert pendant la durée du transfert. L'IOCP (15) assigne ensuite les cycles de bus parmi les canaux de transfert attachés à ce moment là en fonction de tout arrangement désiré de priorité, à condition que le dispositif relié à un canal de transfert soit prêt à envoyer ou à recevoir des données avant l'affectation de cycles au canal de transfert.
EP19830902485 1982-06-30 1983-06-29 Bus de canaux d'entree/sortie. Withdrawn EP0112912A4 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US39386082A 1982-06-30 1982-06-30
US393860 1982-06-30
US06/426,045 US4564899A (en) 1982-09-28 1982-09-28 I/O Channel bus
US426045 1982-09-28

Publications (2)

Publication Number Publication Date
EP0112912A1 true EP0112912A1 (fr) 1984-07-11
EP0112912A4 EP0112912A4 (fr) 1987-04-28

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EP19830902485 Withdrawn EP0112912A4 (fr) 1982-06-30 1983-06-29 Bus de canaux d'entree/sortie.

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EP (1) EP0112912A4 (fr)
AU (1) AU559558B2 (fr)
WO (1) WO1984000222A1 (fr)

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US4669056A (en) * 1984-07-31 1987-05-26 International Business Machines Corporation Data processing system with a plurality of processors accessing a common bus to interleaved storage
US6126945A (en) * 1989-10-03 2000-10-03 Pharmacia Ab Tumor killing effects of enterotoxins, superantigens, and related compounds
US5175825A (en) * 1990-02-02 1992-12-29 Auspex Systems, Inc. High speed, flexible source/destination data burst direct memory access controller
US5182800A (en) * 1990-11-16 1993-01-26 International Business Machines Corporation Direct memory access controller with adaptive pipelining and bus control features
ATE165925T1 (de) * 1991-07-30 1998-05-15 Siemens Nixdorf Inf Syst Schaltungsanordnung zum aufbau gleichartiger peripheriegeräteanschlussschaltungen als zugangsschaltungen für unterschiedliche peripheriegeräte zu einem gemeinsamen bus
EP0525233A1 (fr) * 1991-07-30 1993-02-03 Siemens Nixdorf Informationssysteme Aktiengesellschaft Méthode et montage pour le transfert de données par accès directe mémoire entre un omnibus de système et une mémoire
US5386532A (en) * 1991-12-30 1995-01-31 Sun Microsystems, Inc. Method and apparatus for transferring data between a memory and a plurality of peripheral units through a plurality of data channels

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EP0028891A1 (fr) * 1979-11-05 1981-05-20 Litton Resources Systems, Inc. Installation de traitement de données

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US3810105A (en) * 1967-10-26 1974-05-07 Xerox Corp Computer input-output system
US3798613A (en) * 1971-10-27 1974-03-19 Ibm Controlling peripheral subsystems
US4038641A (en) * 1976-04-30 1977-07-26 International Business Machines Corporation Common polling logic for input/output interrupt or cycle steal data transfer requests
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GB1314180A (en) * 1969-11-21 1973-04-18 Plessey Telecommunications Res Electrical data transmission systems
EP0028891A1 (fr) * 1979-11-05 1981-05-20 Litton Resources Systems, Inc. Installation de traitement de données

Non-Patent Citations (1)

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See also references of WO8400222A1 *

Also Published As

Publication number Publication date
EP0112912A4 (fr) 1987-04-28
WO1984000222A1 (fr) 1984-01-19
AU1822283A (en) 1984-01-26
AU559558B2 (en) 1987-03-12

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