EP0111557A1 - Laser video disc storage and retrieval system - Google Patents

Abstract

A storage and retrieval system (10) for a laser video disc receives a digital data signal (16) from a computer (13) and includes an interfaced transmitter (20) which transforms the data signal into a video signal shaped (24) for placement on a laser video disc (30). Polling the video disc (30) produces a video signal (38) matching the structure of a selected portion of the shaped video signal (38) stored on the video disc (30). An interfaced receiver (34) receives the video signal (38) from the poll and forms a data signal (42) which can be read by a computer (44), thereby selectively storing and retrieving the data. .

Description

LASER VIDEO DISC STORAGE AND RETRIEVAL SYSTEM

Technical Field

The present invention relates to the field of computer data systems, and more particularly but not by way of limitation, to a system for the storage of data on a laser video disc in standardized video format accessible for random and selected retrieval.

Background of the Invention A video disc is a pτeγrecorded disc containing video and audio data encoded in digital format such that the video data and the audio data can be converted into a television display via an electronic translation device. The video disc is similar to the conventional audio recording which is used with a home stereo system but it offers greater flexibility in the playback mode than the audio recording. A pre-recorded program can be viewed in slow motion; frames can^' be stopped and a still of the video program can be viewed; portions of the video program can be skipped over; the video program can be reversed. The video disc can be provided pre-formatted indexes that allow the operator to select a particular location via a microprocessor located internal to the video disc player.

Video disc systems can be broken into two major categories, stylus and optical systems. A stylus system uses a stylus that either traces the tracks on the disc or senses a change to stylus capacitance on the disc. An optical system uses a laser light beam that is projected onto the video disc. The laser light signal, interacting with the disc, is converted into an electric pulse that is converted into the video and audio signal. The present invention involves the optical system video disc system which utilizes a laser beam for access to data stored on a video disc. A laser beam automatically tracks pre-recorded information on the video disc. The laser beam is modulated by the data on the disc to create an electric signal that is used to recreate the audio and video signals. Digital information is conventionally encoded on the video disc to indicate frame numbers, program start and ending locations and other types of information used to control either the program or access to segments of the program on the disc. This provides the basis for equipment featuring special playback features, such as slow motion; high speed playback; still frame display; reverse frame playback; and random access to data segments. The format of a video recording is developed in compatibility with the standard for television video of the country in which it is used. (In the United States,, this is the NTSC video signal format.) This standard controls the timing of horizontal and vertical traces across a cathode ray display tube. A typical video disc recorded for use in this country contains 54,000 "pictures", or "frames". That is, in the normal audio and video signal used for a standard television program playback, a frame will consist of a series of pulses that, when decoded, will influence the timing and firing of electron guns inside the cathode ray tube to generate a "picture" on a TV screen. The picture is generated by the impact of the electron guns starting at the upper left-hand portion of the screen and scanning horizontally across the screen, then dropping down to the next scan position and proceeding horizontally across the screen again. The timing of the activation of the electron guns during this scanning operation is predetermined, and operated in accordance with, the aforementioned television standard.

Presently, video disc systems are used for the storage and retrieval of pictures in the manner described. Some data is included on the video discs but this data is only used for the control of the video disc and not for storage or retrieval of the data itself. Corvus Systems Inc., located in San Jose, California, has developed interface equipment that converts digital signals to a video format for storage on magnetic tape. The Corvus unit, sometimes called the Corvus Mirror, as_^ designed primarily as an economical means of backing up data contained in a computer disc drive. Sum ary of the Invention

The present invention provides a laser video disc storage and retrieval system which is connected to a computer and which receives a first data signal therefrom. The laser video disc storage system comprises an interface transmitter which interacts in the first data signal to form a formatted first video signal containing the data of the first data signal. Video disc mastering equipment receives the first video signal and impresses the first video signal in memory format on a laser responsive video disc. Playback equipment can be used to interrogate the video disc to produce a second video signal conforming to a selected portion of the first video signal in the memory format of the video disc. Finally, an interface receiver receives the second video signal from the playback equipment and forms a second data signal which is compatible with a computer so that data contained in the selected portion of the memory format of the video disc is readable by the computer.

Accordingly, it is an object of the present invention to - provide a data storage and retrieval system which is economically feasible and which utilizes readily available video disc equipment and components.

Another object of the present invention is to provide a data storage and retrieval system capable of handling very large quantities of data which is rapidly accessible for selected usage.

Another object of the present invention is to provide a data storage and retrieval system which is extremely accurate, being substantially unaffected by outside environmental disturbances.

Another object of the present invention is to provide a data storage and retrieval system which is capable of storing very large quantities in high density compactness.

Other objects, advantages and features of the present invention will become apparent from the description provided ereinbelow when read in conjunction with the included drawings and appended claims.

Brief Description of Drawings Figure 1 is a schematic depicting the arrangement of various equipment to produce video discs in accordance with the present invention. Figure 2 is a schematic depicting the arrangement of further equipment to utilize the video discs of Figure 1 to practice the present invention.

.Figure 3 is a schematic of the interface transmitter utilized in the arrangement schematic of Figure 1. Figure 4 is a detailed schematic of the I/O (input/output) circuit shown in Figure 3.

Figure 5 is a detailed schematic of the control circuit shown in Figure 3.

Figure 6 is a schematic of the interface receiver utilized in the arrangement schematic of Figure 2.

Figure 7 is a pictorial representation of the display face of a video cathode ray tube.

Figure 8 is a graphic representation of the video format of a typical horizontal line displayed on the display face of Figure 7.

Figure 9 is a graphic representation of a portion of a typical horizontal line and a data rate clock signal.

Description A laser video disc storage and retrieval system constructed in accordance with the present invention is depicted and designated by the numeral 10 in the schematic views shown in Figure 1 and in Figure 2. Referring to Figure 1, shown therein is a schematic depicting the arrangement of various equipment, including a storage system 12, used to produce a unique laser video disc containing data than can be retrieved by a retrieval system 14 shown in Figure 2 and which will be described later. The storage system 12, shown connected to a computer 13, via a data buss 16 and a control buss 18, is comprised of an interface transmitter 20, a video signal line 24, a video disc mastering equipment 26 and a video disc 30. The computer 13 is of conventional type, having high speed direct memory access capabilities and a memory of sufficient size to contain an operating system program that will control the data transfer to the interface transmitter 20.

The data to be stored on the video disc 30 is contained on a computer disc 11. This data is transferred into the computer 13 in convenient size blocks where it resides in memory until the interface transmitter 20, which will be described more fully hereinbelow with reference to the schematics of Figures 3 through 5, requests data from the computer 13 by way of control signals sent through the control buss 18. Upon receipt of appropriate control signals the computer 13 sends portions of the data previously stored in computer memory through the data buss 16 to the interface transmitter 20. The interface transmitter 20 collects the data from the data buss 16, formats the data into a format that is compatible with a video signal timing, then combines this data with a standard video signal. The resultant signal is a video signal containing digital data in a video format. This video signal is sent through the line 24 to the video disc mastering equipment 26. During the mastering operation certain control data is added to the video disc 30 by the disc mastering equipment 26. This control data will be used by video playback equipment 32 shown in Figure 2 and described further below. The control data identifies each "picture" with a unique number. The video disc mastering equipment 26 then produces multiple video discs 30 containing the original data contained on the computer discs 11, the data on the video discs 30 being in digital video format.

Referring to Figure 2, shown therein is a schematic depicting the arrangement of the various equipment used to retrieve the data contained on the video disc 30. The retrieval system 14 is comprised of an interface receiver 34, which will be described more fully hereinbelow with reference to the schematic of Figure 6, and the video disc player 32 which reads the video disc 30. The video disc player 32 is a standard commercially available laser video disc player having external control functions or random access of video pictures and search capabilities for locating specific video pictures, sucn as Sony Model LDP-1000. The interface receiver 34 requests data from the video disc player 32 through a control line 36. The video disc player 32 responds by searching the video disc 30 for the data in either a random or sequential mode. As data is located by the video disc player 32, it is sent to the interface receiver 34 through a video signal line 38. The interface receiver 34 strips the data from the video signal, then transmits the data through a data line 42 to a computer 44 under control of line 40 (while the data from the interface receiver 34 could be returned for use in the computer 13, it is assumed, for this description, that a different computer receives the data) .

Turning now to Figure 7, shown therein is a pictorial representation of the display face of a video cathode ray tube 50 having a screen 52. The United States standard video signal format is comprised of 525 line locations depicted by the lines 54. The lines 54 are not visible but are used to present an image on the screen. The image is "drawn" on a phosphor coated screen by sweeping an electron beam across it. When struck by electrons, the phosphor coating on the surface of the tube emits light. By modulating the intensity of the beam a selectively dotted or dashed line is drawn to form a TV picture. The TV monitor starts its electron beam in the upper left hand corner 55 of the screen 52 and scans one half of the lines 54, or 262 1/2 of these lines. The first scan comprises the first field. The lines scanned are not spaced each above the next one to be scanned, but in effect the scan is of every other line, leaving black or unscanned lines between each of the first 262 1/2 lines scanned. On the second field scanned, also called the interlaced field 56, the spaces between the first field lines are filled in by lines from the second field. Each 262 1/2 line frame takes 1/60 seconds to scan. A full interlaced frame of 525 lines takes 1/30 seconds and consists of two 262 1/2 line frames. The electron beam is "turned on" at the start of a typical horizontal line 58, then "turned off" at the end 60 of this horizontal line and it remains off until it traces to the left hand portion of the screen and is turned back on at the next horizontal line 62.

A typical video horizontal line is 64 microseconds wide. However, only about 50 microseconds show upon the screen 52. Only about 240 lines of the 262 1/2 lines appear on the screen for each of the two fields. At the end of line 262 of the first field, the horizontal sync signal varies by a predetermined interval to signal the electron gun to start field 2 at position 56. This variation in the horizontal sync signal can be utilized to establish the start of field 1. The unique data format that this invention uses is compatible with this format and can be easily modified to be compatible with other video formats.

In Figure 8 there is shown a graphic representation of the video format of horizontal line 54 which is typical of the horizontal lines displayed on the screen 52 (Figure 7). The laser video disc storage and retrieval system 10 of the present invention uses this format in its conversion of digital data to video formatted data and back to digital form. Each horizontal line is divided into 80 bit locations. Turning back to Figure 7 these 80 locations occur within the visible portion 64 of one horizontal line 50. The start and termination of the bit locations is controlled by the video horizontal sync signal previously described. Referring to Figure 9, contained therein is a graphic representation of a portion of a typical horizontal line and a data rate clock signal. The data rate clock 80 is a clock signal timed to pulse 80 clock pulses within the visible portion 64 of a horizontal line. Data is represented by presenting a video signal well within the white region 82 at the rising edge of each clock pulse 83. The width of the data pulse determines the logic level of the data signal. A "0" is represented by a white bar 143 nanoseconds (ns) wide, 84. A logic level "1" is represented by a white bar 429 nanoseconds wide, 86. There will be 80 bit cells, 87, on each horizontal line. The decoded valves of the example in Figure 9 are shown on 88. For discussion purposes there will be 80 bits per line, therefore, 10 bytes (consisting of 8 bits each) per line can be transmitted.

Turning to Figure 3, shown therein is a schematic diagram of the major circuits comprising the interface transmitter 20. The interface transmitter 20 is comprised of: a video signal generator 90 that provides a standard black reference video signal; a sync separator circuit 92 that separates the sync signals from the video signal generated by the video signal generator 90; a horizontal line counter 94 that counts horizontal lines and sends appropriate output signals as required at each start and stop data transmission; a data rate clock 96 that supplies a timed clocking signal equal to the rate of data transmission required; a data control circuit 98 that determines the placement of data within each horizontal line as well as the number and location of data bits on a horizontal line; an l/O, or input/output, circuit 100 that interfaces with the host computer to receive high speed data, synchronize the computer for the interface transmitter 20 and provide start/stop transmission control; and a pulse width modulator 102 which generates the pulse width modulated data, as well as a unique header pulse on one or more selected horizontal lines just prior to transmission of data. The header pulse is utilized by the interface receiver 34, Figure 2 during the operation of the retrieval system 14. The purpose of the header pulse is to signal that data is present in the video field. The interface transmitter 20 is further comprised of a video mixer circuit 104 which combines the digital data from the pulse width modulator 102 and the video signal from the video signal generator 90, and amplifies the resultant signal to produce a video signal with data encoded in the unique data format previously mentioned.

In Figure 4 there is depicted a schematic representation of the l/O control circuit 100. This control circuit is connected to the computer 13, through ports: 100A, by way of line 106; 100B, by way of line 108; 100C, by way of line 110; 100D, by way of computer data buss line 112; and 100E, by way of computer address buss 113. These control, address, and data lines are used to transfer data to the interface transmitter 20 and provide control signals between the computer 13 and the interface transmitter 20.

Circuit 200 is an address decoder that will cause to go active, one and only one output ports 200C, 200D, 200E, 200F, when^' the proper combination, unique to that output port, is input through ports 200D and 200A. Port 200B is a plurality of address lines from computer 13 through port 100E and line 145. Port 200A is an input/output request line from computer 13 through port 100B and line 109. Port 200C is used to start data transfer. Port 200D is used to terminate data transfer. Port 200E is used as a polling port for circuit 212. Port 200F is used to tranfer each byte of data from computer to circuit 206. Circuit 202 is a latch circuit. When port 202B from port 200C through line 240 momentarily goes active, port 202C goes and stays active, until port 202A from port 200D through line 238 momentarily goes active, at which time port 202C goes and stays inactive. Port 202C goes through line 247, junction 232, line 230 and output port 100J.

Circuit 204 synchronizes data transfer between computer and interface transmitter 20. Port 204C from port 202C through line 247, junction 232, line 229 is an input which inhibits operation of 204 where inactive. Port 204C will go active to initiate a data transfer and stay active until the transfer is complete. When port 204C is held active, port 204B from port 200F through line 246, junction 235, line 228 is caused to momentarily go active by computer 13, under program control, causing port 204A to go and stay active. Port 204A through line 227, port 100C is a wait line to computer 13, causing computer 13 to temporarily suspend operation. Port 204D through line 245, junction 234, line 226 and port 100G momentarily goes active, causing port 204A to go inactive, thereby allowing computer 13 to continue operations. Circuit 206 is an eight bit latch. Port 100D from computer 13 consists of eight data lines to junction 214, line 215, port 206A. When port 206B is momentarily caused to go active from line 216, junction 235, line 246, port 200F, by computer 13, under program control, signals at port 206A are latched into circuit 206 and present at port 206C.

Circuit 208 is an eight bit latch. Port 208A from line 217, port 206C consists of eight data lines. When port 208B is momentarily caused to go active from line 220, junction 234, line 226, port 100G, signals at port 208A are latched into circuit 208 and present at port 208C.

Circuit 210 is a parallel to serial converter. Port 210A from line 221, port 208C consists of 8 data lines. Input port 210C, from line 223, port 100H and port 210D from line 224, port 1001, and port 210E, from line 225, port 100M are sequenced active in a binary divide by eight sequence. The combination of these inputs determine which of the eight data lines at port 210A is available at port 210B to line 222, port 100L.

Circuit 212 is an eight bit output port to computer 13. Port 212C from line 219, port 100K determines a predetermined unique combination of signals that will be available to port 212A to line 213, junction 214, port 100D, when port 212B is momentarily caused to go active from line 218, port 200E by computer 13, under program control. This tells the computer, under program control, that a data transfer is going to take place, starting with the next horizontal line. Port 100F through line 242 to port 100A is a straight through connection, and is hooked to computer 13 ready line through line 106.

In Figure 5 there is depicted a schematic representation of the data time control circuit 98. In circuit 300, port 300A from line 323, junction 341 line 339, port 98J is a momentary horizontal sync pulse. Port 300E outputs a momentary pulse, 10 microseconds after the arrival of the pulse at port 300A, through line 324, port 98G. Port 300D from line 325, junction 314, line 338, junction 316, line 337, port 304B disables port 300C when inactive. Port 300B from line 318, junction 310, line 317, port 98K is a data rate clock signal that, for the purpose of the present invention, is set at 1.75 MHZ. Port 300C will output one single pulse of the signal at port 300B, 10 microseconds after the arrival of a pulse at port 300A. -11-

In circuit 302, port 302A from line 343, port 300C going momentarily active will cause one single pulse of the signal at port 302B to be output at port 302C. Port 302B from line 320, junction 312, line 319, junction 310, line 317, port 98K is a data rate clock signal that, for the purpose of the present invention, is set at 1.75 MHZ. Port 302D from line 346, port 306A, going momentarily active will cause one single pulse at the signal at port 302B to be output at port 302C to line 344, junction 350, line 322, port 98B.

Port 303B, of circuit 303, from line 321, junction 312, line 319, junction 310, line 317, port 98K is the data rate clock, previously explained. Port 303F from line 326, junction 314, line 338, junction 316, line 337, port 304B, when active, allows circuit 303 to operate. When port 303A, from line 345, junction 350, line 344, port 302C goes momentarily active, signals at port 303B are passed to port 303C, to line 351, junction 329, line 352, port 98F and remain passing, until port 3Q3E from line 327, port 306B goes momentarily active, which terminates output from port 303C. When port 303E momentarily goes active, in addition to the above, port 303D to line 328, port 306C goes momentarily active.

Circuit 304 is a latch. When port 304A, from line 336, port 981 goes momentarily active, port 304B will go and stay active, until port 304C from line 335, port 98H goes momentarily active, in which case port 304B will go and stay inactive.

Circuit 306 synchronizes parallel to serial conversion. Port 306D from line 342, junction 329, line 351, port 303C is the data rate clock, previously explained, but gated by circuit 303, port 306B will momentarily go active after 80 counts of the signal at port 306D. Port 306C from line 328, port 303D, going momentarily active, will cause all output ports, 306E, 306F, 306G, 306H, 306A, 306B to go inactive and reset all circuits to initial states. Port 306H to line 333, port 308C will go momentarily active after 72 counts of the signal at port 306D. Port 306A to line 346, port 302D will go momentarily active on count 8, 16, 24, 32, 40, 48, 56, 64, 72 but not 80 of the signal at port 306D. Port 306E to line 320, port 98C port 306F to line 331, port 98D, port 306G to line 332, port 98E, are output ports which are sequenced in a divide by 8 binary sequence, using the signal at port 306D as a clock. Circuit 308 allows computer 13 to be released from transmission at the end of every horizontal line, so as to allow for memory refresh cycles, as needed. Port 308B from line 334, junction 316, line 337, port 304B, when inactive, disables output port 308D. Port 308D to line 340, port 98A goes and stays active when port 308A from line 348, junction 341, line 339, port 98J, (horizontal sync) goes momentarily active. Port 308D output is terminated when port 308C, from line 333 to port 306H goes momentarily active. Turning to Figure 3, circuit 96 is a synchronized clock generator with an output of, for the purpose of the present invention, 1.75 MHZ. Port 96A is a 1.75 MHZ, free running square wave oscillator output to line 128, port 98K, port 96B from line 129, junction 141, line 137, junction 140, line 150,_. port 92B is a momentary horizontal sync pulse used to synchronize oscillator.

Circuit 90 is a video signal generator. Port 90A to line 132, junction 133, line 142, port 92A, and line 134, port 104B is a black level signal. Circuit 92 is a sync separator. Port 92A from line 142, junction 133, line 132, port 90A is a black level video signal. Port 92B to line 150, junction 140, line 130, port 94D, line 137, junction 141, line 129, port 96B, line 148, port 98J is a momentarily active horizontal sync signal. Port 92C to line 131, port 94C will go active during field 1 and go inactive during field 2.

Circuit 94 is a horizontal line counter. Port 94B from line 125, port 100J, after going active, will allow counter 94 to operate after the next active going transition of port 94C from line 131, port 92C. Port 94C on active going transition will reset counter to zero and allow counter to count pulses at port 94D.^" Port 94D from line 130, junction- 140, line 150, port 92B is a momentarily active horizontal sync signal. Port 94A to line 124, junction 146, line 147, port 102B, line 121, port 100K goes active for one horizontal line during, for the purpose of the present invention, horizontal lines 29 and line 291. Port 94E to line 127, port 981 goes active for one horizontal line during, for the purpose of the present invention, horizontal lines 30 and 292. Port 94F to line 126, port 98H.goes active for one horizontal line during, for the purpose of the present invention, horizontal lines 235 and 497. Circuit 102 is a pulse width modulator. When port 102B, from line 147, junction 146, line 124, port 94A goes active and port 102C from line 123, port 98G goes active, port 102A outputs an active pulse of 50 microseconds duration. At the instant port 102D from line 120, port 98F goes active, if port 102E from line 119, port 100L is inactive, then a 143 nanoseconds pulse is output to port 102A. At the instant port 102D goes active, if port 102E is active, then a 429 nanoseconds pulse is output to port 102A.

Circuit 104 is a mixer and output amp. Port 104B frcm line 134, junction 133, line 132, port 90A is black level video.

Port 104C from line 135, port 102A is a pulse width modulated data and a header pulse. Port 104A to line 151, port 136 is the video signal output of the interface transmitter 20.

Oscillator circuit 96, video signal generator 90, and sync separator 92 are always on and functioning, as long as power is applied to transmitter. To transmit data from Computer 13 to video disc mastering equipment 26, computer 13 will, under program control, use address lines 113 to port 100E and input/output request line 108 through line 153 to port 100B to cause port 100J through line 125 to port 94B to go and stay high, following the already described logic of circuit 100.

Computer 13 will prepare itself to transfer data and then enter a polling loop, using the above mentioned address and input/output request lines to determine when port 100K has gone active as described previously. Concurrently, horizontal line counter 94 will follow its previously described order of_f operation and upon counting to horizontal line 29, port 94A will go active causing: 1) Computer 13 to exit above mentioned polling loop, as described above for circuit 100;

2) A header pulse to be output port 102A through line 135 through port 104C and finally output through port 104A to line 151, through port 136 to line 24, as described above for circuits 102 and 104.

Computer 13 has only to receive a ready signal from line 106 from line 152 from port 100A from port 100F through line 114 from port 98A, and data transmission will begin.

Horizontal line counter 94 will continue to count and upon reaching horizontal line 30, port 94E through line 127 to port 981 will go active, causing port 98A to go active. Port 98A goes through line 114, port 100F, out port 100A, through line 152 through line 106 which is the ready line to computer 13, thereby starting data transfer.

Computer 13, under program control, will then place a byte of data to be transmitted on data buss 112 into port 100D, and at the same time will place a predetermined and unique combination of signals on line 113 into port 100E and on line 108 into line 153 into 100B, that will cause data at port 100D to be stored in latch 206, Figure 4, through already described steps. Turning back to Figure 3, when the above mentioned signals are present, port 100C through line 154 through line 110 to computer 13 goes active, through an already disclosed process, causing computer 13 to temporarily suspend operations. Port 98B now momentarily goes active through line 115 into port 100G causing data at port 206C, Figure 4, through line 217 through port 208A to be latched into 208 and at output at port 208C, and, turning back to Figure 3, causes port 100C to go inactive through line 154 through line 110, thereby releasing the wait line to computer 13, thus allowing another byte of data to be transmitted by the above mentioned steps. Immediately after port 98D momentarily goes active, port _*s 96C, 98D, 98E begin to go active in a divide by 8 binary sequence, using clock 96, port 96A through line 128 in port 98K as a count clock. Ports 98C, 98D, 98E through lines 116, 117, 118 through ports 100H, 1001, 100M respectively cause the serialization of the data in circuit 210, Figure 4, as previously described. Serialized data is output port 100L through line 119, into port 102E, where said data is converted to a pulse width modulated signal in circuit 102, output through port 102A through line 135, into port 104C, out port 104A through line 151, through port 136 out line 24, with circuits 102 and 104 functioning as previously described.

After 80 serialized bits have been transmitted by the above mentioned proces, line 106 to computer 13 goes inactive, allowing computer 13 to refresh its memory if so equipped. Line 106 will go active again on the next horizontal line for 80 more bits to be serialized. This process will continue until horizontal line counter 94, following previously described operation, reaches horizontal line 235, at which time port 94F goes active through line 126 into port 98H, causing port 98A to go and stay inactive and terminating all outputs from circuit 98.

The above described data transfer process was on video field 1,^" however a transfer on video field 2 is identical with the exception that ports 94E, 94F, 94A will go active on horizontal line 292, 497, 291 respectively. When an entire transfer has been completed, computer 13 will, under program control, use address lines 113 to port 100E and input/output request line 108 through line 153 to port 100B to cause port 100J through line 125 to port 94B to go and stay inactive, thereby ceasing operation of interface transmitter 20. Video mastering equipment 26 represents one of many commercially available video disc mastering and replication processes that utilize a video signal input from any number of different sources, such as the formatted video signal transmitted over line 24 by the interface transmitter 20, and produce as an end product, the optical video disc 30. All processes involved frcm input signal to finished product are conventionally known and practiced by such companies as Sony Corporation, 3-M Corporation and U.S. Pioneer Corporation. Figure 6 shows a schematic representation of the interface receiver 34. The interface receiver 34 is comprised of a number of circuits, including a sync separator 400 which separates the horizontal sync pulse and field 1 signals from the video signal that is brought in port 34A. The operation of the sync separator 400 is identical to the sync separator 92 of the interface transmitter 20 previously described with port 400A being video input, port 400B being horizontal sync output, port 400C being field 1 sync. A line counter 403 counts horizontal lines to keep track of data being received and sends output signals at intervals determined by data format; a code slice circuit 401 removes the sync, burst and other non-data signals from the input video; a header slice circuit 404 along with a header recognize circuit 406 detects the header flag recorded at the head of each field containing data; a serial to parallel converter circuit 405 converts serial data to 8 bit parallel data for high speed transfer to the computer 44; a frame read circuit 409 signals the computer 44 when to read the frame number; a conversion control circuit 407 tells the computer 44 when conversion of data is to start; a laser recorder controller circuit 410 sends appropriate operational signals to the laser video disc player 32 such as search, fast forward, stop, etc.; a frame number decode circuit 402 decodes the frame number and places it on the computer 44 data buss 42; and an address decode circuit 408 decodes data placed under program control on the address or control buss 40 from the computer 44, with the decoded address data used to initiate control signals.

The computer address and control buss 40 as well as the data buss 42 are shown in Figure 6 by double lines with arrowheads and enumerated as 34C and 34B, respectively. For clarity purposes, these lines are shown by the circuits connected to them, and as many circuits connect to the same lines, they are shown as separate lines. In actual use only one address and control line and one data line would be used. Turning to port 34A, when a video signal from the video disc player 32 is present, the signal travels along line 417, through junction 416, along line 418, and into the horizontal sync separator 400 at port 400A. The horizontal sync pulse and field 1 signals are obtained in the same manner as previously described for the interface transmitter 20 (Figure 3, circuit 92).^" The horizontal sync signal is sent out through port 400B along line 428 to junction 429. The field 1 signal will go active and stay active during field 1 and go inactive during field 2. This signal is sent through port 400C along line 420 to junction 421. Turning back to junction 416, the video signal with data is sent along line 415 into the header slice circuit 404 through port 404A. The header slice circuit 404 determines whether a data header is present. The data header previously described is a line with solid white video contained therein. The header is placed one line ahead of the first data line. If the signal at port 404A is black or does not contain an uninterrupted white level video signal for 40 microseconds, port 404B will remain inactive. If a white level, video signal is present for at least 40 microseconds, then port 404B will go active for an additional 30 microseconds. The line counter 403 is inactive until a field 1 signal is active at port 403A through line 422 from junction 421. Upon receipt of an active field 1 signal, the line counter 403 is initialized by resetting all counters and enabling outputs. Each horizontal line is counted; the count pulse for each line is the horizontal sync pulse received from junction 429 through line 427 in port 403B. When the line counter reaches a predetermined line number, determined by the location of frame numbers placed on the video disc 30 during mastering as previously described, the output at port 403D will go active one line after the frame number. This active signal at port 403D is transferred along line 433 to the read frame circuit 409 and through port 409A of the frame read circuit 409. Turning back to junction 416, the video signal from junction 416 is placed on port 401A of the code slice 401 circuit via line 419. The code slice circuit 401 removes all signals and pulses that are not data from the video sign l by allowing to pass only those portions of the video signal which are above a predetermined internal reference voltage. The data stripped from the video signal is in serial form and sent out port 401B a bit at a time along line 456 through junction 451. With regard to the frame decode circuit 402, the frame number, which is placed on the laser video disc at the time of mastering, is a 24 bit Bl-phase coded signal containing the frame number, and this frame number is brought into port 402A along line 452 from junction 451. The frame number decode circuit 402 will not accept and decode the frame number unless it is enabled, and the enabling signal is received through port 402F. Turning back to the line counter 403, port 403C will go active two lines before the frame number and stay active until after the last line containing the frame number has been completed. The determination of lines which will contain frame numbers will be established as previously described. When port 403C goes active, the enable signal will be sent along line 432 into port 402F of the frame number decode circuit 402. While port 402F is active, the frame number is decoded and placed in registers. The frame number is read into the computer 44 under program control through data lines 34B through port 402B.

Turning to the address decoder 408, the computer 44 under program control brings line 412 active through port 408L. When port 408L is active, any one of the output lines 408B, 408C, 408D, 408E, 408F, 408G, 408H, 4081, ^'408J or 408K can go active depending on the predetermined combination of inputs through lines 34C along line 413 and into port 408A. When output port 408D goes active, an active signal is sent along line 435 to junction with line 454 into port 402C of the frame number decode circuit 402. This places the first 8 bit byte of the frame number on the computer 44 data line 34B. The next 8 bit byte of the frame number is then placed on the data line 34B by bringing port 408E active, and an active signal is sent along line 436 to junction with line 455 into port 402D. The last 8 bit byte is placed on data line 34B by bringing port 408F active, the active signal sent along line 437 to junction with line 456 into port 402E.

Turning back to line counter 403, as previously discussed, the presence of data on a field will be determined by a solid white video signal on the line just before data starts. In order to be certain that a video picture is not present with one line of white, the header recognize circuit 406 will examine the two lines before data starts: one line for a "black" video signal, and the first line before start of data for a white video signal. Port 403E will become active for the duration of one line, two lines before the start of data. Port 403F will become active for the duration of one line, one line before the start of data. Port 406F of the header recognize circuit 406 is an enable port under program control of the computer 44. When the computer program has read the frame number and verified that the frame being read is correct, it will cause an active signal through the address decode 408 port 408B along line 424 and into port 406F of header recognize circuit 406. This will enable circuit 406 until port 406E goes active. If the computer does not want to decode the frame, a signal will be sent out through port 408C along line 425 into port 406E. If an active signal is present at 406E, the. header recognize circuit 406 will be disabled. In the header recognize circuit 406, when port 406F has been pulsed active and line 426 into port 406C is pulsed for one horizontal line, port 406A will read the signal on line 414. If line 414 is inactive, a white line is not present one line before the data header. Port 406B will then receive an active signal along line 423 at the next horizontal line. When port 406B is active, port 406A is again sampled. If line 414 is active, port 406A will be active. If port 406A was inactive when port 406C was active and if port 406A was active when port 406B was active, then port 406D will go and stay active. This will indicate a data flag is present and data can be decoded at the start of the next horizontal line. The active signal at port 406D will cause an active signal along line 434 to junction 447.

Circuit 407 tells computer 44 when conversion is to take place and which field is being converted. Computer 44 auses

OM port 408H to go active by a previously described process, causing line 439 through line 457 to port 407B. This places a data byte on the data buss 34B through port 407C through line 458, the value of which is determined try input ports 407A and 407D. When 407A is active through line 446 from junction 447, this^' tells computer 44 that data is to be converted; when port 407D from line 445 through junction 444 through line 421 through junction 431 is active, this signals computer 44 that data is on field 1. in a similar manner circuit 409 tells computer 44 when to read frame number from circuit 402. Computer 44 causes port 4081 to go active, through line 440 through line 459 through port 409B. This places a byte of data on the data buss 34B through port 409C through line 460, the value of which is determined by input ports 409A and 409D. When port 409A is active through line 433 from port 403D, this tells computer 44 to read frame number from circuit 402. When port 409D through line 443, junction 444, is active, this tells computer 44 that frame number is on field 1. Turning now to the serial to parallel converter circuit 405, this circuit converts the serial data that is stripped from the video signal by the code slice circuit 401 and which is present at junction 451, sent through line 449 and into port

405A. Port 405F from junction 447 through line 448 is an enable input. If port 405F is active, conversion can take place, and port 405E through line 456 goes active, which is the ready line to computer 44. If port 405F is inactive, conversion cannot take place. Port 405G from line 430 from junction 429 is a momentary horizontal sync pulse used to reset circuit 405 counters to "0". After computer 44 has recognized data sent by circuit 407, and receives ready signal from port 405E through line 456 to line 34D, then computer 44 requests a byte of data be placed on data buss 34B through line 456 from port 405C. Computer 44 causes this by causing port 408G to go active, through line 438 through line 457 to port 405B, also causing port 405D through line 455 to line 34D, to go active, causing computer 44 to temporarily cease operation. This is -21-

the wait line to computer 44. After circuit 405 has received and decoded 8 pulses from port 405A and made this byte of data available on data buss 34B through line 456 through port 405C, port 405D, the wait line, goes inactive, allowing computer 44 to receive byte of data and request the next. This sequence continues for 10 such requests and then port 405E through line 456 to line 34D, the ready line, is made inactive until a pulse at port 405G resets port 405E active. This conversion process takes place until computer 44 causes port 408C to go active, which terminates the conversion.

Circuit 410 will take a byte of data from buss 34B through line 463 through port 410C when port 408J is caused to go active through line 441, through line 461, and port 410A, and convert that byte of data to a unique and predetermined signal out of port 410D through line 464 to control port 36 which goes to video disc player 32 to control its functions. This command is latched into circuit 410 until port 408K through line 442 through line 462 through port 410B goes active, at which time ouput from circuit 410 is terminated. The present invention provides several major advantages including greatly reduced replication costs for large fixed data bases. The time to replicate approximately 300 mbytes on a magnetic disc is 30 minutes, while the time to replicate approximately 300 mbytes o a video disc is approximately 1 second. Further, the present invention provides greatly improved environmental stability of the entire retrieval system, since the laser disc is practically unaffected by an adverse environment. The cost of the drive to play a video disc as opposed to a magnetic disc is less than 10% of the cost of the magnetic disc drive. And since there is no physical contact between a reading mechanism and the video disc, and the data is below the surface on a video disc, long term integrity of the data is much better than any presently known magnetic system. It is clear that the present invention is well adapted to carry out the objects and to attain the ends and advantages mentioned as well as those inherent therein. While presently preferred embodiments of the invention have been described for purposes of this disclosure, numerous changes may be made which will readily suggest themselves to those skilled in the art and which are encompassed within the invention disclosed and as defined in the appended claims.

Claims

What is claimed is:

1. A laser video disc storage and retrieval system for receiving digital data in the form of a first data signal from a computer, the system comprising: interface transmitter means for forming a video formatted first video signal which contains the data of the first data signal so that the first video signal is receivable by disc mastering equipment for placement on a laser video disc.

2. The laser video disc storage and retrieval system of claim 1 in which at least a portion of the first data signal on the laser video disc is retrieved in the form of a second data signal containing a selected portion of the data, the system further comprising: interface receiver means for receiving the second video signal and forming a second data signal compatible with a computer so that the data contained in the second data signal is readable by a computer.

3. A laser video disc storage and retrieval system for use with a computer which has an output buss through which a digital first data signal is transferrable to external equipment, the system comprising: interface transmitter means connected to the output buss for video formatting the first data signal received therefrcm so as to form a formatted first video signal which contains the data of the first data signal, the first video signal capable of being placed onto a laser video disc by disc mastering equipment in memory format; means for interrogating the laser responsive video disc to produce a second video signal conforming to a selected portion of the formatted first video signal in the memory format of the video disc; and interface receiver means for receiving the second video signal from the playback interrogating means and forming a second data signal compatible with the computer so that the data contained in the selected portion of the memory format is readable by a computer.

4. A laser video disc storage and retrieval system for use with a computer which has an output buss through which a first data signal is transferrable to external equipment, the system comprising: interface transmitter means connected to the output buss for formatting the first data signal received therefrom and for forming a formatted first video signal which contains the data of the first data signal; mastering means for receiving the formatted first video signal and impressing the formatted first video signal in memory format on a laser responsive video disc; playback means for interrogating the laser responsive video disc to produce a second video signal conforming to a selected portion of the formatted first video signal in the memory format of the video disc; and interface receiver means for receiving the second video signal from the playback means and forming a second data signal compatible with the computer so that the data contained in the selected portion of the memory format is readable by the computer.

OMP