EP0089607B1

EP0089607B1 - Mains-wired monitoring and security system

Info

Publication number: EP0089607B1
Application number: EP83102557A
Authority: EP
Inventors: Umberto De Monte; Daniele Gorasso
Original assignee: Zeltron Istituto Zanussi per lElettronica SpA
Current assignee: Zeltron Istituto Zanussi per lElettronica SpA
Priority date: 1982-03-18
Filing date: 1983-03-15
Publication date: 1986-10-15
Also published as: DE3367037D1; EP0089607A1; ATE23000T1; IT8245711A0; IT1159756B

Abstract

A mains-wired monitoring and security system comprises an electric supply mains network (10) having connected thereto a control unit, a plurality of detecting units, and a plurality of actuating units. Each unit includes associated counter means (5, 15, 29) controlled in synchronism with each other. Each detecting unit transmits a coded signal (f2) along the mains network when an associated sensor (14) detects an alarm condition and its associated counter means (15) simultaneously counts a specific number N. At least one actuating unit activates an associated actuator (37) in response to said coded signal if its associated counter simultaneously counts the number N. The central unot visually displays said number N, which is common to at least one detecting unit and at least one actuating unit, in response to said coded signal.

Description

This invention relates to a mains-wired monitoring and security system according to the precharacterising part of patent claim 1. Such a system is known from GB-A-2 023 896.
The above specification discloses a heat insulated pipe system comprising electric wires incorporated in the heat insulating material and local detectors for detecting an increase of electric conductivity between the wires due to moisture intrusion into the material. Clock pulses in the form of cycles of the power ac drive individual counters at the detectors, which are sequentially counted full for temporarily switching the detector outputs to a common signal wire going to a central station, such that any moisture responding detector is readily identified by the associated counter step of a central counter. In the case that moisture intrusion is existent at one of the detector locations, the respective detector will not issue a signal so that the central unit is able to verify the location of moisture intrusion. However, if a detector suffers from a failure, thus being unable to issue a signal, the central station is unable to distinguish whether the drop-out of the respective signal is due to moisture intrusion or to a failure of the respective detector. Furthermore, the system being driven and synchronised by the mains ac, a dropout of the power source will render the system, in total, inoperative. Thus, such a system will not be suitable for monitoring objects such as buildings and residential premises in which the power supply is accessible for unauthorised persons.
US-A-4156112 discloses a control system using time division multiplexing including, apart from a central unit and a plurality of sensing units, a plurality of actuating units. Each unit comprises counters which are synchronised by the central unit through a special synchronisation line, thus, additional wiring which undesirably complicates the entire system is necessary.
It is the object of the present invention to provide a mains-wired monitoring and security system of the aforementioned kind which is of relatively simple construction and reliable operation, which may be employed for monitoring a plurality of zones and for controlling a plurality of actuators spaced throughout the building and which is not affected by drop-outs of the mains power supply. Moreover, this system should provide the ability for self-monitoring.
This object is attained by the characterising features of patent claim 1. Preferred embodiments of the invention are the subject matter of the subclaims.
The characteristics and advantages of the invention will become more clearly evident from the following description of an exemplary embodiment with reference to the accompanying drawings, wherein:

Figs. 1 to 3 show block diagrams of individual units connected to each other through an electric supply mains network in a preferred embodiment of a monitoring and security system according to the invention.

With reference to Fig. 1, the system comprises a central control unit provided with an independent power supply (not shown). The central unit includes a carrier wave transmitter 9 comprising an oscillator and a comparator (known and therefore not shown). Transmitter 9 is adapted to continuously generate a synchronizing signal having a frequency f1 (for instance 100 kHz), which is applied to output terminal 38. In a per se known manner, transmitter 9 is adapted to apply the synchronizing signal also to a further output terminal 39 as long as a logic enable signal is present at its input terminal 40.
Output terminal 39 of transmitter 9 is connected to an electric supply mains network 10 of a building through an interface 11 adapted to stay the mains voltage.
Output 38 of transmitter 9 controls a frequency divider 4 having a dividing proportion of D=f_1/f₀ (for instance equal to 1000 in the example described), wherein f0 (equal to 100 Hz) is the frequency of the output signal of frequency divider 4, said output signal being employed for the timing control of the system as will be described hereinafter.
The output of frequency divider 4 is applied to a counter stage 5 comprising for instance two four-bit counters in the form for instance of respective integrated circuits CD 4029. Counter stage 5 is adapted to cyclically count up to a maximum number M (for instance M=128) and is in a per se known manner designed so as to present two successive counting sequences from 0 to M/2 to its main output 6 during each counting cycle T=₁.₂₈ seconds. Counter stage 5 has a further output 8 to which it applies a logic enable signal (level "1") for the duration of one counting step (i.e. 10 msec in the example described) whenever the maximum count M is attained. Output 8 of counter stage 5 is connected to input 40 of transmitter 9, while counter outputs 6 are applied to respective inputs of a display device 7 for instance of the luminous diode (LED) type.
The central unit further comprises a signal receiver 12, the input of which is connected to mains network 10 through interface 11, while its output in the form of a logic signal controls a corresponding input of a logic control stage 42. In particular, receiver 12 normally generates a logic level "0" at its output, said output changing to logic level "1" when receiver 12 detects a coded signal at its input which, as will be explained in detail later, has a frequency f2 (e.g. 80 kHz).
Logic stage 42 has a further input connected to the output of a configuration memory 13 consisting for example of two integrated circuits CD 4031 and constituting a shift register having a total of M memory locations. In a per se known manner, shift register-13 is initially programmed by storing the presence or absence of individual peripheral units of the system to be described later at corresponding memory locations. In the described example, the absence of peripheral units will be stored at the first sixty-four locations, while the presence of peripheral units will be stored in corresponding ones of the second group of sixty-four locations. The control input 41 of register 13 is connected to the output of frequency divider 4, so that the 128 locations of the register will be cyclically scanned with the frequency f0 in synchronism with counter stage 5. Register 13 is adapted to generate a logic level "1" at its output only on the scanning of memory locations having stored therein the presence of at least one peripheral detecting unit.
Logic control stage 42 may be composed of a plurality of commercially available logic elements and is provided with two outputs 46 and 47 alternatingly activated by successive counts of M/2. Output 46 is activated during the count from 0 to M/2 for generating the same logic level as present at the output of receiver 12. Output 47 is activated during the count from M/2 to M to generate a logic level "1" only if there is a difference between the logic levels at the outputs of receiver 12 and register 13. Output 47 of stage 42 is additionally adapted to activate an indicator device 45 when at level "1".
An enable input 43 of display device 7 is selectively activated via a manually operable switch 44 or via one of the outputs 46 or 47 of stage 42. In every case that a logic level "1" is present at input 43, display device 7 is activated to display the count (between 0 and M/2) actually present at the outputs of counter stage 5.
The monitoring and security system according to the invention further includes a plurality of peripheral detector units, provided with independent power supply (not shown), each one of which having the construction as shown in Fig. 2 and being located at any point of the building to be monitored. As will be explained in the following, each peripheral detector unit is identified by a specific number N<_M/2 which may also be common to a group of such units.
With reference to Fig. 2, each peripheral detector unit comprises a detecting device 14 including a sensor (not shown) which may be of a per se known type and/or of different type for each such unit as required. The sensor may thus for example be a gas leak sensor, a break-in sensor, an inundation sensor, an incendiary sensor or the like. The output of detector 14 is normally at the logic level "0" and is adapted to change to level "1" whenever the sensor is activated by detecting an alarm condition. Each peripheral detector unit further comprises a counter stage 15 which may be composed of three four-bit counters of the type CD 4029. Counter stage 15 is programmed in a per se known manner to cyclically count up to the number M=128 and to generate a logic enable signal (logic level "1") at an output 16 (normally at logic level "0") whenever the count of N:5M/2 is reached. Counter stage 15 is in addition programmed to generate a logic command signal (logic level "1") at an output 17 (normally at logic level "0"), whenever the counter of N+M/2 is reached. The said enable and command signals are generated at the respective outputs 16 and 17 of counter stage 15 for the duration of one counting step, i.e. for 10 msec in the example described. As already explained above, each peripheral unit may be identified by a different number N.
The output of detector 14 and the output 16 of counter stage 15 are connected to respective inputs of a comparator stage 18, consisting for instance of an AND gate, arranged to generate an output command signal (logic level "1") in response to the simultaneous presence of logic level "1" at its inputs. Output 17 of counter stage 15 and the output of comparator 18 are applied to the command input of a per se known carrier wave transmitter 19, comprising for instance an oscillator for generating a coded signal having, as already explained above, a frequency f2=80 kHz in response to the presence of logic level "1" at its command input. The output of transmitter 19 is connected to mains network 10 through an interface unit 20 adapted to stay the mains voltage.
Each peripheral detecting unit further includes a carrier wave receiver 21 the input of which is connected to mains network 10 through interface unit 20.
Receiver 21 is substantially composed of a phase-locked loop circuit (PLL) which may be in the form of an integrated circuit of the type CD 4046. In a per se known manner receiver 21 is adapted to generate at its output 22 a reset signal which is applied to a reset input of counter stage 15 in response to receiving the already mentioned synchronization signal having the frequency f1 at its input. Also in a known manner, the phase-locked loop circuit of receiver 21 is controlled by the periodically received synchronization signal (received for each counting cycle T) for continuously generating a signal having the synchronization frequency f1 at a further output 23. The latter is applied to a counting input 25 of counter stage 15 through a frequency divider 24 having a dividing coefficient D=f_1/f₀, i.e. 1000 in the example described. The counting input 25 of counter stage 15 is thus controlled with the frequency f0 and thus in synchronism with the counter 5 of the central unit shown in Fig. 1.
The monitoring and security system according to the invention further includes a plurality of peripheral actuating units, provided with independent power supply (not shown), each of which is designed as shown in Fig. 3 and located at any suitable point of a building to be monitored. As will be explained in the following, each actuating unit is identified by a specific number N which may be common to a plurality of actuating units and/or to one or a plurality of peripheral detecting units. One or several detecting units may be associated with one or several actuating units as required.
With reference to Fig. 3, each peripheral actuating unit is provided with a carrier wave receiver 26, the input of which is connected to mains network 10 through an interface unit 27 adapted to stay the mains voltage.
Receiver 26 is identical to receiver 21 of Fig. 2 and may thus be comprised of an integrated circuit of the type CD 4046.
In particular, receiver 26 is adapted to generate at its output 28 a reset signal which is applied to a corresponding input of a counter stage 29 in response to receiving the synchronization signal having the frequency f1 at its input. In addition, the phase-locked loop circuit of receiver 26 is controlled by the periodically received synchronization signal (received once for each counting cycle T, as already explained) to continuously generate a synchronization signal having the frequency f1 at a further output 30. Output 30 of receiver 26 is applied to a counting input 31 of counter stage 29 through a frequency divider 34 having the same dividing coefficient D=f1/f0 as frequency divider 24 of Fig. 2. Thus the counting input 31 of counter stage 29 is also controlled with the frequency f0, i.e. in synchronism with the counter stage 5 of the central control unit.
Counter stage 29 may be constituted by two four-bit counters of the type CD 4029, analogous to counter stage 5 of Fig. 1.
In a per se known manner, counter stage 29 is programmed to cyclically count up to the number M and to generate at an output 32 a logic enable signal (logic level "1") each time it reached the count N.
As already said, the number N≤MI2 may be different for each peripheral unit.
The peripheral actuating units each include a further carrier wave receiver 33, the input of which is connected to mains network 10 through interface 27. Receiver 33 may likewise be formed, analogously to receiver 12 of Fig. 1, by an integrated circuit of the type CD 4046 made by RCA, and is adapted to generate at its output 35 a command signal (for example logic level "1") which is applied to a corresponding input of a comparator and integrator stage 36 in response to receiving the coded signal having the frequency f2 at its input.
Stage 36 is of a per se known type and adapted to store (for instance by means of a load capacitor (not shown)) the command signal received from receiver 33 whenever the enable signal is simultaneously present at the output of counter 29.
In addition, stage 36 is adapted to generate an activating output signal for an associated actuator 37 whenever it has stored the above mentioned command signal for a predetermined number of times (for instance three times) within a predetermined period of time.
Actuator 37 may be of any type adapted to the specific purpose corresponding to the number N identifying the respective actuating unit and thus the type of the sensor provided in the at least one peripheral detecting unit identified by the same number N. Actuator 37 may thus for instance comprise a solenoid valve adapted to interrupt the supply of a combustible gas or to activate an anti-incendiary sprinkler system, apparatus for closing fireproof doors, an alarm siren or the like.
In operation of the system, counter 5 of the central Unit (Fig. 1) counts progressively with the frequency f0 determined by frequency divider 4. On attaining the count of M, output 8 of counter 5 enables transmitter 9 to generate at its output the synchronization signal having the frequency f1 for a duration of 10 msec. This signal is applied to mains network 10 through interface 11 and thus to all of the peripheral detecting and actuating units shown in Figs. 2 and 3, respectively.
In each peripheral detecting unit the synchronization signal is received, through interface unit 20, by the respective receiver 21, causing the latter to reset counter 15 by way of its output 22 and to generate at its output 23 a timing signal in synchronism with the frequency f1, as already explained. Receiver 21 thus controls counter 15 with the frequency f0 through frequency divider 24; after each reset operation (carried out each time the count of M is attained, as already explained, and effective to periodically eliminate any irregularity in the function of counter 15) counter 15 is in step with the timing signal generated by frequency divider 4 of the central unit.
As counter stage 15 attains the count of N, it generates at its output 16 the logic level "1" which, only in case that sensor 14 be activated by an alarm condition, enables comparator 18 to activate transmitter 19. This means that if sensor 14 is active at the time that the count of N is attained, transmitter 19 applies the coded signal with the frequency f2 to mains network 10 for the duration of one counting step.
In an analogous manner, transmitter 19 generates the same coded signal at its output, irrespective of the condition of sensor 14 and under the control of output 17 of counter 15, each time the said counter attains the count of N+M/2, it being supposed that each peripheral detecting unit provided within the system is identified by a different number N:5M/2.
Each complete counting cycle from 0 to M (having a duration T of 1.28 sec in the example described) is divided into two periods of equal duration: a first counting period from 0 to M/2, and a second period for counting from M/2 to M, said periods being designates T1 and T2, respectively.
During the period T1, coded signals having the frequency f2 are transmitted along mains network 10 only if at least one detecting unit is activated by an alarm condition; in this case the code signal is transmitted along the mains network at the instant at which the count of N identifying the activated detecting unit is attained.
During the period T2 (which, as will become more clearly evident in the following, is employed for carrying out an auto-diagnosis of the system), a plurality of code signals having the frequency f2 are transmitted along mains network 10 in timed succession. Each of these code signals is generated by a different detecting unit at the instance at which the count of N identifying the respective unit is attained.
With reference to Fig. 1, it is now supposed that switch 44 normally connects input 43 of display device 7 with output 46 of logic stage 42.
If during the period T1 the central control unit receives a coded signal having the frequency f2 (indicative of an alarm condition of a detecting unit N), receiver 12 generates a logic signal "1" which is applied to the input 43 of display device 7 through output 46 of stage 42 and switch 44. Display device 7 is thereby caused to display, for repetitive periods of 10 msec each, the counted number present at outputs 6 of counter 5, which corresponds to the number N identifying the activated detecting unit. This periodic display continues until the cause for the alarm condition has been remedied, and allows the cause of the alarm to be immediately recognized.
During the period T2, and as long as the entire system functions correctly, the central control unit receives coded signals having the frequency f2 each time register 13 generates at its output the logic level "1", while at output 47 of stage 42 there is normally present a logic level "0".
If, at the time that register 13 generates the logic output level "1", receiver 12 does not receive a coded signal, the absence of this signal is indicative of a malfunction existing in the components and/or connections of a corresponding peripheral detecting unit. Under these conditions, the output of receiver 12 is at logic level "0", while output 47 of stage 42 is at logic level "1", thereby activating signalling or indicating device 45. The user is thus warned of the existing condition of malfunction and may now actuate switch 44 for connecting input 43 of display device 7 with output 47 of logic stage 42, causing display device 7 to display, for repetitive periods of 10 msec each, the count appearing at the outputs of counter 5 and corresponding to the number N identifying the peripheral detecting unit beset by the malfunction. This enables the user to intervene in good time for remedying the cause of the malfunction.
As regards the peripheral actuating units (Fig. 3), the synchronizing signal having the frequency f1 is received through interface unit 27 by receiver 26, causing the latter to reset counter 29 through its output 28 and to generate at its output 30 a signal in step with the frequency f1, as already said. Receiver 26 thus controls counter 29 through frequency divider 34 with the frequency f0; after each reset operation (carried out each time the count of M is attained and employed for periodically eliminating any irregularity in the function of counter 29), the counter 29 is in step with the timing signal generated by frequency divider 4 of the central unit.
If during the counting period T1 receiver 33 detects the presence of a coded signal having the frequency f2 in the mains network 10, it generates a command signal at its output, as already indicated.
This command signal, however, is able to activate comparator 36 only if counter 29 simultaneously generates an enable signal at its output 32. This means that only the peripheral actuating unit, or units, respectively, identified by the same number N as the detecting unit generating the coded signal, is or are able to store the command signal in its or their comparator-integrator 36. Only if the command signal repeats itself over the above noted period of time for a predetermined number of complete counting cycles (three in the example described), does comparator 36 activate actuator 37 as already described above. This permits unnecessary and unwanted activation of actuator 37 caused for instance by faults in the mains network to be avoided and ensures such activation to take place only under genuine alarm conditions, thus contributing to the reliability of the entire system.
If receiver 33 detects command signal during the autodiagnosis period T2, comparator 36 can obviously not be activated, as output 32 of counter 29 is at logic level "0" as already stated. In every case, the entire system functions also in the absence of voltage in the mains network 10, thanks to its independent power supply.
The above description clearly shows the structural simplicity and operational reliability of the monitoring and security system according to the invention, in which the central unit and the peripheral units operate in synchronism, and in which the peripheral units are cyclically scanned during alternating alarm signal periods and auto- diagnosis periods.
The described system may obviously varied in any suitable manner within the scope of the invention. It is thus obvious to the skilled artisan that with slight modifications of the circuitry the peripheral actuating units may also be provided with means for carrying out an autodiagnosis analogous to those provided for the detecting units (transmitter 19 and associated connections in Fig. 2).
In addition, the timing control of the monitoring and security system may be directly derived from mains network 10; in this case, frequency dividers 4, 24 and 34 are simply replaced by per se known mains voltage zero passage detectors.

Claims

1. Mains-wired monitoring and security system, comprising an electric supply mains network (10) having connected thereto at least one central control unit (Fig. 1) and a plurality of peripheral detecting units (Fig. 2), said central control unit comprising a counter (5) adapted to cyclically count up to a number M, each peripheral detecting unit comprising a counter (15) having accorded a specific number Mm, said counter (15), providing an output when the count equals N, an associated detector (14) for detecting an alarm condition, and signal transmitting means (18,19) being controlled by said detector (14) and by said counter (15), said transmitting means (18, 19) being responsive to the coincidence of said counter and detector outputs for providing· a respective coded signal (f2) of short time duration to be output to said mains network (10) and received by said central control unit, said central control unit providing counting signals (f1) and further a synchronisation signal at each count of said number M, resetting the counters (5, 15), characterised in that separate actuating units (Fig. 3) are connected to said mains network (10) and each being provided with receiving means (26, 33) for the signals (f1, f2) transmitted from, the central control unit and from the peripheral detecting units, respectively, said actuating units each being provided with a counter (29) and being accorded to one of the numbers accorded to at least one of said peripheral detecting units and being provided with an actuator (37) being activated upon receipt of a signal (f2) transmitted from at least one of said peripheral detecting units accorded to the same number as said actuating unit in response to a signal issued from the detector (14) of the respective detecting unit, each of said central control, detector and actuator units, respectively, being provided with independent power supply means.

2. Monitoring and security system according to claim 1, characterised in that the actuator (37) of each peripheral actuating unit is adapted to be activated through comparator-integrator means (36) having a first input (35) controlled by a command signal of an alarm receiver (33) in response to said coded signal (f2), and a second input (32) controlled by said associated counter (29) at each count of the respective number N, with an enable signal permitting said command signal to be stored.

3. Monitoring and security system according to claim 1, characterised in that said number N is smaller than or equal to M/2, each peripheral detecting unit being adapted to transmit said coded signal (f2) along said mains network (10) each time the associated counter (15) counts a specific number N plus M/2, said central unit being provided with memory means (13) for storing said number N plus M/2 of all peripheral detecting units, said memory means (13) being controlled by synchronisation means for cyclically reading said numbers and for actuating a warning device (45) if the central unit detects the absence of said coded signal (f2) at the instance of reading one of said numbers N plus M/2.