EP0087919A3 - A static type semiconductor memory device including a word line discharging circuit - Google Patents

A static type semiconductor memory device including a word line discharging circuit Download PDF

Info

Publication number
EP0087919A3
EP0087919A3 EP83300945A EP83300945A EP0087919A3 EP 0087919 A3 EP0087919 A3 EP 0087919A3 EP 83300945 A EP83300945 A EP 83300945A EP 83300945 A EP83300945 A EP 83300945A EP 0087919 A3 EP0087919 A3 EP 0087919A3
Authority
EP
European Patent Office
Prior art keywords
memory device
word line
type semiconductor
semiconductor memory
device including
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP83300945A
Other versions
EP0087919A2 (en
EP0087919B1 (en
Inventor
Kouichi Kitano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of EP0087919A2 publication Critical patent/EP0087919A2/en
Publication of EP0087919A3 publication Critical patent/EP0087919A3/en
Application granted granted Critical
Publication of EP0087919B1 publication Critical patent/EP0087919B1/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/414—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the bipolar type
    • G11C11/415—Address circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
EP83300945A 1982-02-27 1983-02-23 A static type semiconductor memory device including a word line discharging circuit Expired EP0087919B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP57029796A JPS58147882A (en) 1982-02-27 1982-02-27 Word line discharging circuit of semiconductor storage device
JP29796/82 1982-02-27

Publications (3)

Publication Number Publication Date
EP0087919A2 EP0087919A2 (en) 1983-09-07
EP0087919A3 true EP0087919A3 (en) 1986-05-07
EP0087919B1 EP0087919B1 (en) 1989-10-11

Family

ID=12285957

Family Applications (1)

Application Number Title Priority Date Filing Date
EP83300945A Expired EP0087919B1 (en) 1982-02-27 1983-02-23 A static type semiconductor memory device including a word line discharging circuit

Country Status (5)

Country Link
US (1) US4611303A (en)
EP (1) EP0087919B1 (en)
JP (1) JPS58147882A (en)
DE (1) DE3380717D1 (en)
IE (1) IE55517B1 (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4601014A (en) * 1982-03-19 1986-07-15 Fujitsu Limited Semiconductor memory with word line charge absorbing circuit
US4570240A (en) * 1983-12-29 1986-02-11 Motorola, Inc. AC Transient driver for memory cells
US5278795A (en) * 1987-03-27 1994-01-11 U.S. Philips Corporation Memory circuit having a line decoder with a Darlington-type switching stage and a discharge current source
US4951255A (en) * 1989-04-14 1990-08-21 Atmel Corporation Memory current sink
CA2042432A1 (en) * 1990-05-31 1991-12-01 Robert M. Reinschmidt Memory selection circuit
JPH05205483A (en) * 1992-01-23 1993-08-13 Sony Corp Bipolar ram circuit
US8547756B2 (en) 2010-10-04 2013-10-01 Zeno Semiconductor, Inc. Semiconductor memory device having an electrically floating body transistor
US8130547B2 (en) 2007-11-29 2012-03-06 Zeno Semiconductor, Inc. Method of maintaining the state of semiconductor memory having electrically floating body transistor
US10340276B2 (en) 2010-03-02 2019-07-02 Zeno Semiconductor, Inc. Method of maintaining the state of semiconductor memory having electrically floating body transistor

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0025316A2 (en) * 1979-08-30 1981-03-18 Fujitsu Limited A termination circuit for word lines of a semiconductor memory device

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5341968A (en) * 1976-09-29 1978-04-15 Hitachi Ltd Semiconductor circuit
US4168490A (en) * 1978-06-26 1979-09-18 Fairchild Camera And Instrument Corporation Addressable word line pull-down circuit
JPS5831673B2 (en) * 1979-08-22 1983-07-07 富士通株式会社 semiconductor storage device
JPS5841597B2 (en) * 1980-12-24 1983-09-13 富士通株式会社 Semiconductor memory discharge circuit
US4393476A (en) * 1981-07-13 1983-07-12 Fairchild Camera & Instrument Corp. Random access memory dual word line recovery circuitry
JPS6052518B2 (en) * 1981-12-18 1985-11-19 富士通株式会社 semiconductor storage device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0025316A2 (en) * 1979-08-30 1981-03-18 Fujitsu Limited A termination circuit for word lines of a semiconductor memory device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS, 16th February 1978, pages 98-99, IEEE, New York, US; A. HOTTA et al.: "Session IX: static and nonvolatile memories: Tham 9.1: A high-speed low-power 4096 x 1-bit bipolar RAM" *

Also Published As

Publication number Publication date
JPH0156472B2 (en) 1989-11-30
EP0087919A2 (en) 1983-09-07
JPS58147882A (en) 1983-09-02
IE55517B1 (en) 1990-10-10
DE3380717D1 (en) 1989-11-16
EP0087919B1 (en) 1989-10-11
IE830418L (en) 1983-08-27
US4611303A (en) 1986-09-09

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