EP0066603A1 - Systeme de controle electrique - Google Patents

Systeme de controle electrique

Info

Publication number
EP0066603A1
EP0066603A1 EP19820900205 EP82900205A EP0066603A1 EP 0066603 A1 EP0066603 A1 EP 0066603A1 EP 19820900205 EP19820900205 EP 19820900205 EP 82900205 A EP82900205 A EP 82900205A EP 0066603 A1 EP0066603 A1 EP 0066603A1
Authority
EP
European Patent Office
Prior art keywords
component
electrical
monitoring
components
selectively
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP19820900205
Other languages
German (de)
English (en)
Inventor
Stephen J. Kreinick
Bradley J. Denny
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ivac Medical Systems Inc
Original Assignee
Ivac Medical Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ivac Medical Systems Inc filed Critical Ivac Medical Systems Inc
Publication of EP0066603A1 publication Critical patent/EP0066603A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
    • G01R31/2834—Automated test systems [ATE]; using microprocessors or computers

Definitions

  • This invention relates generally to improvements in electrical monitoring systems and, more particularly, to a new and improved system for determining electrical circuit integrity in complex electronic systems, such as computers, medical instrumentation and the like, whereby a minimum of dedicated electronic hardware can be used to monitor a large number of electrical components.
  • Such components may include resistors, diodes, switches, thermisters, optoelectronic transducers, the various elements of light emitting displays, which make up complex electronic systems, such as computers, or are critical components in medical instrumentation and the like.
  • resistors diodes, switches, thermisters, optoelectronic transducers, the various elements of light emitting displays, which make up complex electronic systems, such as computers, or are critical components in medical instrumentation and the like.
  • the provision of appropriate monitoring and evaluation circuitry for a large number of electrical components has generally required a concomitant allocation of substantial dedicated electronic hardware for this purpose, with attendant high cost and circuit complexity.
  • the monitoring and evaluating circuitry can be vast indeed.
  • the present invention provides a new and improved electrical system for uniquely energizing and monitoring the performance of any one of a plurality of electrical components which can be selectively addressed, and evaluating the integrity of such components rapidly, one at a time, by a single comparator system which provides a measure of the component performance.
  • the invention provides a new and improved electrical system for uniquely energizing and monitoring the performance of any one of a plurality of electrical components connected in a row and column energization and connection matrix which can be selectively addressed by a computer controlled address selection subsystem or the like, as by a microprocessor.
  • a microprocessor with an 8-bit output port drives a pair of 4 to 16 decoders for selecting individual row and column switches in the component connection matrix. All of the row switches are connected to supply a common power source to the selected row, and all of the column switches are connected to ground through a common resistor ladder.
  • a window comparator compares the resistor ladder voltage with maximum and minimum voltages to provide input over a single line, or set a single computer input bit, as a measure of the performance of any selectively addressed and energized component.
  • the new and improved electrical monitoring system of the present invention is capable of accurately and reliably monitoring a large number of devices.
  • an 8-bit output port can energize and monitor up to 256 devices, and two 8-bit ports can energize and monitor up to 65,536 devices, while still requiring only one feedback bit to test all of the devices.
  • a plurality of electrical components to be energized and monitored are each electrically connected for unique and selective energization between a single row and single column in a connection array defining a row and column component connection and energization matrix.
  • Each column and each row represents an electrical conductor.
  • Each individual row is selected by activating its corresponding row switch. Accordingly, switches 16 - 19 control the selection of each of Rows 1 - N, respectively. Similarly, a plurality of switches 20 - 23 may be activated, one at a time, to individually select any one of Columns 1 - N, respectively.
  • a computer address selection subsystem which may be embodied within a microprocessor or the like, is illustrated as having an 8-bit output port, by way of example, for driving a row decoder
  • each row decoder 26 and column decoder 27 is a 4 to 16 line decoder, the pair of decoders can define 256 unique row and column addresses for electrical components.
  • the row decoder 26 selects one of the switches 16 - 19 and the column decoder 27 selects one of the switches 20 - 23, depending upon the particular component to be addressed in accordance with the instructions from the computer address selection subsystem 25. Once addressed in this manner, the selected component is automatically energized and its circuit integrity or performance is monitored.
  • all of the row switches 16 - 19 are adapted to connect their respective rows to a common source of electrical power +V when any individual switch is activated. Similarl00 all of the column switches 20 - 23 are connected to ground through a conventional resistor ladder network 30.
  • the computer address selection subsystem 25 will generate the address Row 2, Column 2.
  • Row decoder 26 will activate switch 17 and column decoder 27 will activate switch 21 to complete the circuit from the source +V, through the diode 13, and through the resistor ladder network 30 to ground.
  • the resistor ladder network is simply a resistor string to which the various components being monitored are connected, and different components, depending upon the electrical current they are designed to carry, may be connected to different resistors in the ladder network.
  • the electrical voltage drop across the resistor ladder network 30 is directed as input to a suitable comparator network 31, which may be a window comparator or the like.
  • the resistor ladder network voltage is compared with maximum and minimum reference voltages in the comparator network 31 to determine the circuit integrity or performance of the selectively addressed and energized component.
  • the results of such a comparison are then directed over a single line 32 as a performance measure, typically a single computer input bit, to a computer monitoring subsystem 33 which may also typically be embodied in a microprocessor or the like.
  • a single 8-bit output port can energize and monitor up to 256 electrical components and yet require only a single feedback bit to the monitoring subsystem 33.
  • a pair of 8-bit ports can monitor up to 65,536 electrical components and still require only a single feedback bit.
  • the system of the present invention minimizes the quantity of electronic hardware ordinarily required for determining circuit integrity in complex electronic systems, such as computers, medical instrumentation and the like, and vastly increases the number of electrical components which can be energized and mqnitored by otherwise limited electronic hardware and software.
  • the new and improved electrical monitoring system is accurate, reliable, and satisfies a long existing need in the electrical arts for such a system.

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Testing And Monitoring For Control Systems (AREA)

Abstract

Systeme electrique d'excitation et de controle du fonctionnement d'un composant electrique quelconque parmi une pluralite de composants electriques connectes dans une matrice a rangees et colonnes qui peuvent etre adressees selectivement par un sous-systeme de selection d'adresses commandee par ordinateur. Un microprocesseur avec un point de connexion de sortie a 8 bits (25a, 25b) commande une paire de decodeurs (4 a 16) (26, 27) pour selectionner des commutateurs individuels de rangees et de colonnes (16-19, 20-23) dans la matrice de connexion des composants, tous les commutateurs de colonne etant connectes a la terre par l'intermediaire d'une resistance en echelle (30), et un comparateur a fenetre (31) compare la tension de la resistance en echelle avec les tensions maximum et minimum pour determiner un seul bit d'entree d'ordinateur (32) comme une valeur de mesure de la performance d'un composant adresse et excite de maniere selective.
EP19820900205 1980-12-15 1981-11-27 Systeme de controle electrique Withdrawn EP0066603A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US21676380A 1980-12-15 1980-12-15
US216763 1988-07-08

Publications (1)

Publication Number Publication Date
EP0066603A1 true EP0066603A1 (fr) 1982-12-15

Family

ID=22808411

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19820900205 Withdrawn EP0066603A1 (fr) 1980-12-15 1981-11-27 Systeme de controle electrique

Country Status (2)

Country Link
EP (1) EP0066603A1 (fr)
WO (1) WO1982002096A1 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2150696B (en) * 1983-11-25 1988-09-01 Mars Inc Automatic test equipment
US4749947A (en) * 1986-03-10 1988-06-07 Cross-Check Systems, Inc. Grid-based, "cross-check" test structure for testing integrated circuits
US4857833A (en) * 1987-08-27 1989-08-15 Teradyne, Inc. Diagnosis of faults on circuit board
US4897836A (en) * 1987-10-20 1990-01-30 Gazelle Microcircuits, Inc. Programmable connection path circuit
US5065090A (en) * 1988-07-13 1991-11-12 Cross-Check Technology, Inc. Method for testing integrated circuits having a grid-based, "cross-check" te

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3621387A (en) * 1969-08-21 1971-11-16 Gen Instrument Corp Computer-controlled tester for integrated circuit devices
US4055801A (en) * 1970-08-18 1977-10-25 Pike Harold L Automatic electronic test equipment and method
US3673397A (en) * 1970-10-02 1972-06-27 Singer Co Circuit tester
US4114093A (en) * 1976-12-17 1978-09-12 Everett/Charles, Inc. Network testing method and apparatus
US4212075A (en) * 1978-10-10 1980-07-08 Usm Corporation Electrical component testing system for component insertion machine
US4271515A (en) * 1979-03-23 1981-06-02 John Fluke Mfg. Co., Inc. Universal analog and digital tester
US4300207A (en) * 1979-09-25 1981-11-10 Grumman Aerospace Corporation Multiple matrix switching system

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO8202096A1 *

Also Published As

Publication number Publication date
WO1982002096A1 (fr) 1982-06-24

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Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Designated state(s): AT CH DE FR GB LI LU NL SE

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 19830318

RIN1 Information on inventor provided before grant (corrected)

Inventor name: DENNY, BRADLEY J.

Inventor name: KREINICK, STEPHEN J.