EP0060751B1 - Apparatus for switching data transmission channels - Google Patents

Apparatus for switching data transmission channels Download PDF

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Publication number
EP0060751B1
EP0060751B1 EP19820400357 EP82400357A EP0060751B1 EP 0060751 B1 EP0060751 B1 EP 0060751B1 EP 19820400357 EP19820400357 EP 19820400357 EP 82400357 A EP82400357 A EP 82400357A EP 0060751 B1 EP0060751 B1 EP 0060751B1
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Prior art keywords
data
parallel
clock signal
channels
phase
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EP19820400357
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German (de)
French (fr)
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EP0060751A1 (en
Inventor
Christian Blanc
Rémy Gomez
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Thales SA
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Thomson CSF SA
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/02—Arrangements for detecting or preventing errors in the information received by diversity reception

Definitions

  • the present invention relates to data transmission and more particularly to a device for switching data transmission channels.
  • the invention applies to the case where data is to be transmitted, from a sending equipment to a receiving equipment, alternately by means of a first and a second data transmission channel, and in particular in the case where the one of the channels, called the normal channel, is intended to carry the data normally, the other channel, called the emergency channel, being intended to route the data when the normal channel fails.
  • the invention applies in particular to the transmission of data by radio-relay systems.
  • the radio-relay systems in fact comprise, between two localities to be served, several parallel data transmission channels (generally seven) on which the data to be transmitted are distributed, to which is added an additional backup channel usable for any of these seven ways when its quality becomes insufficient.
  • This switching device comprises means for gradually phasing, before the switching operation, the clock signal associated with the channel previously in service, called the old channel, and the clock signal associated with the newly activated channel. service, known as the new channel, and means for synchronizing, before the switching operation, the data transmitted on the old and the new channel.
  • These synchronization means include a buffer memory associated with each of the channels, a coincidence detector between the data stored in these two buffer memories, a circuit making it possible to decentralize before the switching operation and in the event of detection of no coincidence, the data stored in the buffer memory associated with the new channel, until detection of coincidence, and a circuit making it possible to refocus after the switching operation the data stored in the buffer memory associated with the new channel , so as to make possible a new decentering during a new switching operation in the same direction which could occur later.
  • the present invention relates to a switching device that does not require synchronization of the data, while making it possible to improve the insensitivity of the receiving equipment to the switching operation, and by presenting a simplified structure.
  • the subject of the invention is a device for switching data transmission channels, interposed between a receiving equipment and two data transmission channels each transmitting, according to different propagation conditions, the data transmitted by the same transmitting equipment. and the clock signal associated with this data, the device being of the type comprising first means for lengthening in a ratio n, the duration of the data transmitted on the two transmission channels and second switching means for transmitting to the equipment receiver of the data received from one or the other of the two channels, characterized in that it also comprises third means for supplying a clock signal intended for the receiving equipment in phase with the clock signal of the channel which is switched, fourth means coupled to the first means for synchronizing the data of the two channels whose durations are lengthened by the first means, fifth means coupled to the receiving equipment to shorten in the same ratio n the duration of the data supplied by the first means and transmit the data thus obtained to the receiving equipment in synchronism with the clock signals supplied by the third means, the second switching means being interposed between the first and fifth means for transmitting to the receiving equipment the data
  • the switching device 1 shown in FIG. 1 is interposed between on the one hand, a receiving equipment (not shown), to which it provides switched data D c on a transmission channel 2 called downstream channel, on the other hand a channel normal transmission 3 and a backup transmission channel 4.
  • a transmission channel 2 called downstream channel
  • a channel normal transmission 3 on the other hand
  • a backup transmission channel 4 On the normal and backup channels are transmitted respectively normal data D N and backup D s , which are the data transmitted by the same transmitting equipment (not shown), but having undergone different propagation conditions on these two channels.
  • the data transmission on the transmission channels 2, 3 and 4 is done according to the separate clock mode, that is to say that clock signals Hc, H N and Hs respectively associated with the data Dc, D N and Ds are transmitted simultaneously to this data on transmission channels 5, 6 and 7 respectively associated with transmission channels 2, 3 and 4.
  • the switching device 1 ensures, in a normal state, that is to say in the absence of failure of the normal channel 3, the connection of the channels 2 and 3 as well as the connection of the channels 5 and 6, and, in a standby state, that is to say in the presence of a failure of the normal channel 3, the connection of channels 2 and 4 as well as the connection of channels 5 and 7.
  • the switching device 1 comprises a switch 8 capable of ensuring a connection of the downstream channel 2 either to the normal channel 3 or to the emergency channel 4, according to the switching order received.
  • the switching device 1 comprises, upstream of the switch 8, means 9 for extending in a ratio n the duration of the data transmitted on the normal channel 3 and means 10 for reducing in the same ratio n the frequency of the clock signal associated with the data transmitted on the normal channel.
  • the switching device 1 comprises, upstream of the switch 8, means 11 for lengthening in the ratio n the duration of the data transmitted over the emergency route 4, and means 12 for reducing in the same ratio n the frequency of the clock signal associated with the data transmitted on the emergency route.
  • the switching device 1 also comprises, upstream of the switch 8, means 13 for phasing the fictitious clock signals h N and hs supplied respectively by the means 10 and 12.
  • the means 13 are intended to ensure either the setting of the phase of the fictitious clock signal put back in phase by the means 13, h'c, on the phase of the signal h s , that is to say the setting of the phase of the signal h'c on the phase of the signal h N , according to the position d 'a switch 13' interposed between on the one hand the means 10 and 12, on the other hand the means 13.
  • the switch 13 ' is controlled like the switch 8, with the difference that the control of the switch 8 is delayed relative to to the control of the switch 13 'by means of a timing circuit 8'.
  • the switching device 1 also comprises, upstream of the switch 8, means 14 to take account of the fictitious data d N supplied by the means 9, as well as means 15 to ensure that the fictitious data ds supplied by the means 11 are taken into account, by the fictitious clock signal reset to phase h ' c provided by means 13.
  • the switching device 1 comprises, downstream of the switch 8, means 16 for shortening in the same ratio n, the duration of the switched dummy data of c obtained at the output of the switch 8, and equal to either the dummy data of N supplied by means 14, or to the fictitious data of s supplied by means 15, according to the position of switch 8.
  • the means 16 supply the switched data to the downstream channel 2.
  • the switching device 1 also comprises, downstream of the switch 8, means 17 for increasing in the same ratio n the frequency of the fictitious switched clock signal h'c supplied by the means 13, the means 17 supply the real clock signal switched Hc to channel 5.
  • the switching device does not require any synchronization real data. Indeed, provided that the propagation condition differences between the normal and backup channels do not result in a loss of synchronism covering more than 2 binary elements, switching using switch 8 is done while the same Fictitious binary element is present on the channels to be switched.
  • the performance of the switching device according to the invention is further increased by the fact that the switching of the clock signals is done on the fictitious clock signals, that is to say those whose frequency is divided by n, and not on real clock signals. Indeed whatever the means used to ensure a progressive setting of the phase of a clock signal on the phase of another clock signal of the same frequency F, it is technically impossible to perform a phase jump greater than ⁇ . However, if these means operate, as the means 13 do, on clock signals whose frequency is divided by n, it is possible to gradually make up a difference of up to ⁇ between the fictitious clock signals of frequency F It then becomes possible to gradually make up for a difference of up to n ⁇ between the real clock signals, of frequency F.
  • the invention therefore makes it possible to solve in an extremely simple manner the problems posed by the switching of transmission channels.
  • FIG. 2 the various means shown in FIG. 1 are shown in detail.
  • the means for fictitiously lengthening in a ratio n the duration of the normal data D N consist of a series-parallel converter.
  • This parallel serial converter comprises a serial-parallel register 20, of n binary elements, the serial input of which is connected to channel 3 and the clock input of which is connected to channel 6.
  • This serial-parallel converter also includes a parallel-parallel register 21, of n binary elements, the parallel inputs of which are connected to the parallel outputs of the register 20.
  • the means 10 for fictitiously reducing in the ratio n the frequency of the clock signal H N associated with the normal data D N consist of a divider by n whose input is connected to channel 6 and whose output is connected to parallel-parallel register clock input 21.
  • the means 11 for fictitiously lengthening the duration of the service data D s in a ratio n also consist of a series-parallel converter.
  • This serial-parallel converter comprises a serial-parallel register 22, of n bits, whose serial input is connected to channel 4 and whose clock input is connected to channel 7.
  • This serial-parallel converter comprises also a parallel-parallel register 23 of n binary elements whose parallel inputs are connected to the outputs of register 22.
  • the means 12 for fictitiously reducing in a ratio n the frequency of the clock signal H s consist of a divider by n whose input is connected to channel 7 and whose output is connected to the clock input of the register parallel-parallel 23.
  • the means 13 for phasing the fictitious clock signals h n and h s consist of a phase locked loop.
  • This phase locked loop comprises in series a phase comparator 24, a first input of which constitutes the input of the phase locked loop, an amplifier 25, an oscillator 26 controlled in voltage and operating at the frequency of the clock signals.
  • the input of the loop phase locked is connected to the output of the switch 13 ', whose inputs are respectively connected to the outputs of the dividers 10 and 12. The control of the switch 13' will be described later.
  • the means 14 for ensuring that the fictitious data d N is taken into account by the fictitious clock re-phased h'c consist of a parallel-parallel register, of n binary elements, the parallel inputs of which are connected to the outputs of the register 21, and whose clock input is connected to the output of the divider 27.
  • the means 15 for ensuring that the fictitious data ds are taken into account by the fictitious clock reset to phase h'c consist of a parallel-parallel register, of n binary elements, the parallel inputs of which are connected to the outputs of the register 23 , and whose clock input is connected to the output of the divider 27.
  • the switch 8 shown very schematically in this figure, is in fact made up of n switches each provided with two inputs connected respectively to the output of the same rank of the registers 14 and 15. The control of these switches will be described later.
  • the means 16 for shortening, in the ratio n, the duration of the dummy data switched and re-phased dc consist of a parallel-series converter.
  • This parallel-to-serial converter comprises a parallel-parallel register 28, of n binary elements, the parallel inputs of which are connected to the outputs of the n switches forming the switch 8, and a parallel-series register 29 of which the parallel inputs are connected to the outputs of the register 28, and the serial output of which is connected to the downstream channel 2.
  • the clock input of register 29 is connected to the output of the voltage-controlled oscillator 26 which supplies it with a real clock signal reshaped in phase H ' c .
  • the clock input of register 28 is connected to the output of a divider by n, 30, the input of which is connected to the output of oscillator 26. In practice, the dividers 27 and 30 are combined.
  • the means 17 for increasing in the ratio n the frequency of the fictitious hortoge signal, represented in FIG. 1, and useful for the presentation of the principle of the invention are not found identically in FIG. 2, due limits imposed by technology.
  • the means 17 are found on the one hand in the fact that the voltage-controlled oscillator 26 operates at the frequency of the real clock signals (that is to say of frequency not divided by n) , and on the other hand in the introduction of a divider by n, 27, following the oscillator 26 in the phase locked loop. This makes it possible to obtain the real clock signal put back in phase, while avoiding the technological difficulties linked to the production of frequency multipliers. Indeed, it then suffices to introduce downstream of the switch 8 a frequency divider, which is much more easily achievable in practice than the introduction of a frequency multiplier.
  • the means 18 for synchronizing the fictitious data comprise a set 31 of n “exclusive OR” doors, represented very schematically in the drawing using a single “exclusive OR” door, and each provided with two inputs connected to the outputs of the same rank of registers 14 and 15. The outputs of these n “exclusive OR” doors are connected to the inputs of a first “OR” door 32.
  • the means 18 also include a counter 33 whose clock input is connected to the output of the “OR” gate 32, and a decoder 34 of the value m connects to the output of the counter 33, m being defined later.
  • the means 18 also comprise a second “OR” gate 35 provided with a first input connected to the output of the decoder 34 and with a second input which receives the switching order COM.
  • the means 18 also include a first monostable 36 whose input is connected to the output of the "OR” gate 35, and a second monostable 37 whose input receives the switching order COM.
  • the means 18 also include a third "OR” gate 38 provided with two inputs connected respectively to the output of the motorized vehicles 36 and 37, and of an output connected to the control input of the switch 13 'and of the timing circuit 8 ′ and providing a validation signal for switching VAL.
  • the timer circuit 8 ' consists for example of a monostable.
  • the means 18 also include a first “AND” gate 39 provided with a first input which receives the switching order COM, with a second input connected to the output of the decoder 34, and with an output providing a first signal DEP phase shift control ,.
  • the means 18 finally comprise a second “AND” gate 40 provided with a first input which receives the switching order COM via an inverter 41, with a second input connected to the output of the decoder 34, and with an output which provides a second phase shift control signal DEP 2 .
  • the first and second phase shift control signals respectively supply the phase shift control input of the dividers 10 and 12, a phase shift control of these dividers resulting in an elementary phase shift of 2n n on the fictitious clock signals supplied by these dividers.
  • the switching device shown in Figure 2 operates as follows.
  • the data D N received on channel 3 are first entered at the frequency F in the series-parallel register 20 (F denoting the frequency of the real clock signals H N and Hs). These data D N are subsequently entered in the parallel-parallel register 21 at the frequency F, developed by the divider 10 from n the frequency F. The same is true for the recording of the data D s , received on channel 4, in registers 22 and 23.
  • registers 20 and 22 do not simultaneously present the same content.
  • This prior synchronization necessary during each switching operation when a single backup channel is assigned to several normal channels, is however only useful at system initialization when the same backup channel is constantly assigned to the same normal way.
  • This prior synchronization of the fictitious data is ensured by the means 18, the operation of which will be described later.
  • the data registered in the register 28 are initially (before the switching order of the switch 8) the data of the old channel, and these data are taken into account by the fictitious clock signal reset in phase h 'c developed by the phase locked loop during this first time. And in a second step (after the switching order of switch 8) the data entered in register 28 are the data of the new channel, taken into account by the signal h'c produced by the phase locked loop during this second time.
  • the serial parallel passage of these data that is to say their transformation into real data, is ensured by the register 29.
  • the operation of the means 18 for synchronizing the fictitious data d N and d s stored in the registers 21 and 23 will now be described.
  • the synchronization process begins with a comparison of the data stored in the registers 14 and 15, using of the set 31 of doors "exclusive OR". If the content of register 14 is identical to the content of register 15, the output signal from the “AND” gate 32 takes a first logic level; otherwise, it takes a second logical level.
  • a counter 33 is used, the clock input of which is sensitive to the passages from the first to the second logic level of the signal applied to it, to count the number of times a difference between the contents of these two registers is detected during a certain duration T 1 counted either from the moment when the switching order becomes active, or from the moment when the counting result becomes equal to a certain number m.
  • This is obtained by the use of the monostable 36 of duration equal to the duration T l , triggered by the output signal from the “OR” gate 35 of which a first input receives the switching order COM and of which a second input is connected at the output of the decoder 34 of the value m of the counter 33.
  • the signal VAL is maintained at a logic level such that neither the switch 13 'nor the timing circuit 8' are activated.
  • phase shift command is applied to the phase shift control input of one of the counters 10 and 12.
  • Each command of phase shift of one of these counters has the effect of shifting the content of the register (21 or 23) associated with this counter by a binary element. Thanks to the presence of the “AND” gates 39 and 40 and of the inverter 41, the phase shift command is applied to the counter associated with the new channel, that is to say to the channel which will be put into service after switching . It is indeed assumed that the switching order takes a first logic level when a failure is observed on the normal channel and a second logic level when the stopping of this failure is observed on the normal channel.
  • the counter 33 determines whether the value m before the end of the duration T 1 or failing this, if at the end of a duration T 2 much greater than T, the counter 33 has always reached the value m before the end of each duration Tv the signal VAL assumes a logic level such that the switch 13 ′ and the timing circuit 8 ′ are activated. This is obtained by using the “OR” gate 38 and the monostable 37 of duration equal to the duration T 2 .

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Description

La présente invention concerne la transmission de données et plus particulièrement un dispositif de commutation de voies de transmission de données.The present invention relates to data transmission and more particularly to a device for switching data transmission channels.

L'invention s'applique au cas où des données sont à transmettre, d'un équipement émetteur vers un équipement récepteur, alternativement au moyen d'une première et d'une seconde voies de transmission de données, et notamment au cas où l'une des voies, dite voie normale, est destinée à acheminer normalement les données, l'autre voie, dite voie de secours, étant destinée à acheminer les données lorsque la voie normale est défaillante.The invention applies to the case where data is to be transmitted, from a sending equipment to a receiving equipment, alternately by means of a first and a second data transmission channel, and in particular in the case where the one of the channels, called the normal channel, is intended to carry the data normally, the other channel, called the emergency channel, being intended to route the data when the normal channel fails.

L'invention s'applique notamment à la transmission de données par faisceaux hertziens. Les faisceaux hertziens comportent en effet, entre deux localités à desservir, plusieurs voies de transmission de données en parallèle (généralement sept) sur lesquelles sont reparties les données à transmettre, auxquelles est ajoutée une voie supplémentaire de secours utilisable pour l'une quelconque de ces sept voies lorsque sa qualité devient insuffisante.The invention applies in particular to the transmission of data by radio-relay systems. The radio-relay systems in fact comprise, between two localities to be served, several parallel data transmission channels (generally seven) on which the data to be transmitted are distributed, to which is added an additional backup channel usable for any of these seven ways when its quality becomes insufficient.

Un problème technique se pose du fait que les deux voies de transmission ont des conditions de propagation différentes. Bien que les données transmises sur ces deux voies soient identiques, ceci se traduit par une perte de synchronisme des données et par un déphasage des signaux d'horloge associés aux données.A technical problem arises from the fact that the two transmission channels have different propagation conditions. Although the data transmitted on these two channels are identical, this results in a loss of synchronization of the data and in a phase shift of the clock signals associated with the data.

Ce problème se pose avec d'autant plus d'acuité que le débit binaire des voies de transmission de données est élevé. En effet plus le débit binaire est élevé, plus la différence de temps de propagation entre les voies se traduit par un nombre d'éléments binaires élevé, c'est-à-dire par une perte de synchronisme importante. En revanche, si le débit binaire est suffisamment faible, aucune perte de synchronisme ne se produit.This problem is all the more acute when the bit rate of the data transmission channels is high. In fact, the higher the bit rate, the more the difference in propagation time between the channels results in a high number of binary elements, that is to say by a significant loss of synchronism. On the other hand, if the bit rate is sufficiently low, no loss of synchronism occurs.

Or, pour ne pas altérer la transmission des données, il faut que ces phénomènes soient insensibles pour l'équipement récepteur lors de l'opération de commutation.However, in order not to alter the data transmission, these phenomena must be insensitive to the receiving equipment during the switching operation.

Pour ce faire, un dispositif de commutation a été proposé dans la demande de brevet N6 7 919 082 déposée le 24 juillet 1979 par la demanderesse (N° de publication 2462065). Ce dispositif de commutation comporte des moyens pour mettre progressivement en phase, avant l'opération de commutation, le signal d'horloge associé à la voie précédemment en service, dite ancienne voie, et le signal d'horloge associé à la voie nouvellement mise en service, dite nouvelle voie, et des moyens pour mettre en synchronisme, avant l'opération de commutation, les données transmises sur l'ancienne et la nouvelle voie.To do this, a switching device has been proposed in patent application N 6 7 919 082 filed on July 24, 1979 by the applicant (Publication No. 2462065). This switching device comprises means for gradually phasing, before the switching operation, the clock signal associated with the channel previously in service, called the old channel, and the clock signal associated with the newly activated channel. service, known as the new channel, and means for synchronizing, before the switching operation, the data transmitted on the old and the new channel.

Ces moyens de mise en synchronisme comportent une mémoire-tampon associée à chacune des voies, un détecteur de coïncidence entre les données stockées dans ces deux mémoires-tampon, un circuit permettant de décentrer avant l'opération de commutation et en cas de détection de non-coïncidence, les données stockées dans la mémoire-tampon associée à la nouvelle voie, et ce jusqu'à détection de coïncidence, et un circuit permettant de recentrer après l'opération de commutation les données stockées dans la mémoire tampon associée à la nouvelle voie, de manière à rendre possible un nouveau décentrage lors d'une nouvelle opération de commutation dans le même sens qui pourrait se présenter ultérieurement.These synchronization means include a buffer memory associated with each of the channels, a coincidence detector between the data stored in these two buffer memories, a circuit making it possible to decentralize before the switching operation and in the event of detection of no coincidence, the data stored in the buffer memory associated with the new channel, until detection of coincidence, and a circuit making it possible to refocus after the switching operation the data stored in the buffer memory associated with the new channel , so as to make possible a new decentering during a new switching operation in the same direction which could occur later.

La mise en synchronisme des données, solution vers laquelle on est naturellement conduit lorsqu'on examine le problème, requiert donc un matériel fort complexe et ne remplit pas parfaitement l'objectif que l'on s'est fixé, à savoir une insensibilité de l'équipement récepteur aux phénomènes accompagnent la commutation, ceci en raison des diverses manipulations que l'on fait subir aux données stockées dans la mémoire tampon associée à la nouvelle voie (la sortie de cette mémoire tampon étant directement reliée, après commutation, à l'équipement récepteur).Putting data in synchronism, a solution to which we are naturally led when we examine the problem, therefore requires very complex equipment and does not perfectly fulfill the objective that we have set, namely an insensitivity of the the equipment receiving the phenomena accompanies the switching, this due to the various manipulations that are made to the data stored in the buffer memory associated with the new channel (the output of this buffer memory being directly connected, after switching, to the receiving equipment).

Une autre approche de résolution de ce problème est décrite dans la demande de brevet français 2445669 qui concerne un dispositif de commutation de voies de transmission de données interposé entre un équipement récepteur et deux voies de transmissions de données transmettant chacune selon des conditions de propagation différentes. Des mémoires tampons au nombre de trois par voie sont prévues pour mémoriser les données reçues de chacune des voies. Des unités de réception disposées sur chacune des voies élaborent des signaux d'horloge de référence à partir des données transmises sur chacune des voies qui déterminent des cycles d'écriture des données reçues dans chacune des mémoires tampons. Les cycles d'écriture dans les mémoires tampon sont entrelacés et ont pour chaque mémoire tampon une durée égale à 3 fois la période du signal d'horloge de référence. Une boucle à verrouillage de phase est asservie sur l'écart de phase moyen existant entre les signaux d'horloge de référence fournis par les unités de réception pour délivrer des impulsions d'horloge de lecture à la fréquence de référence des mémoires tampons de chacune des voies. Les données lues dans les mémoires tampons de chacune des voies sont appliquées aux entrées d'un circuit de sélection de voie qui sélectionne les données de la voie de transmission la moins perturbée.Another approach to solving this problem is described in French patent application 2445669 which relates to a device for switching data transmission channels interposed between a receiving equipment and two data transmission channels each transmitting according to different propagation conditions. Buffers three in number per channel are provided to store the data received from each of the channels. Receiving units arranged on each of the channels generate reference clock signals from the data transmitted on each of the channels which determine the write cycles of the data received in each of the buffer memories. The write cycles in the buffer memories are interleaved and have for each buffer memory a duration equal to 3 times the period of the reference clock signal. A phase locked loop is slaved to the average phase difference existing between the reference clock signals supplied by the reception units to deliver read clock pulses at the reference frequency of the buffers of each of the tracks. The data read in the buffers of each of the channels is applied to the inputs of a channel selection circuit which selects the data of the least disturbed transmission channel.

Cette solution qui ne nécessite plus la mise en synchronisme des données reçues sur les deux voies de transmission n'est toutefois pas applicable aux faisceaux hertziens dans lesquels la transmission des données sur les voies de transmission est effectuée selon le mode à horloge séparée, c'est-à-dire où les signaux d'horloge et les données sont transmises sur des voies différentes car dans ce cas l'asservissement de la boucle à verrouillage sur la moyenne de phase des signaux d'horloge transmis sur les deux voies ne permet pas d'obtenir des signaux d'horloge rigoureusement en phase avec les signaux d'horloge de la voie commutée.This solution, which no longer requires synchronization of the data received on the two transmission channels, is however not applicable to radio-relay systems in which the transmission of data on the transmission channels is carried out according to the separate clock mode, ie that is to say where the clock signals and the data are transmitted on different channels because in this case the slaving of the locking loop on the phase average of the clock signals transmitted on the two channels does not allow to obtain clock signals rigorously in phase with the clock signals of the switched channel.

La présente invention a pour objet un dispositif de commutation ne nécessitant pas de mise en synchronisme des données, tout en permettant d'améliorer l'insensibilité de l'équipement récepteur à l'opération de commutation, et en présentant une structure simplifiée.The present invention relates to a switching device that does not require synchronization of the data, while making it possible to improve the insensitivity of the receiving equipment to the switching operation, and by presenting a simplified structure.

A cet effet, l'invention a pour objet un dispositif de commutation de voies de transmission de données, interposé entre un équipement récepteur et deux voies de transmission de données transmettant chacune selon des conditions de propagation différentes, les données émises par un même équipement émetteur et le signal d'horloge associé à ces données, le dispositif étant du type comprenant des premiers moyens pour allonger dans un rapport n, la durée des données transmises sur les deux voies de transmission et des deuxièmes moyens de commutation pour transmettre à l'équipement récepteur des données reçues de l'une ou l'autre des deux voies caractérisé en ce qu'il comprend également des troisièmes moyens pour fournir un signal d'horloge à destination de l'équipement récepteur en phase avec le signal d'horloge de la voie qui est commutée, des quatrièmes moyens couplés aux premiers moyens pour mettre en synchronisme les données des deux voies dont les durées sont allongées par les premiers moyens, des cinquièmes moyens couplés à l'équipement récepteur pour raccourcir dans le même rapport n la durée des données fournie par les premiers moyens et transmettre les données ainsi obtenues à destination de l'équipement récepteur en synchronisme avec les signaux d'horloge fournis par les troisièmes moyens, les deuxièmes moyens de commutation étant interposés entre les premiers et cinquièmes moyens pour transmettre vers l'équipement récepteur les données mises en synchronisme par les quatrièmes moyens au travers des cinquièmes moyens, la durée allongée des données fournies par les premiers moyens étant supérieure à deux fois la différence maximale de propagation entre les deux voies.To this end, the subject of the invention is a device for switching data transmission channels, interposed between a receiving equipment and two data transmission channels each transmitting, according to different propagation conditions, the data transmitted by the same transmitting equipment. and the clock signal associated with this data, the device being of the type comprising first means for lengthening in a ratio n, the duration of the data transmitted on the two transmission channels and second switching means for transmitting to the equipment receiver of the data received from one or the other of the two channels, characterized in that it also comprises third means for supplying a clock signal intended for the receiving equipment in phase with the clock signal of the channel which is switched, fourth means coupled to the first means for synchronizing the data of the two channels whose durations are lengthened by the first means, fifth means coupled to the receiving equipment to shorten in the same ratio n the duration of the data supplied by the first means and transmit the data thus obtained to the receiving equipment in synchronism with the clock signals supplied by the third means, the second switching means being interposed between the first and fifth means for transmitting to the receiving equipment the data synchronized by the fourth means through the fifth means, the extended duration of the data provided by the first means greater than twice the maximum propagation difference between the two channels.

Les objets et caractéristiques de la présente invention apparaîtront plus clairement à la lecture de la description suivante d'un exemple de réalisation, ladite description étant faite en relation avec les dessins ci-annexés dans lesquels:

  • - la figure 1 est un schéma synoptique d'un dispositif de commutation conforme à l'invention;
  • - la figure 2 est un schéma détaillé d'un dispositif de commutation conforme à l'invention.
The objects and characteristics of the present invention will appear more clearly on reading the following description of an exemplary embodiment, said description being made in relation to the attached drawings in which:
  • - Figure 1 is a block diagram of a switching device according to the invention;
  • - Figure 2 is a detailed diagram of a switching device according to the invention.

Le dispositif de commutation 1 représenté sur la figure 1 est interposé entre d'une part, un équipement récepteur (non représenté), auquel il fournit des données commutées Dc sur une voie de transmission 2 dite voie aval, d'autre part une voie de transmission normale 3 et une voie de transmission de secours 4. Sur les voies normales et de secours sont transmises respectivement des données normales DN et de secours Ds, qui sont les données émises par un même équipement émetteur (non représenté), mais ayant subi des conditions de propagation différentes sur ces deux voies.The switching device 1 shown in FIG. 1 is interposed between on the one hand, a receiving equipment (not shown), to which it provides switched data D c on a transmission channel 2 called downstream channel, on the other hand a channel normal transmission 3 and a backup transmission channel 4. On the normal and backup channels are transmitted respectively normal data D N and backup D s , which are the data transmitted by the same transmitting equipment (not shown), but having undergone different propagation conditions on these two channels.

La transmission des données sur les voies de transmission 2, 3 et 4 se fait selon le mode horloge séparée, c'est-à-dire que des signaux d'horloge Hc, HN et Hs respectivement associés aux données Dc, DN et Ds sont transmis simultanément à ces données sur des voies de transmission 5, 6 et 7 respectivement associées aux voies de transmission 2, 3 et 4.The data transmission on the transmission channels 2, 3 and 4 is done according to the separate clock mode, that is to say that clock signals Hc, H N and Hs respectively associated with the data Dc, D N and Ds are transmitted simultaneously to this data on transmission channels 5, 6 and 7 respectively associated with transmission channels 2, 3 and 4.

Le dispositif de commutation 1 assure, dans un état normal, c'est-à-dire en l'absence de défaillance de la voie normale 3, la connexion des voies 2 et 3 ainsi que la connexion des voies 5 et 6, et, dans un état de secours, c'est-à-dire en présence d'une défaillance de la voie normale 3, la connexion des voies 2 et 4 ainsi que la connexion des voies 5 et 7.The switching device 1 ensures, in a normal state, that is to say in the absence of failure of the normal channel 3, the connection of the channels 2 and 3 as well as the connection of the channels 5 and 6, and, in a standby state, that is to say in the presence of a failure of the normal channel 3, the connection of channels 2 and 4 as well as the connection of channels 5 and 7.

Le passage de l'état normal à l'état de secours, et réciproquement de l'état de secours à l'état normal lorsque la défaillance cesse, est commandé par un ordre de commutation COM fourni par un dispositif (non représenté) chargé de surveiller en permanence la qualité de la transmission sur la voie normale 3 et d'en tirer des conséquences sur la nécessité d'effectuer de telles commutations. Ce dispositif ne fait pas l'objet de l'invention et ne sera donc pas décrit de manière plus détaillée.The transition from the normal state to the emergency state, and vice versa from the emergency state to the normal state when the failure ceases, is controlled by a switching command COM supplied by a device (not shown) responsible for continuously monitor the quality of the transmission on the normal channel 3 and draw conclusions from this on the need to carry out such switching operations. This device is not the subject of the invention and will therefore not be described in more detail.

Le dispositif de commutation 1 comporte un commutateur 8 apte à assurer une connexion de la voie aval 2 soit à la voie normale 3 soit à la voie de secours 4, suivant l'ordre de commutation reçu.The switching device 1 comprises a switch 8 capable of ensuring a connection of the downstream channel 2 either to the normal channel 3 or to the emergency channel 4, according to the switching order received.

Le dispositif de commutation 1 comporte, en amont du commutateur 8, des moyens 9 pour allonger dans un rapport n la durée des données transmises sur la voie normale 3 et des moyens 10 pour réduire dans le même rapport n la fréquence du signal d'horloge associé aux données transmises sur la voie normale.The switching device 1 comprises, upstream of the switch 8, means 9 for extending in a ratio n the duration of the data transmitted on the normal channel 3 and means 10 for reducing in the same ratio n the frequency of the clock signal associated with the data transmitted on the normal channel.

De la même façon le dispositif de commutation 1 comporte en amont du commutateur 8 des moyens 11 pour allonger dans le rapport n la durée des données transmises sur la voie de secours 4, et des moyens 12 pour réduire dans le même rapport n la fréquence du signal d'horloge associé aux données transmises sur la voie de secours.In the same way, the switching device 1 comprises, upstream of the switch 8, means 11 for lengthening in the ratio n the duration of the data transmitted over the emergency route 4, and means 12 for reducing in the same ratio n the frequency of the clock signal associated with the data transmitted on the emergency route.

Le dispositif de commutation 1 comporte également en amont du commutateur 8 des moyens 13 de mise en phase des signaux d'horloge fictifs hN et hs fournis respectivement par les moyens 10 et 12. Les moyens 13 sont destinés à assurer soit le calage de la phase du signal d'horloge fictif remis en phase par les moyens 13, h'c, sur la phase du signal hs, soit le calage de la phase du signal h'c sur la phase du signal hN, suivant la position d'un commutateur 13' interposé entre d'une part les moyens 10 et 12, d'autre part les moyens 13. Le commutateur 13' est commandé comme le commutateur 8, à la différence près que la commande du commutateur 8 est retardée par rapport à la commande du commutateur 13' au moyen d'un circuit de temporisation 8'.The switching device 1 also comprises, upstream of the switch 8, means 13 for phasing the fictitious clock signals h N and hs supplied respectively by the means 10 and 12. The means 13 are intended to ensure either the setting of the phase of the fictitious clock signal put back in phase by the means 13, h'c, on the phase of the signal h s , that is to say the setting of the phase of the signal h'c on the phase of the signal h N , according to the position d 'a switch 13' interposed between on the one hand the means 10 and 12, on the other hand the means 13. The switch 13 'is controlled like the switch 8, with the difference that the control of the switch 8 is delayed relative to to the control of the switch 13 'by means of a timing circuit 8'.

Le dispositif de commutation 1 comporte également, en amont du commutateur 8, des moyens 14 pour assurer une prise en compte des données fictives dN fournies par les moyens 9, ainsi que des moyens 15 pour assurer une prise en compte des données fictives ds fournies par les moyens 11, par le signal d'horloge fictif remis en phase h'c fourni par les moyens 13.The switching device 1 also comprises, upstream of the switch 8, means 14 to take account of the fictitious data d N supplied by the means 9, as well as means 15 to ensure that the fictitious data ds supplied by the means 11 are taken into account, by the fictitious clock signal reset to phase h ' c provided by means 13.

Le dispositif de commutation 1 comporte, en aval du commutateur 8, des moyens 16 pour raccourcir dans le même rapport n, la durée des données fictives commutées d'c obtenues en sortie du commutateur 8, et égales soit aux données fictives d'N fournies par les moyens 14, soit aux données fictives d's fournies par les moyens 15, suivant la position du commutateur 8. Les moyens 16 fournissent les données commutées à la voie aval 2.The switching device 1 comprises, downstream of the switch 8, means 16 for shortening in the same ratio n, the duration of the switched dummy data of c obtained at the output of the switch 8, and equal to either the dummy data of N supplied by means 14, or to the fictitious data of s supplied by means 15, according to the position of switch 8. The means 16 supply the switched data to the downstream channel 2.

Le dispositif de commutation 1 comporte également en aval du commutateur 8 des moyens 17 pour accroître dans le même rapport n la fréquence du signal d'horloge fictif commuté h'c fourni par les moyens 13, les moyens 17 fournissent le signal d'horloge réel commuté Hc à la voie 5.The switching device 1 also comprises, downstream of the switch 8, means 17 for increasing in the same ratio n the frequency of the fictitious switched clock signal h'c supplied by the means 13, the means 17 supply the real clock signal switched Hc to channel 5.

Dans la pratique, pour des raisons d'économie de matériel liées à des observations statistiques des défaillances des voies de transmission, une seule voie de secours est généralement affectée à plusieurs voies normales transportant des données différentes. Dans ces conditions, on est conduit à rajouter au dispositif de commutation 1, en amont du commutateur 8, des moyens 18 de mise en synchronisme des données fictives d'N et d's. La commutation n'est alors effectuée au moyen du commutateur 8 que lorsque les données fictives d'N et d's ont été remises en synchronisme par les moyens 18. Les moyens 18 seraient inutiles si une voie de secours était affectée de manière fixe à chaque voie normale.In practice, for reasons of economy of material linked to statistical observations of the failures of the transmission channels, a single backup channel is generally assigned to several normal channels carrying different data. Under these conditions, we are led to add to the switching device 1, upstream of the switch 8, means 18 for synchronizing the fictitious data of N and d's. Switching is then carried out by means of switch 8 only when the fictitious data of N and d's have been brought into synchronism by the means 18. The means 18 would be useless if an emergency channel was fixedly assigned to each channel normal.

Du fait que la commutation des données se fait sur les données fictives, c'est-à-dire dont la durée est multipliée par n, et non sur les données réelles, le dispositif de commutation selon l'invention ne nécessite aucune mise en synchronisme des données réelles. En effet, à condition que les différences de condition de propagation entre les voies normales et de secours ne se traduisent pas par une perte de synchronisme recouvrant plus de 2 éléments binaires, la commutation à l'aide du commutateur 8 se fait alors que le même élément binaire fictif est présent sur les voies à commuter.Because the switching of the data is done on the dummy data, that is to say the duration of which is multiplied by n, and not on the real data, the switching device according to the invention does not require any synchronization real data. Indeed, provided that the propagation condition differences between the normal and backup channels do not result in a loss of synchronism covering more than 2 binary elements, switching using switch 8 is done while the same Fictitious binary element is present on the channels to be switched.

Les performances du dispositif de commutation conforme à l'invention sont encore accrues du fait que la commutation des signaux d'horloge se fait sur les signaux d'horloge fictifs, c'est-à-dire dont la fréquence est divisée par n, et non sur les signaux d'horloge réels. En effet quels que soient les moyens utilisés pour assurer un calage progressif de la phase d'un signal d'horloge sur la phase d'un autre signal d'horloge de même fréquence F, il est techniquement impossible d'effectuer un saut de phase supérieur à π. Or si ces moyens opèrent, comme le font les moyens 13, sur de signaux d'horloge dont la fréquence est divisée par n, il est possible de rattraper progressivement un écart allant jusqu'à π entre les signaux d'horloge fictifs de fréquence F. Il devient alors possi- n ble de rattraper progressivement un écart allant jusqu'à nπ entre les signaux d'horloge réels, de fréquence F. Grâce à l'invention, il devient donc possible de compenser l'écart exact existant entre les signaux d'horloge associés à l'ancienne et à la nouvelle voie, et non plus seulement de compenser cet écart modulo 2π, c'est-à-dire à l'intérieur d'un seul élément binaire. Ceci n'est possible évidemment qu'à la condition que le déphasage entre ces deux signaux d'horloge ne soit pas supérieur à nπ.The performance of the switching device according to the invention is further increased by the fact that the switching of the clock signals is done on the fictitious clock signals, that is to say those whose frequency is divided by n, and not on real clock signals. Indeed whatever the means used to ensure a progressive setting of the phase of a clock signal on the phase of another clock signal of the same frequency F, it is technically impossible to perform a phase jump greater than π. However, if these means operate, as the means 13 do, on clock signals whose frequency is divided by n, it is possible to gradually make up a difference of up to π between the fictitious clock signals of frequency F It then becomes possible to gradually make up for a difference of up to nπ between the real clock signals, of frequency F. Thanks to the invention, it therefore becomes possible to compensate for the exact difference existing between the signals. clock associated with the old and the new channel, and no longer only to compensate for this modulo 2π deviation, that is to say within a single binary element. This is obviously only possible on condition that the phase shift between these two clock signals is not greater than nπ.

L'invention permet donc de résoudre de manière extrêmement simple les problèmes posés par la commutation de voies de transmission.The invention therefore makes it possible to solve in an extremely simple manner the problems posed by the switching of transmission channels.

Sur la figure 2 on a représenté de manière détaillée les différents moyens représentés sur la figure 1.In FIG. 2, the various means shown in FIG. 1 are shown in detail.

Les moyens pour allonger fictivement dans un rapport n la durée des données normales DN consistent en un convertisseur série-parallèle. Ce convertisseur série parallèle comporte un registre série-parallèle 20, de n éléments binaires, dont l'entrée série est reliée à la voie 3 et dont l'entrée d'horloge est reliée à la voie 6. Ce convertisseur série-parallèle comporte également un registre parallèle-parallèle 21, de n éléments binaires, dont les entrées parallèle sont reliées aux sorties parallèle du registre 20.The means for fictitiously lengthening in a ratio n the duration of the normal data D N consist of a series-parallel converter. This parallel serial converter comprises a serial-parallel register 20, of n binary elements, the serial input of which is connected to channel 3 and the clock input of which is connected to channel 6. This serial-parallel converter also includes a parallel-parallel register 21, of n binary elements, the parallel inputs of which are connected to the parallel outputs of the register 20.

Les moyens 10 pour réduire fictivement dans le rapport n la fréquence du signal d'horloge HN associé aux données normales DN consistent en un diviseur par n dont l'entrée est reliée à la voie 6 et dont la sortie est reliée à l'entrée d'horloge du registre parallèle-parallèle 21.The means 10 for fictitiously reducing in the ratio n the frequency of the clock signal H N associated with the normal data D N consist of a divider by n whose input is connected to channel 6 and whose output is connected to parallel-parallel register clock input 21.

Les moyens 11 pour allonger fictivement dans un rapport n la durée des données de service Ds consistent également en un convertisseur série-parallèle. Ce convertisseur série-parallèle comporte un registre série-parallèle 22, de n éléments binaires, dont l'entrée série est reliée à la voie 4 et dont l'entrée d'horloge est reliée à la voie 7. Ce convertisseur série-parallèle comporte également un registre parallèle-parallèle 23 de n éléments binaires dont les entrées parallèle sont reliées aux sorties du registre 22.The means 11 for fictitiously lengthening the duration of the service data D s in a ratio n also consist of a series-parallel converter. This serial-parallel converter comprises a serial-parallel register 22, of n bits, whose serial input is connected to channel 4 and whose clock input is connected to channel 7. This serial-parallel converter comprises also a parallel-parallel register 23 of n binary elements whose parallel inputs are connected to the outputs of register 22.

Les moyens 12 pour réduire fictivement dans un rapport n la fréquence du signal d'horloge Hs consistent en un diviseur par n dont l'entrée est reliée à la voie 7 et dont la sortie est reliée à l'entrée d'horloge du registre parallèle-parallèle 23.The means 12 for fictitiously reducing in a ratio n the frequency of the clock signal H s consist of a divider by n whose input is connected to channel 7 and whose output is connected to the clock input of the register parallel-parallel 23.

Les moyens 13 de mise en phase des signaux d'horloge fictifs hn et hs consistent en une boucle à verrouillage de phase. Cette boucle à verrouillage de phase comporte en série un comparateur de phase 24 dont une première entrée constitue l'entrée de la boucle à verrouillage de phase, un amplificateur 25, un oscillateur 26 conmandé en tension et fonctionnant à la fréquence des signaux d'horloge réels HN et Hs, et un diviseur par n, 27, dont la sortie est reliée à une seconde entrée du comparateur de phase 24. L'entrée de la boucle à verrouillage de phase est reliée à la sortie du commutateur 13', dont les entrées sont respectivement reliées aux sorties des diviseurs 10 et 12. La commande du commutateur 13' sera décrite ultérieurement.The means 13 for phasing the fictitious clock signals h n and h s consist of a phase locked loop. This phase locked loop comprises in series a phase comparator 24, a first input of which constitutes the input of the phase locked loop, an amplifier 25, an oscillator 26 controlled in voltage and operating at the frequency of the clock signals. real H and N H s, and a divider by n, 27, whose output is connected to a second input of the phase comparator 24. the input of the loop phase locked is connected to the output of the switch 13 ', whose inputs are respectively connected to the outputs of the dividers 10 and 12. The control of the switch 13' will be described later.

Les moyens 14 pour assurer une prise en compte des données fictives dN par l'horloge fictive remise en phase h'c consistent en un registre parallèle-parallèle, de n éléments binaires, dont les entrées parallèle sont reliées aux sorties du registre 21, et dont l'entrée d'horloge est reliée à la sortie du diviseur 27.The means 14 for ensuring that the fictitious data d N is taken into account by the fictitious clock re-phased h'c consist of a parallel-parallel register, of n binary elements, the parallel inputs of which are connected to the outputs of the register 21, and whose clock input is connected to the output of the divider 27.

De même les moyens 15 pour assurer une prise en compte des données fictives ds par l'horloge fictive remise en phase h'c consistent en un registre parallèle-parallèle, de n éléments binaires, dont les entrées parallèle sont reliées aux sorties du registre 23, et dont l'entrée d'horloge est reliée à la sortie du diviseur 27.Likewise, the means 15 for ensuring that the fictitious data ds are taken into account by the fictitious clock reset to phase h'c consist of a parallel-parallel register, of n binary elements, the parallel inputs of which are connected to the outputs of the register 23 , and whose clock input is connected to the output of the divider 27.

Le commutateur 8, représenté très schématiquement sur cette figure, est en fait constitué de n commutateurs munis chacun de deux entrées reliées respectivement à la sortie de même rang des registres 14 et 15. La commande de ces commutateurs sera décrite ultérieurement.The switch 8, shown very schematically in this figure, is in fact made up of n switches each provided with two inputs connected respectively to the output of the same rank of the registers 14 and 15. The control of these switches will be described later.

Les moyens 16 pour raccourcir, dans le rapport n, la durée des données fictives commutées et remises en phase d'c consistent en un convertisseur parallèle-série. Ce convertisseur parallèle-série comporte un registre parallèle-parallèle 28, de n éléments binaires, dont les entrées parallèle sont reliées aux sorties des n commutateurs formant le commutateur 8, et un registre parallèle-série 29 dont les entrées parallèle sont reliées aux sorties du registre 28, et dont la sortie série est reliée à la voie aval 2. L'entrée d'horloge du registre 29 est reliée à la sortie de l'oscillateur commandé en tension 26 qui lui fournit un signal d'horloge réel remis en phase H'c. L'entrée d'horloge du registre 28 est reliée à la sortie d'un diviseur par n, 30, dont l'entrée est reliée à la sortie de l'oscillateur 26. Dans la pratique, les diviseurs 27 et 30 sont confondus.The means 16 for shortening, in the ratio n, the duration of the dummy data switched and re-phased dc consist of a parallel-series converter. This parallel-to-serial converter comprises a parallel-parallel register 28, of n binary elements, the parallel inputs of which are connected to the outputs of the n switches forming the switch 8, and a parallel-series register 29 of which the parallel inputs are connected to the outputs of the register 28, and the serial output of which is connected to the downstream channel 2. The clock input of register 29 is connected to the output of the voltage-controlled oscillator 26 which supplies it with a real clock signal reshaped in phase H ' c . The clock input of register 28 is connected to the output of a divider by n, 30, the input of which is connected to the output of oscillator 26. In practice, the dividers 27 and 30 are combined.

Les moyens 17 pour accroître dans le rapport n la fréquence du signal d'hortoge fictif, représentés sur la figure 1, et utiles pour la présentation du principe de l'invention ne se retrouvent pas à l'identique sur la figure 2, en raison des limites imposées par la technologie. Sur la figure 2, les moyens 17 se retrouvent d'une part dans le fait que l'oscillateur commandé en tension 26 fonctionne à la fréquence des signaux d'horloge réels (c'est-à-dire de fréquence non divisée par n), et d'autre part dans l'introduction d'un diviseur par n, 27, à la suite de l'oscillateur 26 dans la boucle à verrouillage de phase. Ceci permet d'obtenir le signal d'horloge réel remis en phase, tout en évitant les difficultés technologiques liées à la réalisation de multiplieurs de fréquence. En effet, il suffit alors d'introduire en aval du commutateur 8 un diviseur de fréquence, ce qui est beaucoup plus facilement réalisable en pratique que l'introduction d'un multiplieur de fréquence.The means 17 for increasing in the ratio n the frequency of the fictitious hortoge signal, represented in FIG. 1, and useful for the presentation of the principle of the invention are not found identically in FIG. 2, due limits imposed by technology. In FIG. 2, the means 17 are found on the one hand in the fact that the voltage-controlled oscillator 26 operates at the frequency of the real clock signals (that is to say of frequency not divided by n) , and on the other hand in the introduction of a divider by n, 27, following the oscillator 26 in the phase locked loop. This makes it possible to obtain the real clock signal put back in phase, while avoiding the technological difficulties linked to the production of frequency multipliers. Indeed, it then suffices to introduce downstream of the switch 8 a frequency divider, which is much more easily achievable in practice than the introduction of a frequency multiplier.

Les moyens 18 de mise en synchronisme des données fictives comportent un ensemble 31 de n portes «OU exclusif", représentées très schématiquement sur le dessin à l'aide d'une seule porte «OU exclusif", et munies chacune de deux entrées reliées aux sorties de même rang des registres 14 et 15. Les sorties de ces n portes «OU exclusif» sont reliées aux entrées d'une première porte «OU» 32.The means 18 for synchronizing the fictitious data comprise a set 31 of n "exclusive OR" doors, represented very schematically in the drawing using a single "exclusive OR" door, and each provided with two inputs connected to the outputs of the same rank of registers 14 and 15. The outputs of these n “exclusive OR” doors are connected to the inputs of a first “OR” door 32.

Les moyens 18 comportent également un compteur 33 dont l'entrée d'horloge est reliée à la sortie de la porte «OU» 32, et un décodeur 34 de la valeur m relie à la sortie du compteur 33, m étant défini ultérieurement.The means 18 also include a counter 33 whose clock input is connected to the output of the “OR” gate 32, and a decoder 34 of the value m connects to the output of the counter 33, m being defined later.

Les moyens 18 comportent également une deuxième porte «OU» 35 munie d'une première entrée reliée à la sortie du décodeur 34 et d'une seconde entrée qui reçoit l'ordre de commutation COM. Les moyens 18 comportent également un premier monostable 36 dont l'entrée est reliée à la sortie de la porte «OU» 35, et un second monostable 37 dont l'entrée reçoit l'ordre de commutation COM. Les moyens 18 comportent également une troisième porte «OU» 38 munie de deux entrées reliées respectivement à la sortie des mo- nostables 36 et 37, et d'une sortie reliée à l'entrée de commande du commutateur 13' et du circuit de temporisation 8'et fournissant un signal de validation de commutation VAL. Le circuit de temporisation 8' consiste par exemple en un monostable. Les moyens 18 comportent également une première porte «ET» 39 munie d'une première entrée qui reçoit l'ordre de commutation COM, d'une seconde entrée reliée à la sortie du décodeur 34, et d'une sortie fournissant un premier signal de commande de déphasage DEP,. Les moyens 18 comportent enfin une deuxième porte «ET» 40 munie d'une première entrée qui reçoit l'ordre de commutation COM via un inverseur 41, d'une seconde entrée reliée à la sortie du décodeur 34, et d'une sortie qui fournit un second signal de commande de déphasage DEP2.The means 18 also comprise a second “OR” gate 35 provided with a first input connected to the output of the decoder 34 and with a second input which receives the switching order COM. The means 18 also include a first monostable 36 whose input is connected to the output of the "OR" gate 35, and a second monostable 37 whose input receives the switching order COM. The means 18 also include a third "OR" gate 38 provided with two inputs connected respectively to the output of the motorized vehicles 36 and 37, and of an output connected to the control input of the switch 13 'and of the timing circuit 8 ′ and providing a validation signal for switching VAL. The timer circuit 8 'consists for example of a monostable. The means 18 also include a first “AND” gate 39 provided with a first input which receives the switching order COM, with a second input connected to the output of the decoder 34, and with an output providing a first signal DEP phase shift control ,. The means 18 finally comprise a second “AND” gate 40 provided with a first input which receives the switching order COM via an inverter 41, with a second input connected to the output of the decoder 34, and with an output which provides a second phase shift control signal DEP 2 .

Le premier et le second signal de commande de déphasage alimentent respectivement l'entrée de commande de déphasage des diviseurs 10 et 12, une commande de déphasage de ces diviseurs se traduisant par un déphasage élémentaire de 2n n sur les signaux d'horloge fictifs fournis par ces diviseurs.The first and second phase shift control signals respectively supply the phase shift control input of the dividers 10 and 12, a phase shift control of these dividers resulting in an elementary phase shift of 2n n on the fictitious clock signals supplied by these dividers.

Le dispositif de commutation représenté sur la figure 2 fonctionne de la façon suivante.The switching device shown in Figure 2 operates as follows.

Les données DN reçues sur la voie 3 sont dans un premier temps inscrites à la fréquence F dans le registre série-parallèle 20 (F désignant la fréquence des signaux d'horloge réels HN et Hs). Ces données DN sont dans un second temps inscrites dans le registre parallèle-parallèle 21 à la fréquence F, élaborée par le diviseur 10 à partir de n la fréquence F. Il en est de même pour l'inscription des données Ds, reçues sur la voie 4, dans les registres 22 et 23.The data D N received on channel 3 are first entered at the frequency F in the series-parallel register 20 (F denoting the frequency of the real clock signals H N and Hs). These data D N are subsequently entered in the parallel-parallel register 21 at the frequency F, developed by the divider 10 from n the frequency F. The same is true for the recording of the data D s , received on channel 4, in registers 22 and 23.

En raison des différences de condition de propagation existant entre les deux chemins empruntés par les données émises par le même équipement émetteur, les registres 20 et 22 ne présentent pas simultanément le même contenu.Due to the differences in propagation conditions between the two paths taken by the data sent by the same team As the transmitter, registers 20 and 22 do not simultaneously present the same content.

En revanche, les registres 21 et 23, dont le contenu ne change qu'à la fréquence F, présen- n tent simultanément le même contenu, à condition toutefois que les données fictives DN et Ds aient subi une mise en synchronisme préalable. Cette mise en synchronisme préalable, nécessaire lors de chaque opération de commutation lorsqu'une seule voie de secours est affectée à plusieurs voies normales, n'est toutefois utile qu'à l'initialisation du système lorsque la même voie de secours est constamment affectée à la même voie normale. Cette mise en synchronisme préalable des données fictives est assurée par les moyens 18 dont le fonctionnement sera décrit ultérieurement.On the other hand, the registers 21 and 23, the content of which changes only at the frequency F, present the same content simultaneously, provided however that the fictitious data D N and D s have undergone prior synchronization. This prior synchronization, necessary during each switching operation when a single backup channel is assigned to several normal channels, is however only useful at system initialization when the same backup channel is constantly assigned to the same normal way. This prior synchronization of the fictitious data is ensured by the means 18, the operation of which will be described later.

Les commutateurs 8 et 13' sont commandés soit par l'ordre de commutation COM à travers les moyens 18, soit directement par l'ordre de commutation COM, suivant que la mise en synchronisme préalable des données fictives s'avère ou non nécessaire.The switches 8 and 13 'are controlled either by the switching order COM through the means 18, or directly by the switching order COM, depending on whether the prior synchronization of the fictitious data proves or is not necessary.

On se place maintenant dans le cas où les données fictives sont rendues synchrones, c'est-à-dire dans le cas où le contenu des registres 21 et 23 est identique. Lorsqu'intervient alors la commande du commutateur 13', le signal hc d'entrée de la boucle à verrouillage de phase passe brusquement de la phase du signal d'horloge fictif avant commutation à la phase du signal d'horloge fictif après commutation. En revanche, ce passage se fait de manière très progressive sur le signal d'horloge fictif h'c obtenu en sortie de la boucle à verrouillage de phase. Or les données fictives dN et ds sont inscrites dans les registres 14 et 15 sur les fronts actifs du signal h'c de sortie de la boucle à verrouillage de phase. Par conséquent la prise en compte de ces données dans les registres 14 et 15 varie progressivement dans le temps, ce qui correspond pour la nouvelle voie à une prise en compte des données par un signal d'horloge qui se rapproche progressivement du signal d'horloge associé à la nouvelle voie, et pour l'ancienne voie à une prise en compte des données par un signal d'horloge qui s'éloigne progressivement du signal d'horloge associé à l'ancienne voie. Pour que la commutation des données se fasse dans les meilleures conditions, du point de vue de l'équipement récepteur, on observe qu'il convient de commander le commutateur 8 approximativement au milieu de la durée d'intrégration de la boucle à verrouillage de phase. Le circuit de temporisation 8' est donc choisi en fonction de ces considérations.We now place ourselves in the case where the fictitious data are made synchronous, that is to say in the case where the content of the registers 21 and 23 is identical. When the switch 13 'is then commanded, the input signal h c of the phase-locked loop suddenly changes from the phase of the dummy clock signal before switching to the phase of the dummy clock signal after switching. On the other hand, this passage takes place very gradually on the fictitious clock signal h ′ c obtained at the output of the phase locked loop. However, the fictitious data d N and d s are written into registers 14 and 15 on the active edges of the signal h'c output from the phase-locked loop. Consequently, the taking into account of this data in registers 14 and 15 varies gradually over time, which corresponds for the new channel to taking into account of the data by a clock signal which progressively approaches the clock signal. associated with the new channel, and for the old channel to take into account the data by a clock signal which progressively moves away from the clock signal associated with the old channel. For the data switching to take place in the best conditions, from the point of view of the receiving equipment, it is observed that the switch 8 should be controlled approximately at the middle of the integration time of the phase locked loop . The timing circuit 8 'is therefore chosen according to these considerations.

Ainsi les données inscrites dans le registre 28 sont dans un premier temps (avant l'ordre de commutation du commutateur 8) les données de l'ancienne voie, et ces données sont prises en compte par le signal d'horloge fictif remis en phase h'c élaboré par la boucle à verrouillage de phase pendant ce premier temps. Et dans un deuxième temps (après l'ordre de commutation du commutateur 8) les données inscrites dans le registre 28 sont les données de la nouvelle voie, prises en compte par le signal h'c élaboré par la boucle à verrouillage de phase pendant ce deuxième temps. Le passage parallèle série de ces données, c'est-à-dire leur transformation en données réelles, est assuré par le registre 29.Thus the data registered in the register 28 are initially (before the switching order of the switch 8) the data of the old channel, and these data are taken into account by the fictitious clock signal reset in phase h 'c developed by the phase locked loop during this first time. And in a second step (after the switching order of switch 8) the data entered in register 28 are the data of the new channel, taken into account by the signal h'c produced by the phase locked loop during this second time. The serial parallel passage of these data, that is to say their transformation into real data, is ensured by the register 29.

On décrit maintenant le fonctionnement des moyens 18 de mise en synchronisme des données fictives dN et ds stockées dans les registres 21 et 23. Le processus de mise en synchronisme débute par une comparaison des données stockées dans les registres 14 et 15, au moyen de l'ensemble 31 de portes «OU exclusif». Si le contenu du registre 14 est identique au contenu du registre 15, le signal de sortie de la porte «ET» 32 prend un premier niveau logique; sinon, il prend un second niveau logique.The operation of the means 18 for synchronizing the fictitious data d N and d s stored in the registers 21 and 23 will now be described. The synchronization process begins with a comparison of the data stored in the registers 14 and 15, using of the set 31 of doors "exclusive OR". If the content of register 14 is identical to the content of register 15, the output signal from the “AND” gate 32 takes a first logic level; otherwise, it takes a second logical level.

On utilise un compteur 33 dont l'entrée d'horloge est sensible aux passages du premier au second niveau logique du signal qui lui est appliqué, pour compter le nombre de fois où l'on détecte une différence entre les contenus de ces deux registres pendant une certaine durée T1 comptée soit à partir du moment où l'ordre de commutation devient actif, soit à partir du moment où le résultat du comptage devient égal à un certain nombre m. Ceci est obtenu par l'utilisation du monostable 36 de durée égale à la durée Tl, déclenché par le signal de sortie de la porte «OU» 35 dont une première entrée reçoit l'ordre de commutation COM et dont une deuxième entrée est reliée à la sortie du décodeur 34 de la valeur m du compteur 33.A counter 33 is used, the clock input of which is sensitive to the passages from the first to the second logic level of the signal applied to it, to count the number of times a difference between the contents of these two registers is detected during a certain duration T 1 counted either from the moment when the switching order becomes active, or from the moment when the counting result becomes equal to a certain number m. This is obtained by the use of the monostable 36 of duration equal to the duration T l , triggered by the output signal from the “OR” gate 35 of which a first input receives the switching order COM and of which a second input is connected at the output of the decoder 34 of the value m of the counter 33.

Si le compteur 33 atteint la valeur m avant la fin de la durée T1, le signal VAL est maintenu à un niveau logique tel que ni le commutateur 13' ni le circuit de temporisation 8' ne sont activés.If the counter 33 reaches the value m before the end of the duration T 1 , the signal VAL is maintained at a logic level such that neither the switch 13 'nor the timing circuit 8' are activated.

De plus, à chaque fois que le compteur 33 atteint la valeur m avant la fin de la durée Ti, une commande de déphasage est appliquée à l'entrée de commande de déphasage de l'un des compteurs 10 et 12. Chaque commande de déphasage de l'un de ces compteurs a pour effet de décaler d'un élément binaire le contenu du registre (21 ou 23) associé à ce compteur. Grâce à la présence des portes «ET» 39 et 40 et de l'inverseur 41, la commande de déphasage est appliquée au compteur associé à la nouvelle voie, c'est-à-dire à la voie qui sera mise en service après commutation. On suppose en effet que l'ordre de commutation prend un premier niveau logique lorsqu'une défaillance est observée sur la voie normale et un second niveau logique lorsque l'arrêt de cette défaillance est observé sur la voie normale.In addition, each time the counter 33 reaches the value m before the end of the duration T i , a phase shift command is applied to the phase shift control input of one of the counters 10 and 12. Each command of phase shift of one of these counters has the effect of shifting the content of the register (21 or 23) associated with this counter by a binary element. Thanks to the presence of the “AND” gates 39 and 40 and of the inverter 41, the phase shift command is applied to the counter associated with the new channel, that is to say to the channel which will be put into service after switching . It is indeed assumed that the switching order takes a first logic level when a failure is observed on the normal channel and a second logic level when the stopping of this failure is observed on the normal channel.

En revanche, si le compteur 33 n'atteint pas la valeur m avant la fin de la durée T1 ou à défaut, si à la fin d'une durée T2 très supérieure à T, le compteur 33 a toujours atteint la valeur m avant la fin de chaque durée Tv le signal VAL prend un niveau logique tel que le commutateur 13' et le circuit de temporisation 8' sont activés. Ceci est obtenu par l'utilisation de la porte «OU» 38 et du monostable 37 de durée égale à la durée T2.On the other hand, if the counter 33 does not reach the value m before the end of the duration T 1 or failing this, if at the end of a duration T 2 much greater than T, the counter 33 has always reached the value m before the end of each duration Tv the signal VAL assumes a logic level such that the switch 13 ′ and the timing circuit 8 ′ are activated. This is obtained by using the “OR” gate 38 and the monostable 37 of duration equal to the duration T 2 .

Le choix de ce processus de mise en synchronisme, faisant appel à plusieurs tests successifs de coïncidence entre les contenus des registres 14 et 15 pendant une durée égale à T1 est destiné à s'affranchir des phénomènes suivants: données pauvres en informations (séquences 111111--, 000000--) et données ayant une périodicité inférieure à n (séquences 101010---11001100----). Dans ces cas en effet le contenu des registres ne peut à lui seul lever le doute. Le seul moyen de s'en affranchir est alors de tirer parti de la présence dans les données transmises de mots de synchronisation qui se répètent avec une périodicité égale à T1 ou sous multiple de T1.The choice of this synchronization process, using several successive tests coincidence between the contents of registers 14 and 15 for a period equal to T 1 is intended to overcome the following phenomena: data poor in information (sequences 111111--, 000000--) and data having a periodicity less than n ( sequences 101010 --- 11001100 ----). In these cases the content of the registers cannot in itself remove the doubt. The only way to get rid of it is then to take advantage of the presence in the transmitted data of synchronization words which are repeated with a periodicity equal to T1 or under multiple of T 1 .

Comme par ailleurs on souhaite que la mise en synchronisme des données fictives se déroule le plus rapidement possible, le choix entre les valeurs m, T1 et T2 est finalement l'affaire d'un compromis entre rapidité et qualité de la mise en synchronisme souhaitées.As we also want the synchronization of the fictitious data to take place as quickly as possible, the choice between the values m, T 1 and T 2 is ultimately a matter of a compromise between speed and quality of the synchronization desired.

Claims (9)

1. A device for switching data transmission channels, said device being interposed between a receiver unit and two data transmission channels (3 and 4), each channel transmitting under different conditions of propagation the data delivered by a common transmitter unit as well as the clock signal associated with said data, the device comprising first means (9 and 11) for increasing by a factor n the duration of the data transmitted over the two transmission channels, and second switching means (8) for transmitting the data received from one or the other of the two channels to the receiver unit, characterized in that it further comprises third means (13, 17) for delivering a clock signal to the receiver unit, this signal being in phase with the clock signal of the switched channel, fourth means (18) coupled to the first means (9, 11), conceived to synchronize the data of the two channels, the durations of which are increased by the first means, and fifth means (16) coupled to the receiver unit and intended to shorten by the same factor n the duration of the data furnished by the first means and to transmit these data thus obtained to the receiver unit synchroneously with the clock signals delivered by the third means (13, 17), the second switching means (8) being interposed between the first means (9, 11) and the fifth means (16) in order to transmit the data which have been synchronized by the fourth means (18) through the fifth means to the receiver unit, the increased duration of the data furnished by the first means (9, 11) being larger than two times the maximum difference of propagation between the two channels.
2. A device according to claim 1, characterized in that the first means (9) for increasing the duration of the data transmitted on the first transmission channel by a factor n consist of a first series-parallel converter (20 and 21), a series input of which is connected to the first transmission channel and n parallel outputs of which are connected to the first inputs of n switches (8).
3. A device according to claims 1 and 2, characterized in that the first means (11) for increasing the duration of the data transmitted on the second transmission channel by a factor n consist of a second series-parallel converter (22 and 23), a series input of which is connected to the second transmission channel and n parallel outputs of which are connected to the second inputs of the n switches (8).
4. A device according to claims 1, 2 and 3, characterized in that the fifth means (16) for shortening the duration of the data transmitted to the receiver unit consist of a parallel-series converter (28 and 29), the n parallel inputs of which are connected to the outputs of the n switches and the series output of which is connected to the receiver unit.
5. A device according to claims 1 to 4, characterized in that the third means (13, 17) intended to deliver a clock signal to the receiver unit which is in phase with the clock signal of the switched channels are constituted by a phase-locked loop (24, 25, 26, 27), the input of which is connected to the output of a clock signal switch (13'), the inputs of the clock signal switch (13') being connected to a pulse divider (10, 12), which divides by n the clock signal pulses of each one of the channels.
6. A device according to any one of claims 1 to 5, characterized in that it comprises a delay circuit (8') for delaying the switching of the data by the second switch means (8) for a time delay which is necessary to get in phase the clock signal delivered by the phase-locked loop with the clock signal of the switched channels.
7. A device according to any one of claims 1 to 6, characterized in that it comprises seventh means (14, 15) intended to take into account the data with increased duration due to the first means (9, 11) in synchronism with the clock signal generated by the phase-locked loop (13).
8. A device according to claim 7, characterized in that the seventh means (14 and 15) for taking into account the fictitious data which have been increased in duration by the first means (9, 11) in synchronism with the clock signal furnished by the phase-locked loop (3) consist of two parallel-parallel registers (14 and 15) of n binary elements, these registers being interposed between the two series-parallel converters (9 and 11) and the n switches (8) and being provided with clock inputs connected to the output of the means (13) for getting the clock signals in phase.
9. A device according to claim 8, characterized in that the fourth means (18) for getting the fictitious data in synchronism comprise a control circuit for shifting the data stored in the series-parallel converter associated to the old channel in the event of detection of non-coincidence between the contents of the two parallel-parallel registers (14 and 15), and a circuit for controlling the delay circuit (8) and the switch (13'), capable of activating the delay circuit (8') and the switch (13') in the event of detection of coincidence between the contents of the two parallel-parallel registers (14 and 15).
EP19820400357 1981-03-13 1982-03-02 Apparatus for switching data transmission channels Expired EP0060751B1 (en)

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FR8105127A FR2501937B1 (en) 1981-03-13 1981-03-13 DEVICE FOR SWITCHING DATA TRANSMISSION CHANNELS
FR8105127 1981-03-13

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EP0060751B1 true EP0060751B1 (en) 1985-10-16

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USRE33404E (en) * 1983-04-18 1990-10-23 Megabit Communications, Inc. Enhanced distance data transmission system
FR2553244B1 (en) * 1983-10-07 1988-12-30 Trt Telecom Radio Electr SWITCHING DEVICE WITH AUTOMATIC DATA PHASE ON 3.5 BITS
JPS60102036A (en) * 1983-11-09 1985-06-06 Nec Corp Synchronizing switching system
JPS6370632A (en) * 1986-09-11 1988-03-30 Nec Corp Line switching system
KR100226528B1 (en) * 1995-03-29 1999-10-15 가나이 쓰도무 Decoder for compressed and multiplexed video and audio data
US7628810B2 (en) 2003-05-28 2009-12-08 Acufocus, Inc. Mask configured to maintain nutrient transport without producing visible diffraction patterns
US20050046794A1 (en) 2003-06-17 2005-03-03 Silvestrini Thomas A. Method and apparatus for aligning a mask with the visual axis of an eye
CN102448404B (en) 2009-08-13 2015-06-10 阿库福库斯公司 Masked intraocular implants and lenses

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JPS5858859B2 (en) * 1976-01-30 1983-12-27 日本電気株式会社 Line identification method
DE2851168B1 (en) * 1978-11-27 1980-04-17 Siemens Ag Device replacement circuit
JPS5588452A (en) * 1978-12-26 1980-07-04 Nec Corp Digital signal switching circuit for diversity receiver for digital radio communication
JPS5840383B2 (en) * 1979-05-21 1983-09-05 富士通株式会社 Line control method for data transmission equipment
FR2462065A1 (en) * 1979-07-24 1981-02-06 Thomson Csf Switching of numeric signal equipment - using memory and coincidence detector techniques with two circuits transmitting same data under different conditions

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JPS57162551A (en) 1982-10-06
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DE3266890D1 (en) 1985-11-21
FR2501937B1 (en) 1985-06-07
FR2501937A1 (en) 1982-09-17

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