EP0052604A1

EP0052604A1 - Semiconductor memory precharge circuit

Info

Publication number: EP0052604A1
Application number: EP19810900318
Authority: EP
Inventors: Robert J. Proebsting
Original assignee: Mostek Corp
Current assignee: CTU of Delaware Inc
Priority date: 1980-06-02
Filing date: 1980-06-02
Publication date: 1982-06-02
Also published as: WO1981003572A1

Abstract

Un circuit de memoire a semi-conducteur possede des demi-lignes numeriques (116, 118) qui sont connectees a un amplificateur de detection (120). Une cellule de memoire (122) produit un decalage de tension sur une demi-ligne numerique (116). L'amplificateur de detection (120) tire la demi-ligne numerique (116, 118) ayant la tension la plus faible a la terre. Des circuits de remontee (126, 128) font remonter la demi-ligne numerique (116, 118) ayant la tension la plus elevee jusqu'a atteindre la tension d'alimentation. Apres l'operation de remontee, un signal de precharge (84) active une paire de transistors de precharge (132, 134) qui couplent les demi-lignes numeriques (116, 118) sur un noeud de bascule commun (110). Les tensions sur les demi-lignes numeriques (116, 118) s'equilibrent par le passage de courant par le noeud de bascule (110).A semiconductor memory circuit has digital semi-lines (116, 118) which are connected to a sense amplifier (120). A memory cell (122) produces a voltage offset on a digital half-line (116). The detection amplifier (120) draws the digital half-line (116, 118) having the lowest voltage to earth. Ascent circuits (126, 128) raise the digital half-line (116, 118) having the highest voltage until reaching the supply voltage. After the ascent operation, a preload signal (84) activates a pair of preload transistors (132, 134) which couple the digital half-lines (116, 118) to a common latch node (110). The voltages on the digital half-lines (116, 118) are balanced by the current flow through the rocker node (110).

Description

SEMICONDUCTOR MEMORY PRECHARGE CIRCUIT

TECHNICAL FIELD

The present invention pertains to. semiconductor integrated memory circuits and in particular to a circuit for equilibrating the voltages on complementary half digit lines before the reading of a memory cell connected to one of the half digit lines.

BACKGROUND ART

The course of development for MOSFET (metal oxide semiconductor field effect transistor) memories is toward a greater number of memory cells per circuit chip as well as greater access speed for reading the memory. As the size of semiconductor memories increases from IK, 4K and 16K upward to 64K and 256K the greater number of memory cells in each memory circuit creates greater capacitance along commonly connected nodes. This greater capacitance results in slower operation speed for certain operating steps carried out during each memory cycle. Resistive and capacitive speed limitations which were negligible in the smaller memories can become significant limitations in the speed of operation for the larger size semiconductor memories.

In the type of semiconductor memories which have split digit lines with a center sense amplifier, the process of reading a memory cell results in driving the halves of the digit line to opposite voltage states. During each memory cycle the halves of the digit line . must be equilibrated before another memory cell connected on the digit line can be read. The equilibration 'process comprises precharging the two half digit lines to have essentially the same voltage since the connection of a memory cell to a half digit line results in only a smal voltage change on the line. The state of a memory cell is sensed by comparing the small voltage shift on one hal digit line to the voltage on the complementary half digit line. Precharge circuits heretofore have utilized a massive connecting bus which joins together all the digit lines for a short time period during each memory cycle to equilibrate voltages on the digit lines. Although suc an equilibration operation works well with small memories in larger memories the time constant for the charging operation becomes excessively long and thereby slows down the operation of the memory. Therefore, there exists a need for a precharge circuit which equilibrates the digit half lines in a semiconductor memory during each memory cycle and such equilibration is carried out in a short time period and also accurately balances the voltages on each of the pairs of digit half lines.

DISCLOSURE OF THE INVENTION

In a semiconductor integrated circuit memory a precharge circuit for equilibrating half digit lines where a sense amplifier discharges one of the half digit lines in response to a latch signal supplied through a latch node after a memory cell has been coupled to one of the half digit lines, the precharge circuit comprising a first transistor having drain, source and gate terminals, a selected one of the drain and source terminals thereof connected to a first half digit line, the remaining one of the drain and source terminals thereof connected to said latch node and the gate termina thereof connected to receive a precharge signal which activates the first transistor to provide a conductive path between the drain and source terminals thereof.

A second transistor is provided also having drain, source and gate terminals, a selected one of the drain and sourc terminals thereof connected to a second half digit line, which is the complement of the first half digit line, the remaining one of the drain and source terminals thereof connected to the latch node and the gate terminal thereof connected to receive the precharge signal which activates the second transistor to provide a conductive path betwee the drain and source terminals thereof*. Upon occurrence of the precharge signal the first and second half digit lines are interconnected through the latch node thereby equilibrating the voltages on said first and second half digit lines. The circuit of the present invention is preferably used in a semiconductor memory which is fabricated to have row lines on opposed sides of a sense amplifier and a common latch node is used with all of the sense amplifiers. BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following description taken in conjunction with the accompanying Drawings in which:

FIGURE 1 is a schematic illustration of a semiconductor memory circuit having the precharge circuit heretofore used;

FIGURE 2 is an illustration of timing signals utilized in the semiconductor memory circuits described herein; and

FIGURE 3 is a schematic illustration of a semi¬ conductor memory circuit including the precharge circuit of the present invention.

DETAILED DESCRIPTION

A semiconductor memory utilizing a conventional precharge circuit is illustrated in FIGURE 1. A bit pattern is stored in the semiconductor memory in a plurality of memory cells two of which are shown as cells 10 and 12. Cell 10 comprises an access transistor 10a and a storage capacitor 10b. The drain terminal of transistor 10a is connected to a half digit line 14 and the source terminal of transistor 10a is connected to a first terminal of capacitor 10b which has the second terminal thereof connected to ground. The gate terminal of transistor 10a is joined to a word line 16. Memory cell 12 likewise includes a transistor 12a and a capacitor 12b. The drain terminal of transistor 12a is connected to a half digit line 18 and the source terminal of transistor 12a is connected to a first terminal of capacitor 12b which has the second terminal thereof connected to ground. The gate terminal of transistor 12a is connected to a word line 20. The half digit lines are connected as inputs to a sense amplifier 22 which has a latch node 24. A latch signal is provided to node 24 for activating sense amplifier 22. The latch signal is illustrated in FIGURE 2. A pull up circuit 26 is connected to the half digit line 14 and to a +5 volt supply. The input terminal of circuit 26 is connected to receive a pull up signal which is illustrated in FIGURE 2. A corresponding pull up circuit 28 is connected to half digit line 18 and also receives the pull up signal at the input terminal thereof A precharge transistor 30 is connected so that its drain and source terminals couple the half digit line 14 to a bus line 32. The gate terminal of transistor 30 is connected to receive a precharge signal which is shown in FIGURE 2. A similar precharge transistor 34 connects the half digit line 18 to the bus line 32. The circuit illustrated in FIGURE 1 is only a small part of a complete semiconductor memory but includes examples of each of the significant circuit elements necessary to describe the present invention. Within a full memory circuit there are a plurality of the word lines 16 and 20 with each v/ord line controlling a memory cell that is connected to one of the half digit lines 14 and 18. Likewise there are a plurality of pairs of half digit lines such as 14 and 18 extending to form a two dimensional array of memory cells having sense amplifiers connected between each pair of half digit lines.

A further digit line is illustrated in FIGURE 1 with a representative sense amplifier shown in greater detail. The sense amplifier 40 is connected to half digit lines 42 and 44. A memory cell 46 has an access transistor 46a and a storage capacitor 46b similar to the memory cell circuit described above. A further memory cell 48 includes an access transistor 48a for connecting a storage capacitor 48b to the half digit line 44.

A pull up circuit 50 is connected to half digit line 42 and a pull up circuit 52 is connected to half digit line 44. A precharge transistor 54 connects half digit line 42 to bus line 32 and a precharge transistor 56 connects half digit line 44 to bus line 32.

Within sense amplifier 40 there is a transistor 5^'8 which has drain and source terminals connected to couple half digit line 42 to a node 60. A corresponding transistor 62 connects a node 64 to the half digit line 44. The gate terminals of transistors 58 and 62 are connected to the supply voltage. A transistor 66 has the drain and source terminals thereof connected between node 60 and latch node 24. The gate terminal of transistor 66 is connected to the node 64. A further transistor 70 has the drain and source terminals thereof connected to couple node 64 to node 24. The gate terminal of transistor 70 is connected to node 60.

A number of timing and control signals which are used in_ the circuits described herein are illustrated in FIGURE 2. These comprise a row address strobe (RAS) signal 76, a word line signal 78, a latch signal 80, a pull up signal 82 and a precharge signal 84.

Operation of the memory circuit illustrated in FIGURE 1 is described herein and is further described in U.S. Patent No. 4,061,954. Referring now to FIGURES 1 and 2, each of the capacitors in the memory cells, such as 10 and 12, are charged to a voltage state that represents a binary value. In the usual case the capacitors are charged to either a high (+5 volts) or a low (0 volt) level. The voltage on the capacitor is then correlated with a particular binary state, 0 or 1

Circuitry external to the memory circuit shown in FIGURE 1 generates the RAS signal 76 which causes the generation of the word line signal 78. The word line signal is applied to a selected word line, such as 16 or 20 depending upon the row address applied to the memor circuit. Upon receipt of the word line signal 78 to word line 16, the transistor 10a is turned on to couple capacitor 10b to the half digit line 14. Assuming that the half digit lines 14 and 18 are initially charged to 2.0 volts, the coupling of the capacitor 10b will alter the voltage on half digit line 14 by a slight amount. The capacitance of line 14 is approximately 10 times that of capacitor 10b. Therefore, if capacitor 10b is charged to +5 volts the half digit line 14 will be elevated to approximately 2.3 volts and if the capacitor 10b is charged to 0 volts the half digit line 14 will be lowered to approximately 1.8 volts. Assume that capacitor 10b initially has a +5 volt charge upon receipt of the word line signal 78. The half digit line 14 will be elevated to 2.2 volts. Upon receip of the downward transition of the latch signal 80 by the sense amplifier 22 the amplifier pulls the half digit line which has the lowest voltage thereon downward to approximately 0 volts. For this example half digit line 18 would be pulled downward to 0 volts.

The sense amplifiers 22 and 40 are identical and the internal structure of the sense amplifiers is illustrated for amplifier 40. Assume that half digit line 42 has been elevated to 2.3 volts and half digit line 44 remains at 2.0 volts. Under these conditions, the downward transition of latch signal 80 is applied to node 24. Transistors 58 and 62 function as resistors in this circuit as explained in U.S. Patent No. 4,061,954. Transistors 58 causes node 60 to be at the 2.3 volt potential of digit line 42 while transitor 62 causes node 64 to be at the 2.0 volt potential of digit line 44. The transistors 66 and 70 each have a threshold voltage of approximately .5 volts and such a voltage must be reached between the gate and source terminals thereof before the transistor begins to conduct. As the voltage on node 24 drops, transistor 70 will be first turned on due to the greater potential on its gate terminal as compared to the potential on the gate terminal of transistor 66. As transistor 70 is turned on the charge on nodes 64 and 44 are discharged through transistor 70 thus lowering the voltage on node 64. If the voltage on the latch node 24 is lowered slowly enough transistor 66 is not turned on and the voltage on node 60 does not change. As the voltage on node 24 becomes less, node 64 is further discharged thus lowering the voltage on the gate of transistor 66. When the voltage on node 24 is finally pulled to 0, node 64 is fully discharged while the voltage on node 60 is unaffected since transistor 66 was never turned on. The sense amplifier 40 thus pulls the voltage down on the half digit line having the lower initial voltage thereby sensing slight voltage differences between the two half digit lines. Following the downward transition of latch signal 80 the upward transition of the pull up signal 82 is applied to the pull up circuits 26 and 28. The pull up circuits detect -the existence of a voltage on the half digit line above a preset threshold voltage and if such a voltage is present the half digit line is pulled up to the supply voltage. In the present example, line 14 would be elevat from 2.3 volts to approximately 5.0 volts. Thus, after t pullup operation, half digit line 14 is charged to 5.0 volts and half digit line 18 is at 0 volts. The state of the half digit lines is then read through output circuitr (not shown) .

The next step is equalization of the voltages on the half digit lines so that the upcoming read operation can be undertaken. This is carried out in response to the upward transition of the precharge signal 84 which is supplied_, to all of the precharge transistors 30, 34, 54 and 56. The precharge signal 84 turns on the precharge transistors to connect the bus line 32 to each of the hal digit lines so that there is a current flow from those lines at 5 volts to those lines at 0 volts. The precharg transistors are turned on for a sufficient period of time so that the voltages on the half digit lines have equilibrated to substantially equal levels. The equalization of these voltages is critical since^ as noted above, a single memory cell produces only a small voltage shift on the corresponding half digit line.

The voltages on the half digit lines become more equal as the precharge transistors are held on for a greater length of time. For sufficient equalization the precharge transistors must generally be turned on for at least 5 time constants for the resistance and capacitance of the combination comprising primarily the resistance of bus line 32 together with the capacitance of all of the half digit lines in the memory. As the number of bits of storage of a memory circuit increases the number of digit lines increases. This increases the length of bus line 32 thereby increasing its resistance. The increased number of digit lines also increases the total capacitance of these lines. As can be seen from this description the time required to equilibrate the half digit lines is essentially proportional to the square of the number of digit lines in the memory circuit since each half digit line contributes an equal capacitance and an equal incremental resistance to bus line 32. For a small memory circuit such as a IK or a 4K, this contribu^'tion to equilibration time is generally negligible. But, for a large memory array, such as 64K, the equilibration time utilized by the precharge circuit described above becomes significant and can substantially slow down the cycle time of the memory.

A precharge circuit that alleviates the above described problem is illustrated in FIGURE 3. Referring now to FIGURE 3, there is shown a basically similar layout of a memory circuit as described in reference to FIGURE 1. A sense amplifier 90 is connected between half digit lines 92 and 94. A plurality of memory cells, such as 96, are connected to the half digit such as lines 92. Cell 96 is controlled by signals transmitted through a word line 98. Likewise, a memory cell 100 is connected to half digit line 94 and is controlled by signals received through a word line 102. A pull up circuit 104, such as described above, is connected to half digit line 92 and a pull up circuit 106 is connected to half digit line 94. A first precharge transistor 108 connects half digit line 92 to a latch node 110 and a second precharge transistor 112 connects half digit line 94 to latch node 110. The gate terminals of transistors 108 and 112 are connected to receive the precharge signal shown in FIGURE 2.

A second pair of half digit lines 116 and 118 are connected to a sense amplifier 120 which is illustrated in detail and corresponds to sense amplifier 90. Memory

OMPI cells 122 and 124 are connected respectively to half digit lines 116 and 118. Likewise, pull up circuits 126 and 128 are connected to half digit lines 116 and 118. Sense amplifier 120 is connected to latch node 110. A first precharge transistor 132 has its source and drain terminals connected between half digit line 116 and node 110. A second precharge transistor 134 has its source and drain terminals connected between half digit line 118 and node 110. The internal structure of sense amplifier 120 is the same as sense amplifier 40 described above. Sense amplifier 120 includes transistors 136 and 138 which respectively couple half digit line 116 to a node 140 and half digit line 118 to a node 142. The gates of transistors 136 and 138 are connected to the supply voltage. Amplifier 120 further includes transistors 144 and 146 which selectively couple nodes 140 to latch node 110 and node^' 142 to node 110 upon receipt of the downward transition of the latch signal at node 110. The gate terminal of transistor 144 is node 142 while the gate terminal of transistor 146 is node 140.

Operation of the precharge circuit of the present invention is described in reference to the circuit illustrated in FIGURE 3 and the signals shown in FIGURE 2 The sequence of operations whereby the half digit lines

116 and 118 are driven to complementary voltage States by operation of the sense amplifier 120 and the pull up circuits 126 and 128 is the same as that described above for FIGURE 1. At the end of the pull up sequence one of the half digit lines will be at 5.0 volts and the other half digit line will be at 0 volts. The precharge signal 84, shown in FIGURE 2, is connected to the precharge transistors 132 and 134 so that upon the transition of th precharge signal from a low to a high level the transistors 132 and 134 are turned on. When these transistors are turned on nodes 116 and 118 are each connected with the latch node 110 and thereby to each

OMP other. At this time in the memory cycle the latch node 110 is no longer driven but instead is permitted to float. Thus upon activation of the precharge signal the voltages on the half digit lines 116 and 118 equilibrate by current flow through latch node 110. The time constant of the combination of circuit elements including the half digit lines 116 and 118 together with the node 110 and transistors 132 and 134 is much less than that for an equivalent large memory circuit utilizing the precharge circuit illustrated in FIGURE 1. The precharge portion of the memory cycle utilizing the precharge circuit of the present invention is therefore substantially less and is sufficiently short to be tolerable in the operation of a large semiconductor memory. The use of two precharge transistors as shown in FIGURE 3 is particularly advantageous in an MOSFET memory as described above since the two transistors can be interconnected to the latch node and thereby eliminate a crossover path. As described above the precharge signal shown in FIGURE 2 is supplied simultaneously to the precharge transistors 132 and 134, however, it is not necessary that the same precharge signal be supplied to each of the precharge transistors. Separate precharge signals can be used as long as the precharge transistors of a pair have at least a limited common on time? In summary, the present invention provides a precharge circuit for a semiconductor integrated circuit memory wherein the half digit lines are interconnected through a latch node rather than through a bus line which interconnects all of the digit lines in the circuit. The precharge circuit of the present invention provides a precharge operation which requires substantially less time to equilibrate the voltages on the half digit lines. Although one embodiment of the invention has been illustrated in the accompanying Drawings and described in the foregoing Detailed Description, it will be understood that the invention is not limited to the embodiment disclosed, but is capable of numerous rearrangements, modifications and substitutions without departing from the scope of the invention.

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Claims

1. In a semiconductor memory circuit having a plurality of pairs of half digit lines which are driven to one of a set of preselected voltage states after a memory ..cell is read by coupling the cell to one of the pair of half digit lines, the read operation including receipt of a latch signal through a latch node, a precharge circuit for equilibrating voltages on the complementary half digit lines comprising: means for connecting a first half digit line to said latch node upon receipt of a precharge signal; and means for connecting a second half digit line, which is the complement of said first half digit line, to said latch node upon receipt of a precharge signal, wherein said first and second half digit lines are interconnected through the latch node upon receipt of said precharge signals thereby equilibrating the voltages on said first and second half digit lines.

2. A precharge circuit as recited in Claim 1 wherein said means for connecting a first half digit line to said latch node comprises a field effect transistor having a selected one of the drain and source terminals thereof connected to said first half digit line, the remaining one of the drain and source terminals thereof connected to said latch node and the gate terminal thereof connected to receive said precharge signal which activates said transistor to produce a conductive path between said first half digit line and said latch node.

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3. A precharge circuit as recited in Claim 1 wherein said means for connecting a second half digit line to said latch node comprises a field effect transistor having.a selected one of the drain and source -terminals thereof connected to said second half digit line, the remaining one of the drain and source terminals thereof connected to said latch node and the gate terminal thereof connected to receive said precharge signal which activates said transistor to produce a conductive path between said second half digit line and said latch node.

4. In a semiconductor memory a precharge circuit for equilibrating each pair of half digit lines where a sense amplifier discharges one of the half digit lines in response to a latch signal supplied through a latch node after a memory cell has been coupled to one of the half digit lines, the precharge circuit comprising: a first transistor having drain, source and gate terminals, a selected one of the drain and source terminals thereof connected to a first half digit line, the remaining one of the drain and source terminals thereof connected to said latch node and the gate terminal thereof connected to receive a precharge signal which activates said first transistor to produce a conductive path between the drain and source terminals 'thereof; and a second transistor having drain, source and gate terminals, a selected one of the drain and source terminals thereof connected to a second half digit line, which is the complement of said first half digit line, the remaining one of the drain and source terminals thereof connected to said latch node and the gate terminal thereof connected to receive a precharge signal which activates said second transistor to produce a conductive path between the drain and source terminals thereof, wherein said first and second half digit lines are interconnected through the latch node upon occurrence of said precharge signals thereby equilibrating the voltages on said first and second half digit lines.

5. In a semiconductor memory circuit where memory cells are selectively coupled to one line of a plurality of half digit line pairs and a sense amplifier is connected to both of the half digit lines of a pair to draw one of the half digit lines to a low voltage level in response to a latch command received through a latch node and a pull up circuit elevates the other line of the half digit line pair to a high voltage level, a method for equilibrating the voltages on each of the half digit lines comprising the steps of: connecting a first half digit line through a conductive path to said latch node in response to a precharge signal; and connecting the second half digit line through a conductive path to said latch node in response to a precharge signal wherein said first and second half digit lines are voltage equilibrated by current flow through said latch node.

WIP