EP0048781A1 - Communication line adapter for a communication controller - Google Patents

Abstract

Line adapter for transferring information between terminals and a bus connected to the CCU central control unit of a communication controller. It comprises a microprocessor (1) associated with a control memory (2) and a scanning device (7). A memory (11) is divided into zones, a zone being assigned to each line (20-a, 20-b) etc. During an initialization phase, the zones are personalized under microcode control by sending to the memory (11) via an asynchronous path, external register, bus (14), initialization parameters characteristic of the lines such as SDLC, BSC, S / S, etc. The exchange of the data temporarily stored in the zones (11) between the CCU BUS and the lines is done by cycle flight from the memory (2) to the memory (11) in transmission, and from the memory (11) to the memory (2) in reception.

Description

Technical area

The present invention relates, in a communications controller, to an adapter for communication lines making it possible to take into account the different communication protocols which govern the transmission of data on the lines as well as the different possible transmission speeds.

Communications controllers are devices intended to be incorporated in a data processing installation, so as to manage the transmissions on the various lines which are attached to it. Generally, the main command of the remote processing network is concentrated in one or more central processing units CPU containing a directory of rules for processing data originating from or going to the terminal stations or terminals of the remote processing network. The sending and receiving of data through transmission lines is managed by communications controllers placed under the control of the central processing unit (s). However, in addition to the execution of transmission commands in the strict sense of the term, the controller is responsible for executing functions of the directory, in particular functions coming directly from standard transmission procedures. As a result, the central processing units (CPUs) are freed from the corresponding tasks and can devote themselves to carrying out other work.

The communications controller is a complex assembly with an intelligence which is mainly concentrated in one or more central control units CCU. The central control units are connected on the one hand to the terminals through line adapters and on the other hand to the central processing units CPU through channel adapters so designated because of the fact that they are connected to the channels of the central processing unit (s).

The line adapters can serve a certain number of transmission lines by means of a cyclic scanning device, and of a set of random access memories, in which are temporarily stored, the data received or to be sent on the different lines under control of the scanning device.

In such an environment, each line adapter can be connected to lines sending and receiving information from terminals of different types and therefore the protocols and data transmission rates are different. For a data communication network to be as flexible as possible, the different lines must be able to support all the transmission protocols. So we can realize any network configuration.

Generally, each line is associated with a particular adapter circuit, the design of which depends on the data transmission protocol on the line. It is obvious that this solution is expensive and lacks flexibility, because when you want to change the network configuration, you must change the adaptation circuits.

Another solution would be to manage the communication protocols only by firmware. This solution offers great flexibility but is not satisfactory because the performance of certain functions by firmware requires a much greater time than their achievement by appropriate circuits. Consequently such a solution does not achieve high performance.

Statement of the Invention

An object of the present invention is therefore to provide a line adaptation circuit which makes it possible to obtain maximum flexibility for the creation of a remote processing network.

Another object of the present invention is to provide such an adaptation circuit which allows the processing speed characteristics to be preserved.

In accordance with the present invention each line adapter is divided into two parts. The first part is organized around a microprocessor and a set of memories. The microprocessor manages the data sent by the central control unit CCU to the lines via the circuits of the scanner in the second part and vice versa. The set of memories acts as a buffer between the central control unit and the scanning device.

The second part is organized around the scanning device and allows the control of communication lines. This part receives or transmits the data on the lines via a modem or not depending on the type of lines, long distance or short distance and an interface circuit. The scanning circuit includes means for deserializing the data received and serializing the data to be transmitted. In this scanner the data is stored in random access memories. Under the control of an address selection device, the lines are scanned by cyclically exploring the memory positions.

Exchange of information between device memories scanning and the microprocessor is done via the external microprocessor registers and by cycle stealing directly in the microprocessor control memory.

The interface between the two parts includes three exchange paths. The first input / output path is an asynchronous path used essentially during the initialization mode in order to personalize the memories of the scanning device under microcode control according to the characteristics of the lines. A second path is used to make interrupt requests, and a third path is used for the exchange of data by cycle flight between the memories of the scanning device and the microprocessor control memory, under the control of the processing device. scanning.

Other objects, characteristics and advantages of the present invention will emerge more clearly from the following description, made with reference to the drawings appended to this text, which represent a preferred embodiment thereof.

Brief Description of the Figures

• FIG. 1 represents the overall diagram of a system in which the present invention can be incorporated (LAI, LA2, LAn).
• Figure 2 shows the diagram of a line adapter according to the present invention.
• FIG. 3 represents the external registers used in the asynchronous initialization operation.
• FIG. 4 represents the arrangement of a memory zone LIB and of the zone "parameter-state" which is associated with it in the microprocessor control memory.
• Figure 5 shows the external registers that are used in the interrupt request process.
• FIG. 6 represents the elements of the line interface circuit associated with a link.
• FIG. 7 represents the content of a memory area LIB and of the associated parameter-state area for a transmission operation.
• FIG. 8 represents the content of a memory area LIB and of the associated parameter-state area for a reception operation.

Detailed Description of the Invention

With reference to FIG. 1, the overall diagram of a system in which the present invention can be incorporated will be described by way of example. The CC communication controller is an element of a remote processing network, a configuration example of which can be found in the book "Téléinformatique" by G. Macchi and JE Guilbert, in particular in chapter 10. In the communication controller, the unit CCU central control unit manages the data passing between the T terminals and central processing units CPUI and CPU2. The CCU unit is connected to MPX bus multiplex channels of the central processing units CPUI and CPU2 via channel adapters CA1, ..., CAn. It is also connected to the terminals T through line adapters LA1, ..., LAn connected to a CCU Bus bus.

In such an environment, the present invention relates to the production of line adapters, an embodiment which is modular, that is to say that the same adapter can be used whatever the protocols and speeds of transmission on the lines to which it is connected.

Figure 2 schematically shows an adapter according to the present invention. It comprises a microprocessor 1 associated with a control memory 2 comprising a space for the storage of the microprocessor control microcode and a space for the storage of data. This memory is addressed by the microprocessor by the address path 3. The microprocessor is also associated with a local memory 4 which it addresses by the address path 5. The input / output bus, I / O Bus 6 ensures the transit of information between the CCU Bus of the remote processing system and the line adapter by operations initialized by program (PIO) and operations initialized by the adapter (AIO). Bus 6 is connected to local memory 4 by a bus 6a, to the control memory by a bus 6b and to the microprocessor by a bus 6c.

A line scanning device 7 is connected to the microprocessor-memory assembly. In FIG. 2, only the elements essential for understanding the present invention have been represented.

External registers 8 which can be addressed by the microprocessor by the address path 9, allow the microprocessor to communicate with the device 7 by writing or reading operations in the registers 8. They are written or read by the bus 10.

A set of random access memories 11 is divided into several zones, each zone being associated with a communication line. This set is addressed by the path 12 via an address selection device 13. As will be seen below, depending on the operating mode, the addresses are forced by the content of the external registers 8 or they are established by the device 13 itself to control the line scanning operation.

The bus 14 makes it possible to transfer information from the external registers to the memory assembly 11 or vice versa.

The assembly 11 communicates with the memory 2 of the microprocessor in a mode known as "cycle flight" so as to exchange information between an area of the memory 11 selected by the device 13 and a position of the control memory selected by the address information placed in an input / output register 15 comprising an address part and a data part. The data is exchanged by the bus 16 and the addressing of the memory is carried out by the path 17. An interrupt path 18 is also provided to interrupt the microprocessor under certain conditions reported in one of the external registers.

The adapter is connected to the communication links, a link comprising two lines 20a and 20b, if it is bidirectional, and a line if it is uni-directional, to receive and transmit the information to the terminal possibly via a modem 21. Line interface circuits LIC, 22-1 to 22-4 are placed between the scanner 7 and the lines. These interface circuits are connected to the set of memories 11 by buses 23-1 to 23-4 respectively. It includes line drive and reception circuits, and registers for temporarily storing the bits of data received or to be transmitted on the lines to which they are connected. The registers are addressed under control of the device 13, by the addressing path 12 ′.

LIC line interface circuits processing information in serial form, and the scanning device 7 and the microprocessor working on 8-bit bytes, it is necessary to provide a logic circuit 24 placed on the bus 23 to ensure the serialization of the data in transmission and deserialization in reception as well as other logical functions in connection with memories.

Data can be received or transmitted using different protocols, for example SDLC (Synchronous Data Link Control), BSC (Binary Synchronous Communication) and arrhythmic S / S (Start / Stop). For each of the different protocols, transmission parameters are defined such as length of characters for the S / S and BSC protocols, length of the stop code for the S / S protocol, length and type of the CRC control characters, etc. An example parameters definition will be given later.

Communication between the scanning device and the microprocessor takes place in two modes: an asynchronous mode which involves the intervention of the microcode in memory 2 and a synchronous mode independent of the microcode.

Asynchronous mode is used to perform three types of operations.

1 - Initialization phase

The initialization phase is the phase during which the definition of a remote processing network takes place. The system being placed in the initialization mode, the characteristic parameters of each line of the network are stored under the control of the microcode in the memory 11 by a procedure which will be described later. For this, each memory position zone assigned to each particular line receives, via the external registers, in a given field, the initialization parameters characterizing the line. The remaining fields are assigned to the storage of data, their control parameters and their status information characterizing the conditions for the completion of a data exchange. During this phase, the memory assembly 11 is personalized according to the configuration.

2 - Management of the interface wires with the modem

Interface wires (not shown on the Figure 2) are associated with lines 20a, 20b, on these wires pass the control signals of the link. To process the control signals on these wires it is not necessary to have optimum performance but maximum flexibility is desirable so as to be able to manage different types of modems and procedures which are known at present or which could be developed in the future.

The control information going to the modem is sent by the microcode in asynchronous mode by means of the devices 10, 9 and registers 8 and is also stored in a register which will be called "modem output". At each scanning period of the corresponding line, the configuration on these wires is compared with the configuration on the line drivers obtained by local reception circuits by means of a mask determined by the microcode. Any disagreement between the two configurations generates an error condition "Verification of the drive circuits". Thus, the driver circuits of the modem concerned are checked.

At each scanning period, the information on the wires coming from the modem is stored in a "modem input" register and is compared with the information "modem input" kept in the corresponding memory area 11. This comparison operation is triggered by the microcode and is carried out by means of a mask determined by the microcode. A disagreement between the two configurations generates an interrupt request and interrupts the comparison until the microcode resumes it. This prevents multiple interruptions from occurring in the event of a permanent change to modem control wires due to erratic error conditions.

3 - Processing of requests for interruption

Synchronous mode is used for the transfer of information by cycle flight directly into the microprocessor control memory 2 via path 16 and register 15. The information: data, control parameters, associated status information are transferred from / in memory 2 without intervention of the microcode.

The part of memory 2 reserved for this purpose has been divided into LIB memory zones, one zone being assigned to each line.

The exchange of data by cycle flight is a well known operation, it is carried out by means of commands generated by the microprocessor 1. The device 7 can access the memory 2 when the microprocessor has responded to a flight request from cycle by a signal "cycle flight granted". Then the address in the memory 2 of the zone to which the transfer operation must take place is provided to the address part of the register 15. The addressing of the memory 2 is carried out by the path 17 and the transfer of the data by bus 16.

We will now describe with reference to FIG. 3 how the initialization operation is carried out. In this operating mode, the microprocessor communicates to the scanning device 7 the information of the initialization mode previously supplied to the microprocessor by the central control unit CCU, by executing instructions for writing to the external registers.

For this operation, four external registers 8-1, 8-2, 8-3 and 8-4 are necessary. In the register 8-1 the microcode causes the loading of the address of the line (for example 20-a) by which the initialization operation takes place. Successively each line can be treated according to the same process.

In the register 8-2, the microcode causes the loading of the address in the memory unit 11 to which the initialization parameters must be written and in the register 8-3 the initialization parameters themselves.

The formats of the initialization parameters are as follows, these formats are given by way of example and it is obvious that if other protocols or mode of transmission were to be used, other parameters could be defined.

Each parameter has 8 bits from 0 to 7. When the line is a transmission line (such as 20b) bits 0 to 7 have the following meaning:

Bits 0, 1, 2:

Bit 3:

This bit is not used in S / S and SDLC modes. In BSC mode it is used as follows:

BSC, standard interface type X21 if bit 3 is set to 1.

BSC ASCII / EBCDIC bit 3 must be taken into account with bit 2.

Bit 4:

According to the protocol, this bit means:

Bit 5:

• BSC par code si 1 signifie mono SYNC
• BSC ASCII / EBCDIC en conjonction avec le bit 4 indique le type de contrôle d'erreur.
• 1 0 CRC S (CRC = Cyclic Redundancy Checking)
  

This bit is not used for S / S and SDLC protocols. For the BSC protocol it is used as follows:

• BSC by code if 1 means mono SYNC
• BSC ASCII / EBCDIC in conjunction with bit 4 indicates the type of error checking.
• 1 0 CRC S (CRC = Cyclic Redundancy Checking)
  

Bits 6 and 7:

For S / S protocols, BSC by code, these two bits give the character length:

When the line is a receive line, the definition of the bits is the same as before.

For the S / S protocol, the start and stop bits are not taken into account in the definition of the character length, they are removed from the bit stream sent by the terminal to receive pure data characters.

In addition, for a receiving BSC line, the configuration of the synchronization characters must be provided and for a sending BSC line, the configuration of the synchronization character to be inserted every second.

Due to the division of the control memory 2 into LIB memory zones associated with each line ensuring the temporary storage of data in the exchange operation by cycle flight, it is also necessary to provide a starting address determining which LIB memory zone is assigned to the line. The format of this address will be given later when describing the arrangement of the LIB memory areas in memory 2.

Data exchanges take place by byte. An additional external register 8-4 is used to know the end and the result of the exchange.

• Il est mis à 1 lorsque le registre 8-2 est chargé et il est remis à zéro lorsqu'un nouvel échange de données peut avoir lieu concernant une nouvelle ligne et que les données sont placées dans le bon emplacement.

A bit of this external register 8-4 is handled by the scanner as follows:

• It is set to 1 when register 8-2 is loaded and it is reset to zero when a new data exchange can take place concerning a new line and the data is placed in the correct location.

We will now describe with reference to FIG. 4, the arrangement of the part of the control memory 2 reserved for the exchange of data in cycle flight by the synchronous path, bus 16, register 15 of FIG. 2.

The memory 2 is divided into LIB memory zones such as 40 in FIG. 4. A LIB zone is assigned to each communication line. There are as many LIB zones in memory 2 as there are lines managed by the adapter.

Due to the structure of the data, the LIB areas are divided into blocks containing 8 bytes. For the SDLC and BSC protocols, the data is preceded and followed by padding and control characters. In SDLC data reception mode, several frames can be received and the data must be loaded separately to identify these different frames. This is what led to the subdivision of the LIB 40 zones into blocks 41. The zone 40 has been shown divided into 8 blocks 41-1 to 41-8. A complete block can be transferred without interrupting the microcode.

Each LIB zone is associated with a "State parameters" memory zone 42 used for storing control parameters and state information. Each block 41 is assigned a block 43 of the zone 42, for example block 41-1 is associated with block 43-1 and block 41-8 is associated with block 43-8. Each block 43 allows two bytes to be stored.

Before using a block, the associated control parameters, the definition of which will be given later, are transferred by the microcode to the appropriate area 43 and at the end of the processing of a data block, the status information is transferred by the scanning device 7 in block 43 and replaces the parameters.

The microcode. is only interrupted at the end of the processing of a data block if this is required by the parameters. Thus, the message can be sent with a single interruption at the end of the message, or the microcode is only interrupted once a predetermined quantity of data has been processed by the device 7 to obtain or send additional data from / to the CCU central unit.

In reception mode a message is terminated when the end command character is detected. The end information is state information. In BSC the microcode checks the last character of the block to identify the end character (ETB, ETX, ENQ).

The storage capacity of the LIB zones can be determined according to the protocol of the corresponding line, the size of the messages and the speed on the line. The size of a LIB area can vary from 64 to 256 bytes and the storage capacity in a block can vary from 1 to 8 bytes.

• Les deux premiers bits donnent la longueur de la zone LIB en nombre de blocs, un bit suivant indique, s'il est à 0 qu'il s'agit de l'adresse d'une zone LIB, pour passer à la zone "Paramètre-Etats" 42, il est mis à 1. Les bits restants sont des bits d'adresse.

The different LIB zones are assigned to each line in the initialization mode by means of the "starting address" data which is written in memory 1. This data has the following format:

• The first two bits give the length of the LIB area in number of blocks, a next bit indicates, if it is 0 that it is the address of a LIB area, to go to the "Parameter" area -States "42, it is set to 1. The remaining bits are address bits.

This starting address information is used to carry out the addressing of the memory 2 via the path 17 and to know at which locations must the transfer operations in cycle flight take place.

The commands are sent by the control microcode to the device 7 in order to start or stop the transmission of the data on a "Transmission" line such as 20-b or the reception of the data on a reception line such as 20a. These commands are sent to the appropriate line using the asynchronous route; external registers 8, bus 11 and by sending control parameters to memory 11.

We will now give, by way of example, a definition of the parameter field and of the state information that can be used.

Definition of the Parameter Field . "Emission" line

• Bit 0 . bloc valide (bloc peut être transmis. Ce bit indique que le bloc de données associé contient des données à envoyer. Il est mis à zéro par le microcode de commande et mis à un pour le disposition de balayage lorsque l'information d'état est échangée.
• Bit 0 = 0 bloc valide
• Bit 0 = 1 bloc non valide)
• Bit 1 commencer transmission des données.
• Bit 2 Interruption demandée. Ce bit oblige le dispositif 7 à faire une demande d'interruption par l'intermédiaire d'un registre externe et de la ligne 18 lorsque le dernier caractère du bloc a été envoyé à la mémoire 11 dans la position appropriée correspondant à cette ligne.
• Bits 5, nombre d'octets de données dans le bloc. Ces bits 6, 7 indiquent le nombre de multiplets à prendre de ce bloc (de 1 à 8 multiplets en partant du début du bloc)
• Bit 8 envoyer CRC (valable pour le protocole SDLC). Ce bit signifie qu'à la fin du bloc le CRC accumulé [CRC mode de contrôle d'erreur: Cyclic redundancy Checking] doit être envoyé.
• Bit 9 commencer sur octet impair. Si ce bit est à 1 le dispositif de balayage agit comme si le premier multiplet (multiplet 0) du bloc était déjà traité (ceci permet de commencer sur le second multiplet: multiplet 1, impair.)
• Bits 11, Si "00" données intermédiaires
• ¹² "01" dernière données, fin de message EOM. Dans ce cas le dispositif 7 envoie le bloc complet. Lorsque le dernier bit du dernier caractère à envoyer a été transmis au modem, le dispositif 7 interrompt le code de commande et arrête la transmission (EOT).
• Si 1 0 continuer à transmettre ces données en permanence (boucle). Lorsque les dernières données du bloc ont été lues, le dispositif de balayage revient aux premières données.
• Si 1 1 fin de message avec reprise (turn around) même opération que précédemment (01) mais la ligne est mise automatiquement en mode début réception au temps EOT (fin de transmission).
• Bit 13 Pas d'insertion de zéro dans ces données, pas d'accumulation CRC (SDLC) ou transmission interrompue (S/S). Ce bit demande que le dispositif 7 ne réalise pas d'insertion de zéro pour tous les multiplets de données compris dans ce bloc.
• Bit 14 démarrer dispositif mesure de temps.
• Bit 15 envoyer contenu registre "Modem-sortie" à la fin du bloc.

This field contains 16 bits from 0 to 15, the bits having the following meaning:

• Bit 0. valid block (block can be transmitted. This bit indicates that the associated data block contains data to be sent. It is set to zero by the control microcode and set to one for the scanning layout when the status information is exchanged.
• Bit 0 = 0 valid block
• Bit 0 = 1 invalid block)
• Bit 1 start data transmission.
• Bit 2 Interruption requested. This bit obliges the device 7 to make an interrupt request via an external register and line 18 when the last character of the block has been sent to memory 11 in the appropriate position corresponding to this line.
• Bits 5, number of bytes of data in the block. These bits 6, 7 indicate the number of bytes to be taken from this block (from 1 to 8 bytes starting from the beginning of the block)
• Bit 8 send CRC (valid for SDLC protocol). This bit means that at the end of the block the accumulated CRC [CRC error control mode: Cyclic redundancy Checking] must be sent.
• Bit 9 start on odd byte. If this bit is at 1 the scanning device acts as if the first byte (byte 0) of the block was already processed (this allows to start on the second byte: byte 1, odd.)
• Bits 11, If "00" intermediate data
• ¹² "01" last data, end of EOM message. In this case the device 7 sends the complete block. When the last bit of the last character to be sent has been transmitted to the modem, the device 7 interrupts the command code and stops the transmission (EOT).
• If 1 0 continue to transmit this data permanently (loop). When the last data in the block has been read, the scanner returns to the first data.
• If 1 1 end of message with recovery (turn around) same operation as previously (01) but the line is automatically put into reception start mode at EOT time (end of transmission).
• Bit 13 No insertion of zero in this data, no CRC accumulation (SDLC) or interrupted transmission (S / S). This bit requests that the device 7 does not insert zero for all the bytes of data included in this block.
• Bit 14 start time measurement device.
• Bit 15 send register content "Modem-output" at the end of the block.

. "Reception" line

• Bit 0 bloc valide. (bloc prêt à recevoir des données, les données peuvent être envoyées par le dispositif 7. Il est mis à zéro par le microcode de commande et mis à un par le dispositif de balayage lorsque l'information d'état est échangée.
• Bit 0 = 0 bloc valide
• Bit 0 = 1 bloc non valide)
• Bit 1 commencer réception des données
• Bit 2 faire une demande d'interruption à la fin du bloc.
• Bits 5, nombre de multiplets maximum à mettre dans ce ⁶ _, ⁷ bloc.

Only eight bits are used in the control parameter field.

• Bit 0 block valid. (block ready to receive data, the data can be sent by the device 7. It is set to zero by the control microcode and set to one by the scanning device when the status information is exchanged.
• Bit 0 = 0 valid block
• Bit 0 = 1 invalid block)
• Bit 1 start receiving data
• Bit 2 make an interrupt request at the end of the block.
• Bits 5, maximum number of bytes to put in this ⁶ _, ⁷ block.

Definition of the status information field . "Emission" line

• Bit 0 = 1, Block valid. This bit means that the data contained in this block has been sent and that the block can be re-used by the control microcode to put other data.
• Bit 2 an interruption had been requested by the command code (via parameters).
• Bits 5, account of transmitted data. 6, 7
• Bit 10 missing character
• Bit 11 change content "Modem-input" register. This bit indicates that a change in the contents of the "modem-input" register occurred during the processing of this block. Status information is immediately sent and an interruption is immediately requested.
• Bit 12 = EOT (end of transmission. This bit is set to 1 if the scanner 7 has processed a block with end of message information (EOM) in the corresponding parameter field.

. "Reception" line

• Bit 0 block valid. The scanner 7 sets this bit to 1 when the status information is transferred by cycle flight in order to inform the command code that the associated block has been filled. The data can be used by the control microcode.
• Bit 2 an interrupt was requested by the command code via the parameters.
• Bits 5, counts the data received in this block. 6, 7
• Bits 8, if 000 intermediate data
• 12, ¹³ if ₀₀₁ end of reception without CRC verification error. 101 end of reception with CRC verification error. 011 flag limit badly framed 100 abandonment (the message started is bad, do not take it into account. 110 inactive state (the line has fallen back into a rest state).
• Bits if 10 normal service
• ⁹ _, 10 if 11 lost character (overflow).

The LIB areas, 40, are used to stack the data passing between the control unit CCU and the scanner 7 to prevent the conditions of overflow of characters and character request and to regulate the flow of data on the line.

For an operation on a transmission line, the data must be transferred from the CCU control unit to the scanning device in the associated memory area 11 and at the line. Conversely, for a reception operation, the data must be transferred from the reception line to the memory area 11 associated with the line, and then sent to the CCU.

The data is therefore taken from the CCU unit and brought into the appropriate LIB area (transmission operation) or moved from the LIB areas in the CCU unit (reception operation) 16 bytes at a time by AIO operations initialized by the adapter (control microcode).

The data is read and transferred from the LIB zones in the memory 11 (transmission operation) or from the memory 11 to the LIB zones (reception operation) two bytes at a time by operations in cycle flight, initialized by the scanning device. .

For each block of data exchanged between an LIB area and the memory 11, the two corresponding bytes of parameters provide the memory 11 with information concerning the data in this block or the data to be put in this block, what action must be performed by the scanning device at the end of the block such as: interruption of the microcode, ....

The end of block condition allows the device 7 to transfer the 2 bytes of status information which replace the two bytes of parameters associated with this block and to interrupt the microcode if necessary.

Interrupt requests are either made by the microcode via the parameters or made by the device 7, in the event of an abnormal end of data transfer condition.

For this, two registers are provided in the external registers 8. These registers are represented diagrammatically in FIG. 5. The scanning device 7 identifies and sends the address of the line for which the interrupt request is made in the external register of IRR 8-5 interrupt request and the reason for the interrupt request either in the IRR 8-5 register or in the EIRR 8-6 register.

We will now describe with reference to FIG. 6 how the information present on the control wires associated with the transmission and reception lines 20-b and 20-a is managed respectively. The elements represented in FIG. 6 allow the management of a reception-transmission link in connection with a modem 21. Consequently, in an LIC circuit there are as many of these elements as there can be links which are connected to them. .

Some of these wires transmit control information coming from the modem and others transmit control information going to the modem. The meaning of this information depends on the type of standard interface used, for example CCITT V 24 or V 25.

There are therefore two types of control information, the first will be called "input information" coming from the modem and the second "output information" going to the modem.

The signals received on line 20-a are transmitted to a receiver 60-1 in a set of circuits, 60, a receiver being associated with the line and with each control wire. Then they are sent to the scanning device 7 by bus 23 via a REG register 61. The signals to be transmitted on line 20-b are received from memory 11 via bus 23. They are stored in an intermediate register REG 62 and sent over the line by a circuit driver 63-1 in a circuit assembly 63, a driver circuit being associated with the line and with each control wire.

The information on the control wires coming from the modem 64, modem-input information is stored in a “modem input” register 65. This register can be addressed in the same way as a position of the memory 11 by the line 12 ' . The scanning device picks up the information contained in this register each time the line is scanned and stores it in the part of the memory 11 associated with this line to detect changes in the state of the control wires in accordance with the code provided. by the microprocessor through masking configurations.

Conversely, the information to be transmitted to a modem "information modem output" is generated by the microcode and placed in a "modem-output" position of the memory 11 associated with this line using the asynchronous path, 9, 10 external registers. When the line is scanned, the logic circuit 24 transfers the "modem-output" data to the "modem-output" register 66. The "modem-output information" control wires, 67, are taken at the output of register 66.

The modem-input information is processed as follows: in memory 11, two bytes per line are devoted to the "modem-input" configuration and to the "modem-input" command. The control byte is generated by the control code so that the scanner knows how to handle changes to "modem-input" data.

. "Modem-input" configuration bits 0 to 5

• Bit 0 Poste de données prêt
• Bit 1 Prêt à émettre
• Bit 2 Indicateur de tonalité
• Bits Sont transparents pour le
• 3 et 4 dispositif ⁷
• Bit 5 Bit de la ligne réception, il est donné au code comme indicateur lorsqu'un changement se produit. Généralement ce bit est masqué par le code.

According to the control byte (mask) all the bits of the configuration can be checked to find if a change has occurred, but only the first three have an effect on the operation of the device 7, these are:

• Bit 0 Data station ready
• Bit 1 Ready to send
• Bit 2 Tone indicator
• Bits are transparent to the
• 3 and 4 device ⁷
• Bit 5 Bit of the reception line, it is given to the code as an indicator when a change occurs. Generally this bit is masked by the code.

. "Modem-input" command bits 8 to 13

In logic device 24, incoming "modem-input" data must be compared with the previously stored configuration to detect any changes. The microcode can command a bit comparison selectively by loading a masking configuration in bits 8 to 13. This configuration undergoes an AND operation with the first six bits of the "modem-input" data.

When a change is detected, it is reported to the microprocessor.

• Dans la mémoire 11 trois octets sont alloués par ligne aux configurations "modem-sortie".
• . Deux octets de configurations "MOdem-sortie" (empilée/immédiate)

The "modem output" data processing is done as follows:

• In memory 11 three bytes are allocated per line to the "modem-output" configurations.
• . Two bytes of "MOdem-output" configurations (stacked / immediate)

These two configurations are transferred to the LIC circuits, 22 appropriate without modification by the device 7. They are given by the command code using the asynchronous path, 9, 10, external registers 8.

. Service request "Modem-output" bits 6 and 7 of the configurations.

When they are at zero, these bits cause the logic device 24 to send the "modem-output" configuration to the addressed line. These commands are established by the microcode using the asycnchronous path after the loading of the "modem-output" configuration by the same path.

The difference between the two commands is that the logic device 24 sends the immediate "modem-output" configuration as soon as the line is scanned and the "modem-output" configuration stacked only at the request of the microcode at the end of sending a data block if requested in the associated parameters.

. One byte, mask for checking the driver circuits.

By appropriately positioning the bits of this mask, the verification of certain drive circuits is inhibited.

We will now describe by way of example how a transmission operation takes place on a line. In the example chosen, the transmission mode on the line is SDLC mode. Reference may be made to FIG. 7 in which the contents of the associated LIB area 40 and of the "Parameter-states" area 42 are represented. The same references as in FIG. 4 have been used.

On the line on which the operation is to take place, is assigned an LIB area, used as a buffer between the central processing units and the scanner 7.

Each block in the LIB area is associated with a field in the Parameter-state area, as described above with reference to FIG. 4. This field is used in transmission to give information to the device 7. The information parameters are replaced by status information supplied by the scanner after the block transmission is completed.

• Bit 0 BV (bloc valide) lorsqu'il est à zéro il informe le dispositif de balayage que le bloc de champ paramètre correspondant est prêt à être traité par le dispositif de balayage pour une transmission de données. (1: bloc est vide, 0: bloc est plein).
• Bit 2 IR (interruption demandée) lorsque le dispositif de balayage a transmis le bloc il demande une interruption au microprocesseur avec l'indicateur IR=_l dans le champ d'état correspondant.
• Bits BL (longueur du bloc) indique le nombre de ⁵ _, 6, 7 caractères défini dans le bloc qui sont à transmettre sur la ligne (1 à 8 octets).
• Bit 8 S CRC (envoyer CRC) envoyer les deux caractères FCS (FCS= Frame Check Sequence) après avoir envoyé les données du bloc impliqué.
• Bit 9 S 0 O (commencer sur multiplet impair) le premier octet du bloc n'est pas transmis sur la ligne.
• Bits ND (données normales si 00)
• 11 et ¹² LB (dernier bloc si 01) dernier bloc à transmettre. Après la fin de la transmission, cet indicateur fera que le dispositif de balayage 7 fait une demande d'interruption pour informer le microprocesseur que le message a été envoyé (information d'état, bit EOT) (fin de transmission) mis à 1. TC (transmission continue) continuer à transmettre les caractères définis dans ce bloc si 10 EOM+TA (fin de message + bouclage).
• Bit 13 NZI (pas d'insertion de zéro) supprimer l'insertion du bit zéro après 5 bits 1 consécutifs envoyés sur la ligne: utiliser pour envoyer les fanions et caractères de remplissage. Lorsque ce bit est à 1, le CRC n'est pas accumulé.
• Bit 14 ST (démarrage dispositif de comptage de temps) actionne un dispositif de comptage de temps dans le dispositif 7. A la fin du temps, une interruption est demandée au microprocesseur.
• Bit 15 SMO (envoyer modem-sortie) l'information "modem-sortie" empilée est envoyée dans le registre 66 du circuit LIC correspondant à la fin de la transmission du bloc.

The parameter field comprises 16 bits, providing the indicators represented in FIG. 7 in the last zone 43-8, indicators which have the following meaning:

• Bit 0 BV (block valid) when it is zero it informs the scanner that the corresponding parameter field block is ready to be processed by the scanner for data transmission. (1: block is empty, 0: block is full).
• Bit 2 IR (interrupt requested) When the scanning device has transmitted the block, it requests an interrupt from the microprocessor with the indicator IR = _l in the corresponding status field.
• Bits BL (block length) indicates the number of ⁵ _, 6, 7 characters defined in the block which are to be transmitted on the line (1 to 8 bytes).
• Bit 8 S CRC (send CRC) send the two FCS characters (FCS = Frame Check Sequence) after sending the data of the block involved.
• Bit 9 S 0 O (start on odd byte) the first byte of the block is not transmitted on the line.
• Bits ND (normal data if 00)
• 11 and ¹² LB (last block if 01) last block to transmit. After the end of the transmission, this indicator will cause the scanner 7 to make an interrupt request to inform the microprocessor that the message has been sent (status information, EOT bit) (end of transmission) set to 1. TC (continuous transmission) continue to transmit the characters defined in this block if 10 EOM + TA (end of message + loopback).
• Bit 13 NZI (no zero insertion) delete the insertion of the zero bit after 5 consecutive 1 bits sent on the line: use to send flags and fill characters. When this bit is 1, the CRC is not accumulated.
• Bit 14 ST (start time counting device) activates a time counting device in device 7. At the end of the time, an interrupt is requested from the microprocessor.
• Bit 15 SMO (send modem-output) the stacked "modem-output" information is sent to register 66 of the LIC circuit corresponding to the end of the block transmission.

• Bit 0 BV (bloc valide)
• Bit 3 IR est à 1 lorsque IR dans le champ de paramètre était à 1.
• Bits BC, indique le nombre de caractères qui ont 5, 6, 7 été transmis de ce bloc (1 à 8 octets).
• Bit 10 UR (manque de caractère) est à un lorsque le dispositif de balayage vient transmettre le bloc correspondant mais trouve l'indicateur BV à 1.
• Bit 11 MC (changement modem) un changement de l'état des fils du modem s'est produit pendant la transmission du caractère.
• Bit 12 EOT (fin de transmission) est à 1 lorsque l'indicateur LB (dernier bloc) était à 1 dans le champ paramètre.

The status field represented at 44 in FIG. 7 contains the indicators associated with the completion of the transmission of a block:

• Bit 0 BV (valid block)
• Bit 3 IR is 1 when IR in the parameter field was 1.
• Bits BC, indicates the number of characters which have 5, 6, 7 transmitted from this block (1 to 8 bytes).
• Bit 10 UR (lack of character) is set to one when the scanner comes to transmit the corresponding block but finds the BV indicator at 1.
• Bit 11 MC (modem change) a change in the state of the modem wires occurred during the character transmission.
• Bit 12 EOT (end of transmission) is 1 when the LB indicator (last block) was 1 in the parameter field.

• l'indicateur EIRR et
• l'adresse de la ligne.

The IRR external interrupt request register contains:

• the EIRR indicator and
• the address of the line.

- BEGINNING OF A FRAME

• Le premier bloc 41-1 est rempli en fonction des paramètres d'initialisation par exemple caractère de remplissage (remp.)/ caractère de remplissage (remp.)/fanion.

The start of all SDLC frames is constructed by the command code as follows:

• The first block 41-1 is filled as a function of the initialization parameters, for example filling character (replenishment) / filling character (replenishment) / flag.

• . bloc valide indicateur BV à zéro
• . longueur de bloc indicateur BL indique le nombre de caractères de remplissage et de fanions dans le bloc
• . indicateur NZI à 1

The corresponding parameter field 43-1 is established:

• . valid block BV indicator at zero
• . BL block length indicates number of fill characters and flags in block
• . NZI indicator at 1

The second block, block 41-2 is filled with the address and control characters given in the parameters of the transmission command sent by the central processing units.

• . indicateur BV à zéro
• . indicateur BL

The corresponding parameter field 43-2 is established:

• . BV indicator to zero
• . BL indicator

- DATA WITHIN A FRAME

If the frame does not contain data, go to END OF FRAME.

The control code transfers sixteen bytes of data from the central processing units in the third and fourth blocks.

• . BV à zéro
• . BL indique le nombre de multiplets

The corresponding parameter fields are established:

• . BV at zero
• . BL indicates the number of bytes

The next two blocks are filled. Data fields parameters are established in the same way and this is done until all the blocks are full. If he stays still data to be transmitted, the IR indicator "interrupt request" is set to 1, at the end of every second block, block 41-2, 41-4, 41-6, 41-8. When the blocks are full of data ready to transmit, the command code initiates an asynchronous output operation "TRANSMIT OUTPUT" to the scanning device.

Then the scanning device performs an operation in cycle flight to obtain the parameter field associated with the block to be transmitted. The data bytes are then transferred from blocks to memory 11.

• effectue une vérification dans le champ d'état. L'indicateur BV a été mis à un par le dispositif de balayage,

• . la ligne identifiée dans le registre IRR est mise en file d'attente afin que seize octets de données supplémentaires puissent être amenés dans les deux blocs qui ont été vidés.
• . une fois que ces deux blocs sont de nouveau remplis, si les deux blocs suivants sont libres (BV=1) le code de commande provoque le transfert de seize octets pour les remplir afin de maintenir les blocs toujours remplis avec le maximum de données.

Once two blocks have been transmitted on the line, the scanner makes an interrupt request to the microprocessor. The result of the block transmission operation is put in the "status" field and replaces the previous parameters. Then the order code:

• performs a check in the status field. The BV indicator has been set to one by the scanner,

• . the line identified in the IRR register is queued so that sixteen bytes of additional data can be brought into the two blocks that have been emptied.
• . once these two blocks are filled again, if the next two blocks are free (BV = 1) the command code causes the transfer of sixteen bytes to fill them in order to keep the blocks always filled with the maximum amount of data.

- END OF FRAME

• - mettre indicateur SCRC (envoyer CRC) du dernier bloc rempli.
• - le bloc suivant est rempli avec des fanions et des caractères de remplissage suivant les paramètres du mode d'initialisation,
• - le champ paramètre correspondant est établi:
  • . BV = 0
  • . BL = nombre de fanions et de caractères de remplissage dans le bloc,
  • . NZI = 1
  • . TC = 10 si nécessaire ou_':
  • . indicateur EOM = 01, provoquera une interruption par le dispositif de balayage au microprocesseur une fois que le message a été transmis. Le code de commande en réponse prendra les actions nécessaires, soit renverra à l'unité de commande centrale (CCU) l'information d'état de fin de l'opération de transmission, soit attendra la réponse demandée de la ligne si la ligne était unidirectionnelle, (indicateur EOM=11), avant de demander une interruption à l'unité de commande (CCU) pour la ligne concernée.

The end of all SDLC messages is constructed by the command code as follows:

• - set SCRC indicator (send CRC) of the last block filled.
• - the next block is filled with flags and padding characters according to the parameters of the initialization mode,
• - the corresponding parameter field is established:
  • . BV = 0
  • . BL = number of flags and padding characters in the block,
  • . NZI = 1
  • . TC = 10 if necessary or _' :
  • . EOM indicator = 01, will cause an interruption by the scanning device to the microprocessor once the message has been transmitted. The command code in response will take the necessary actions, either return to the central control unit (CCU) the status information for the end of the transmission operation, or wait for the requested response from the line if the line was unidirectional, (EOM indicator = 11), before requesting an interruption to the control unit (CCU) for the line concerned.

• . Indicateur IR = 1
• . Changement sur les fils du modem
• . Manque de caractères
• . Fin de message
• . Expiration du temps
• . Erreur de matériel

INTERRUPTION requested by the scanning device.

• . IR indicator = 1
• . Change in modem wires
• . Lack of characters
• . End of message
• . Time expiration
• . Hardware error

With reference to FIG. 8, the operation for receiving the SDLC data will be described. The data is therefore received by a line 20-a and sent to memory 11 and then it must be transferred by cycle flight to a corresponding LIB memory area.

• - indicateur BV (1: bloc plein, 0: bloc vide) " IR mis à 1, tous les deux blocs
• - indicateur BL nombre d'octets que le dispositif de balayage placera dans chaque bloc.

The control parameters fields in the reception operation must be initialized with the following information:

• - BV indicator (1: full block, 0: empty block) "IR set to 1, every two blocks
• - indicator BL number of bytes that the scanning device will place in each block.

• Indicateur BV mis à 1 par le dispositif de balayage, mis à 0 par le code de commande.

The status field contains the following indicators:

• BV indicator set to 1 by the scanning device, set to 0 by the control code.

• - indique au code de commande que le bloc contient des données à traiter,
• - indiquer au dispositif de balayage que les données contenues dans ce bloc ne sont pas encore traitées, le dispositif de balayage ne peut plus amener des données, la condition "trop de caractères" est reportée, le reste des données reçues est chassé.

When it is 1:

• - indicates to the command code that the block contains data to be processed,
• - indicate to the scanning device that the data contained in this block is not yet processed, the scanning device can no longer bring data, the condition "too many characters" is reported, the rest of the data received is chased.

• - indique au code de commande qu'aucune donnée n'est encore disponible dans ce bloc.
• - indique au dispositif de balayage que le bloc est disponible pour recevoir les données.

When it is 0:

• - indicates to the command code that no data is yet available in this block.
• - indicates to the scanner that the block is available to receive the data.

OR indicator "too many characters" set to 1 when the scanner wants to fill a block and BV is still at 1.

• . BC nombre d'octets dans le bloc
• . FA fanion de fin a été détecté sur la ligne
• . FA O B (limite fanion mal cadré), un fanion mal cadré a été détecté sur la ligne
• . AB (abandon), la condition AB a été détectée sur la ligne
• . ID (état inactif), la condition ID a été détectée
• . V CRC (vérification CRC): le CRC calculé par le dispositif de balayage n'est pas correct
• . MC (changement modem): l'état des fils de contrôle a changé pour cette ligne pendant la réception.

IR indicator set to 1 if required by the parameter

• . BC number of bytes in the block
• . FA end flag was detected on the line
• . FA OB (badly framed flag limit), a badly framed flag was detected on the line
• . AB (abort), condition AB has been detected on the line
• . ID (inactive state), condition ID has been detected
• . V CRC (CRC check): the CRC calculated by the scanner is not correct
• . MC (modem change): the state of the control wires has changed for this line during reception.

BEGINNING OF A FRAME

The command code initiates an asynchronous reception operation to the scanner. After detection of a first flag by the scanning device, the characters which are not additional flags start filling the first available block per cycle flight.

DATA IN A FRAME

• . Les caractères suivants reçus dans le même bloc et dans les blocs suivants sont des données qui doivent être transférées à l'unité de traitement centrale par seize octets.
• . L'indicateur IR fera que le code de commande met en file d'attente la ligne identifiée dans le registre IRR, dans la file d'attente des opérations en vol de cycle afin d'envoyer ces données vers l'unité de commande centrale (CCU).
• . Lorsque deux blocs de données ont été transférés à l'unité de commande centrale, le code de commande remet à zéro l'indicateur BV de commande dans le champ paramètre associé. Ce bit est mis à 1 par le dispositif de balayage lorsque le bloc et le champ d'état sont remplis par les données et de l'information de commande.
• . Les deux blocs suivants sont remplis avec des données (BV=_l+mettre en file d'attente l'adresse de la ligne).

If the frame does not contain address and control character data only, go to END of frame. Otherwise the command code performs the following operations:

• . The following characters received in the same block and in the following blocks are data which must be transferred to the central processing unit by sixteen bytes.
• . The IR indicator will cause the command code to queue the line identified in the IRR register, in the queue for cycle flight operations in order to send this data to the central control unit ( CCU).
• . When two data blocks have been transferred to the central control unit, the command code resets the command BV indicator in the associated parameter field. This bit is set to 1 by the scanner when the block and the status field are filled with data and control information.
• . The next two blocks are filled with data (BV = _l + queue the line address).

END OF FRAME

At the end of a frame (Flag in the status block) once all the data has been sent, the end status information is sent to the central control unit (CCU) and then an interrupt is requested to the CCU control unit for the line concerned. At this time, the blocks may already contain other received frames awaiting other commands from the central control unit.

INTERRUPTION

• . A la détection d'une fin de trame (Fanion, abandon, état inactif),
• . A un changement d'état des fils du modem,
• . Trop de caractères,
• . Fin du temps,
• . Interruption demandée dans le champ paramètre,
• . Erreur de matériel.

The scanning device requests an interruption from the microprocessor:

• . Upon detection of an end of frame (Flag, abandonment, inactive state),
• . When the modem wires change state,
• . Too many characters,
• . End of time,
• . Interruption requested in the parameter field,
• . Hardware error.

Although the essential characteristics of the invention applied to a preferred embodiment of the invention have been described in the foregoing and represented in the drawings, it is obvious that a person skilled in the art can provide all of them. modifications of form or detail which he judges useful, without departing from the scope of said invention.

Claims (11)

1. Communication line adapter for a communications controller controlling the exchange of data between at least one central processing unit and terminals connected to said lines via a central control unit and a common bus to which at least one scanning device is attached by an input / output bus, characterized in that it comprises: first means comprising a microprocessor (1) and a control memory (2) for storing the microprocessor control code and data, second means (7) comprising a set of registers (8, 15) and a random access memory set (11), a memory position area of said set being assigned to each communication line for temporarily storing the information to be transmitted between the input / output bus (6) and the terminals, each zone can be addressed by an address selection device (13, 12), third interface means, comprising three exchange paths between the first and second means; a first asynchronous input-output path (9, 10, 8, 14) so that the microprocessor sends under control of the microcode, by write operations in the registers, initialization parameters in each of the zones of the set of memory allocated to a line, a second asynchronous path (14, 8, 18) for sending interrupt requests to the microprocessor via operations for reading registers and a third synchronous path comprising an exchange bus (16) connecting the control memory and the memory assembly (11) and a path for addressing (15, 17) of the memory (2) so that, under the control of the address selection device, the information is exchanged by cycle theft operations between the control memory and the memory assembly. 2. Adapter according to claim 1 characterized in that the initialization parameters characterize the communication lines. 3. Adapter according to claim 2 characterized in that, the initialization parameters characterizing the lines are sent to the memory assembly of the second means during an initialization phase, via four registers, addressed by the microprocessor by an address path (9), said microprocessor causing the writing, in the first register (8-1) of the address of the line to be characterized, in a second register (8-2) of the area of the set of memory assigned to this line, in a third register (8-3) of initialization parameters and data and in a fourth register (8-4) of exchange control data, the contents of the first and of the second register being used by the address selection device (13) to address the area of the memory assembly and the content of the third register being transferred by a link bus (14) to the position areas of the assembly from memory (11). 4. Adapter according to any one of the preceding claims, characterized in that the part of the control memory allocated to the storage of information is divided into memory areas (LIB), each information storage area being assigned to a communication line for temporarily storing the information passing between the central control unit and the memory assembly (11); an area of storage of control parameters and state information being associated with each information storage area. 5. Adapter according to claim 4 characterized in that each information storage area in the control memory is assigned to each line during the initialization phase, by the microprocessor by writing in the third register a starting address. 6. An adapter according to claim 4 or 5 characterized in that each information storage area is divided into blocks comprising eight bytes of information, a "parameter - status information" field being assigned to each block in the parameters and status information area. 7. Adapter according to claim 4, 5 or 6 characterized in that the control parameters for a transmission line contain information characterizing the information content in the associated block, and for a reception line they contain information characterizing the information to put in the associated block. 8. Adapter according to claim 7 characterized in that the state information will replace the parameters at the end of a transmission or reception operation to indicate how the said operation was carried out. 9. Adapter according to any one of the preceding claims, characterized in that the terminals are connected to the second scanning means by at least one line interface circuit to which are connected a number of lines, each interface circuit comprising drive circuits connected to the transmission lines and reception circuits connected to the reception lines, and a register associated with each line, the register associated with a line of transmission receiving the information to be transmitted from the memory (11) by an exchange bus (23) and the register associated with a reception line receiving the information from the reception circuit for transmitting it to the memory (11) by the bus d exchange (23). 10. An adapter according to claim 9 characterized in that the terminals are connected to the interface circuit by modems, the interface circuits comprising a "modem input" register (65) for receiving information on the control wires associated with the communication line coming from the modem and a modem-output register (66) for storing the information going on the control wires associated with the communication line going to the modem. 11. An adapter according to claim 10 characterized in that the registers "modem-input" and "modem-output" can be addressed by the microprocessor via the address selection device and external registers.

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