EP0029834A1

EP0029834A1 - General purpose data buffer

Info

Publication number: EP0029834A1
Application number: EP19800900984
Authority: EP
Inventors: Kenneth George William Ritchie
Original assignee: Burroughs Corp
Current assignee: Unisys Corp
Priority date: 1979-06-05
Filing date: 1980-12-15
Publication date: 1981-06-10
Also published as: WO1980002755A1

Abstract

Un tampon de donnees a usages multiples sert au stockage et au transfert de donnees entre une paire selectionnee parmi une pluralite de point d'acces de donnees suivant un mode selectionne parmi une pluralite de modes y compris un mode premier entre-premier sorti, un mode dernier entre premier sorti et un mode a acces selectif.A multipurpose data buffer is used for storage and transfer of data between a pair selected from a plurality of data access points according to a mode selected from a plurality of modes including a first in first out mode, a mode last between first out and a mode with selective access.

Description

GENERAL PURPOSE DATA BUFFER The present invention relates to a general purpose data storage device for use, in any selectable one of a plurality of operating modes, for the storage and transfer of data between any selectable two out of a plurality of data ports.

There is great emphasis in the data processing industry towards the use of multiple purpose components, not only to allow a data processor to perform the same number of functions with fewer parts, but also to allow communication with a plurality of peripheral devices in a plurality of modes via a single, multi purpose interface as opposed to a plurality of single purpose, device-specific interfaces, used until now with each particular type of peripheral device. The economic feasibility of mass production of semiconductor devices has made it particularly advantageous to provide a general purpose data storage device with flexible operation for use between two or more data ports.

According to the present invention, there is provided a device for storing data and transferring it between any selectable pair out of a plurality of data ports, said device comprising a control port, input selection means operable in response to a first external command applied to said control port to select a first one of said ports as a data input port, output selections means, operable in response to a second external command applied to said control port to select a second one of said ports as a data output port, a memory for retrievably storing a plurality of data characters, writing means, operable in response to a third external command applied to said control port to store in said memory a succession of data characters received at said first port, and reading means, operable in response to a fourth external command applied to said control port to retrieve said characters from said memory and present them, one by one to said second port, in any selectable one out of a plurality of serial orders.

In a preferred embodiment a general purpose data buffer employs a control logic circuit for selecting an access mode for a random access memory. The random access memory is coupled to two or more bidirectional data ports through a data input multiplexer and a data output register. The control logic circuit enables the random access memory to function as a first-in/first-out data buffer, a last-in/first-out stack memory, a variable-length shift register or a block-readable or writable random acces memory. The control logic circuit designates which of the data ports is an input port and which of the data ports is an output port. The general purpose data buffer further includes a length register for selecting the number of data characters being transferred at one time as well as read and write address pointers for selecting the locations with the random access memory for data transfer. Data transfer between the I/O ports and the random access memory is synchronized by a single buffer clock.

The present invention is further described, by way of an example, by the following description together with the appended drawings, in which:-

Figure 1 is a system block diagram of the general purpose data buffer.

Figure 2 is a logical embodiment of the control logic module of the general purpose data buffer.

Figure 3 is a logical embodiment of the random access comparator and random access multiplexer of the general purpose data buffer.

Figure 4 is a logical embodiment of the write address pointer register and status logic module of the general purpose data buffer of Figure 1.

Figure 5 is a detailed logical implementation of a write address register cell of the write address register of the general purpose data buffer of Figure 1. Figure 6 is a logical embodiment of the masked length selector, the length register, the length multiplexer, and the data input multiplexer of the general purpose data buffer of Figure 1.

Figure 7 is a detailed logical embodiment of a data input cell of the data input multiplexer of the general purpose data buffer of Figure 1.

Figure 8 is a logical embodiment of the read address pointer register of Figure 1.

Figure 9 is a detailed logical embodiment of a read address register cell of the read address pointer register of the general purpose data buffer of Figure 1.

Figures 10A and 10B are logical embodiments of the port A logic, port B logic, and output register of the general purpose data buffer of Figure 1.

Figure 11A is a detailed logical embodiment of a port

A cell in the port A logic of the general purpose data buffer of Figure 1. Figure 11B is a detailed logical embodiment of a port B cell employed in the port B logic of the general purpose data buffer of Figure 1.

Figure 11C is a detailed logical embodiment of an output register cell employed in the data output register of the general purpose data buffer of Figure 1.

Figure 12 is a block diagram of the random access memory of the general purpose data buffer of Figure 1. Figure 1 is a block diagram of the system which comprises the general purpose data buffer. The control logic module 11 receives inputs I∅-I2 which designate the particular accessing mode for the random access memory module. The control logic module 11 also receives a clock signal PH1, an output enable signal (OE), and a designation of which of the data ports coupled to the general purpose data buffer is to be treated as an input port and which is to be treated as an output port. This is labelled the direction signal (DIR). A stack-designation signal is also provided to the control logic module 11 when the random access memory is to be operated in the stack mode. These signals are all provided by some device such as a central processor which is external to the general purpose data buffer. The control logic module is used to generate all control signals within the circuit in accordance with the state of the instruction inputs I∅-I2 and the clock and other input signals. A memory module 13 is a standard random access memory which could comprise 256 9-bit words.

Figure 1 also illustrates, data input/output port A with its associated control logic 15 and data input/output port B with its associated control logic 17. For purposes of explanation, data port A and data port B are bidirectional in nature and will normally function in mutually opposite data-flow directions. This means that when port A 15 is the source of information for the random access module 13, then data port B 17 will be the destination of the data which will be supplied from the random access memory module 13.

The control logic module 11 is coupled to the write address pointer register 19 and the read address pointer register 21. These registers 19, 21 are 8-bit binary up/down counters with parallel-load facility. The write address pointer register 19 addresses the random access memory (RAM) module 13 when data is to be written into the memory, and the read address pointer register 21 addresses the RAM when data is being read from the memory. Both registers can be loaded with external data such as an address from either of the I/O ports 15, 17 or with the contents of the programmed length register 33 or the masked length register 37.

The write address pointer register 19 and the read address pointer register 21 are both coupled to the RAM address multiplexer 23. In conjunction with input clock PH2, the multiplexer 23 selects -either the contents of the write address pointer 19 or the read address pointer 21 as the address for the RAM 13. Thus the write address pointer

19 addresses the RAM 13 during the write phase of an instruction cycle, whereas the read address pointer register 21 addresses the RAM 13 during the read phase of an instruction cycle. The RAM address comparator 25 is employed to compare the contents of the write address pointer 19 with the contents of the read address pointer 21 and generate an output signal to the status logic module 27 whenever the two comparator addresses are equal. This would indicate that for a particular memory location in the RAM 13 a read and a write operation are being requested simultaneously. It can also indicate that a full or empty memory condition has been detected.

The status logic module 27 performs two separate functions. First, it detects when either the address in the write address pointer register 19 or the read address pointer register 21 is at its maximum. This would signify either an addressing error or memory overflow for the RAM 13. Second, if the general purpose data buffer is in the RAM, FIFO, or shift-register modes, the status logic module 27 generates an output signal when the contents of the write address pointer register 19 and the read address pointer register 21 are equal. If the general purpose data buffer is in the stack accessing mode an output is generated when the contents of the read address pointer register 21 equals all high values. The RAM address multiplexer 23 is coupled to the RAM 13 by RAM address bus 24. This enables memory locations in RAM 13 selected by the write address pointer register 19 or read address pointer register 21 to- be accessed for either data input or data output. The data input multiplexer 29 is coupled to both I/O port A 15 and I/O port B 17. The data input multiplexer 29 selects the data input to the RAM 13 and to the length register 33 according to the direction input (DIR) to the control logic module 11. As will be subsequently explained, when DIR equals 0 the input in this particular embodiment is from I/O port B, and when DIR is equal to 1 data port A is selected for input.

Data output register 31 is a nine-bit latch which enables the output from RAM 13 to propagate to its selected output ports 15,.17 when the clock signal PH2 is high.

The data output register 31 will not change its state when clock signal PH2 is low.

As was previously mentioned, I/O port A 15 and I/O port B 17 are coupled to the data output register 31. The I/O port A and B represent two of a plurality of tri-state output cells which are controlled by the direction signal (DIR) and output enable signal (OE) supplied to the control logic module 11. When OE is in a low value, the I/O ports are output-disabled by being held in a high impedance state. When OE is high and DIR is low, data port B is held in its high impedance state and may be used as the data input port to the general purpose buffer. For these values of DIR and OE, data port A is enabled as the output port of the general purpose data buffer. When OE is high and DIR is also high, data port A is held in its high impedance state and may be used as the data input port for the RAM 13 while data port B will be enabled as the output port.

The masked length register 37 is a programmable register which will designate the length of the general purpose buffer when power-on occurs. This length is set a the manufacturing stage for the general purpose data buffer and can be changed from this value by reprogramming. The length register 33 is loaded with data, from either port A or port B, which designates the load length when the general purpose data buffer is in either the FIFO or shift register mode. The length register 33 can be set to any length from one to the maximum storage length of the RAM 13. The length multiplexer 35 is coupled to both the length register 33 and the masked length register 37. This multiplexer is employed to select either the masked length or the programmed length as input to the write address pointer 19 or the read address pointer 21. When power is first supplied to the general purpose buffer, the masked length is selected. When a load length instruction is supplied from either data port A or data port B, the multiplexer switches to select the program length from register 33. The multiplexer will remain in this state until a further power-on signal reselects the masked length register 37.

To enahance the understanding of the preferred embodiment of the general purpose data buffer, the following mnemonics list has been created for consideration in conjunction with the logic circuit diagrams hereinafter discussed. The left column of the table shows the mnemonics as they appear in the logic diagrams, and the right side of the table is a short explanation of the meaning of the mnemonic.

GENERAL DATA BUFFER LSI - MNEMONICS

I∅, I1, I2 INSTRUCTION CODE INPUTS DIR DIRECTION OF DATA FLOW OE OUTPUT ENABLE PHI CLOCK PHASE 1 PH2 CLOCK PHASE 2

LD LOAD ADDRESS POINTERS

LPLR LOAD LENGTH REGISTER LLP PULSE TO LOAD LENGTH REGISTER RWT WRITE TO RAM RAMWT RAM WRITE PULSE STKS STACK SET STKR STACK RESET STCK STACK MODE (i.e. become a last in first out register)

INCW INCREMENT WRITE ADDRESS POINTER INCR INCREMENT READ ADDRESS POINTER RAX READ ADDRESS "ALL ONES" WAX WRITE ADDRESS "ALL ONES" WRST WRITE ADDRESS POINTER RESET RRST READ ADDRESS POINTER RESET PUSH PUSH STACK (i.e. put data into stack) POP POP STACK (i.e. remove data from stack)

EQUL ADDRESS POINTERS EQUAL FLAG STATUS FLAG

RAMAD∅ - RAMAD7 RAM ADDRESS LINES

DI∅ - DI7 DATA INPUTS TO ADDRESS POINTERS RAMIO∅ - RAMI08 DATA I/O TO RAM

PL∅ - PL7 PROGRAMMED LENGTH REGISTER CELLS

ML∅ - ML7 MASKED LENGTH CELLS

PLS PROGRAMMED LENGTH SELECT

MLS MASKED LENGTH SELECT LEN∅ - LEN7 LENGTH CODE CELLS

OR∅ - OR8 OUTPUT REGISTER CELLS

PA∅ - PA8 PORT A CELLS PB∅ - PB8 PORT B CELLS

ATB DIRECTION A TO B WITH OUTPUT ENABLED BTA DIRECTION B TO A WITH OUTPUT ENABLED

WAA∅- WAA7 TOGGLE (DOWN COUNT) TO WRITE ADDRESS POINTER CELLS

WAB∅ - WAB7 TOGGLE (UP COUNT) TO WRITE ADDRESS POINTER CELLS WAC∅ - WAC7 RESET LENGTH TO WRITE ADDRESS POINTER

CELLS

WAD∅ - WAD7 RESET TO ZERO TO WRITE ADDRESS POINTER

CELLS

WAE∅ - WAE7 SET DATA INPUT TO WRITE ADDRESS POINTER

CELLS

WAF∅ - WAF7 RESET DATA INPUT TO WRITE ADDRESS POINTER

CELLS

WAG∅ - WAG7 CLOCK PULSE TO WRITE ADDRESS POINTER

CELLS

WAS∅ - WAS7 SET WRITE ADDRESS POINTER CELLS WAR∅ - WAR7 RESET WRITE ADDRESS POINTER CELLS WA∅ - WA7 WRITE ADDRESS POINTER CELL OUTPUTS

RAA∅ - RAA7 TOGGLE (DOWN COUNT) TO READ ADDRESS

POINTER CELLS

RAB∅ - RAB TOGGLE (UP COUNT) TO READ ADDRESS

POINTER CELLS

RAC∅ - RAC7 RESET DATA INPUT TO READ ADDRESS POINTER

CELLS

RAD∅ - RAD7 SET TO "ONE" TO READ ADDRESS POINTER CELLS

RAE∅ - RAE7 RESET LENGTH TO READ ADDRESS POINTER CELLS

RAF∅ - RAF7 SET DATA INPUT TO READ ADDRESS POINTER CELLS

RAG∅ - RAG7 CLOCK PULSE TO READ ADDRESS POINTER CELLS

RAS∅ - RAS7 SET READ ADDRESS POINTER CELLS

RAR∅ - RAR7 RESET READ ADDRESS POINTER CELLS The following table sets forth the logic equations for the general purpose data buffer of the instant invention.

The logical operation AND is signified by a "." and the logical function OR is signified by a "+". The NOT logical operation is signified by the superscription of a mnemonic name. The logic equations are grouped according to the module in which the equation is implemented. The logic equations and the mnemonic list should be consulted during the consideration of the logic diagrams which will be explained in later sections of the specification.

The general purpose data buffer receives external control inputs I∅, I1 , and I2 and an external clock PH1.The Control logic module I1 processes these inputs to produce internal control signals which determine the buffer mode of operations. The following table sets forth the buffer operation selected for the various configurations of the instruction codes received on I∅ through I2.

TABLE 1 : BUFFER INSTRUCTION CODES

(Or just "prefixed" (.) )

BUFFER OPERATION INSTRUCTION CODE

I2 I1 I∅

IDLE 0 0 0

WRITE 0 1 0

SHIFT 0 1 1

CLEAR 1 0 0

STACK INITIALISE 1 0 1

LOAD LENGTH 1 1 0

RECIRCULATE 1 1 1

When the buffer is in the IDLE mode as indicated above, all internal operations within the general purpose data buffer are inhibited and the clock input will not effect any of the buffer's logic devices.

The READ operation causes an instruction cycle which is dependent on which previous initialization instruction has been executed in the buffer. If the buffer has been initialized by a CLEAR or LOAD LENGTH instruction (STACK flip-flop reset), read address pointer register 21 will be incremented during the write phase and output register 31 will be loaded with the contents of the RAM location addressed by the read address register during the read phase. If the contents of write address pointer register

19 and read address pointer register 21 are equal at the end of the READ instruction cycle, the EMPTY flag will be set. If the buffer has been initialized by a STACK

INITIALISE instruction (STACK flip-flop set), the read address pointer register will be decremented during the write phase, the write address pointer register will be decremented during the read phase, and the contents of the addressed RAM location will be loaded into the output register 31.

Operation during the WRITE cycle is also dependent on which previous initialization instruction has been executed. If the general purpose data buffer has been initialized by a CLEAR or a LOAD LENGTH instruction (the STACK flip-flop reset), the data from the input port, as defined by the state of DIR, will be loaded into the RAM location addressed by write address pointer register 19 during the write phase. The write address pointer register will be incremented during the read phase. If the contents of the write address pointer register 19 and the read address pointer register 21 are equal at the end of a WRITE cycle, the FULL flag in status logic module 27 will be set. If the buffer has been initialized by a STACK INITIALISE instruction, the buffer will operate exactly as for the SHIFT instruction which will be explained next.

The SHIFT instruction is a combination of the READ and WRITE instructions previously described. During the write phase, the data from the input port (as defined by the state of DIR) will be loaded into the RAM location addressed by the write address pointer register 19, and the read address pointer register 21 will be incremented. During the read phase, the contents of the location addressed by the read address pointer register 21 will be loaded into the output register 31, and the write address pointer register will be incremented.

The CLEAR instruction causes read address pointer register 21 and write address pointer register 19 to be set to the value of the data currently at the DIR-defined input port. The EMPTY flag is set, and both the FULL flag and the STACK flip-flop are reset. The resetting of the STACK flip-flop affects subsequent READ and WRITE instructions as previously explained. During the CLEAR instruction, the contents of the location addressed by read address pointer register 21 will be loaded into the output register. During the STACK INITIALIZE instruction, the write address pointer register will be set to "all zeros", and the read address pointer register will be set to "all ones". The STACK flip-flop will be set.

The LOAD LENGTH instruction causes read address pointer register 21, write address pointer register 19, and length register 33 to be loaded with the value of the data at the DIR-defined input port.

The EMPTY flag will be set, the FULL flag will be reset, and the STACK flip-flop will be reset. A flip- flop within the general purpose data buffer will also be set to indicate that the buffer length has been set externally.

The RECIRCULATE instruction is analogous to the SHIFT instruction except that there is no loading of RAM 13. The read address pointer register will be incremented during the write phase. During the read phase, the write address pointer register will be incremented while output register 31 will be loaded with the contents of the location addressed by the read address pointer register. Figure 2 is a logic embodiment of control logic module 11 of Figure 1. Load address pointers - signal LΔ is generated and supplied to the write address pointer register by combining I∅ and through inverter 103 and NOR gate 109. is generated by inverting LD with inverter 119. The stack reset signal STKR is generated by NOR gate 111 from I∅ and . The stack set signal STKS is the output of NOR gate 113 which combines I1, and 2 The write to RAM signal RWT is the output of AND gate 115. An input to AND gate 115 is the external clock signal PH1 and the output of NOR gate 107 which combines 12 and . A POP signal for reading from the RAM when it is in the stack mode is generated from NOR gate 117 combining I2, I1 and NSTCK. The POP signal is provided as an output of the control circuit module I1 to the read address pointer register. POP is inverted by inverter 127 to generate NPOP which is supplied to the read and write address-pointer registers. The stack mode for the general purpose data buffer is selected by a flip-flop which is formed by NOR gates 131 and 133. This is the STACK flip-flop referred to previously. The output STCK supplies an input to NOR- gate 139 where it is combined with and The STCK -signal is also provided to the status logic module and is ^'an input to NOR gates 137 and 141. NOR gate 137 combines STCK with and 12 to generate an output which is an input to NOR gate 145. NOR gate 141 combines STCK, , and 12 to generate an input for NOR gate 147. NOR gate 143 generates the PUSH signal which, when the general purpose data buffer is operating in the stack mode, designates that a new entry is to be placed into the stack. The PUSH signal is combined in NOR gate 145 with the output of NOR gate 137 and NOR gate 139 to generate a signal which designates an increment in the read address pointer register. Similarly, the PUSH signal is combined by NOR gate 147 with the output of NOR gates 141 and 139 to generate a signal which increments the write address pointer. NOR gate 129 receives I∅ , and and then generates the LPLR signal which initiates a load of the length register from one of the data ports. The RAMWT signal is generated by inverter 135 and propagated to the data input multiplexer to signal a RAM write pulse. Figure 3 presents logical embodiments for RAM address comparator 25 and RAM address multiplexer 23 as shown in Figure 1. The components which make up the RAM address multiplexer are shown within the dashed portion of Figure 3 designated by the numeral 23, and the address comparator is shown within the box labelled 25. In RAM address multiplexer 23, a plurality of logic gates are provided in one-to-one correspondence with the addressing lines to the random access memory. The logic gates receive as inputs RAi and from the read address pointe register and WAi and from the write address pointer register. Referring to the gates 201, 203, 205, and 207 and inverter 209, an address for random access memory 13 is generated whenever PH2 (the inverse of external clock PH1) and RA∅ are both on or whenever PH2 and WA∅ are simultaneously on. The address in the former case is propagated out as RAMAD∅ and in the latter case as RAMAD∅. There are eight groups of these gates within random access multiplexer 23 for generating RAMAD∅-RAMAD7 or These addresses are the result of outputs from the write address pointer register 19 and read address pointer register 21.

As previously mentioned, random address comparator 25 is employed for two purposes: first, to determine whether an attempt is being made to simultaneously access a particular memory location in random access memory 13 for both a read and a write operation, and second, to detect a full or empty memory condition. Gates 211 and 213, together with inverter 215, are coupled to NOR gate 217. The gates 211, 213, and 215 will propagate an EQUL∅ signal if both WA∅ and RA∅ are high or and R are high There are again eight groups of these gates connected to NOR gate 217, and a EQUL signal is generated if all of the inputs to NOR gate 217 are low. This would indicate that there is complete identity between the address being requested for a read operation and the address being requested for a write operation. The EQUL signal is supplied to the status logic module 27 for generating appropriate output indication flags as previously explained.

The write address pointer register and the status logic module are shown in Figure 4. The status logic module is enclosed within the dashed portion labeled 27 and generates the FLAG signal under certain conditions. One of the conditions is when the buffer is in the STACK mode and all of the bits of the address of a read instruction are high. The detection of this condition begins at NOR gate 273 where the bits RA7 of the read address for the random access memory are shown as inputs. The output of NOR gate 273 is RAX which is supplied to the gate 283. The STCK signal is routed to gate 283 from control logic module 11 and, if RAX and STCK are simultaneously high, a signal is generated which is inverted by inverter 287 to result in the FLAG signal. The other condition in which the FLAG signal is generated is that in which the buffer is in any mode other than STACK and a read and write are simultaneously attempted on the same memory location. To produce the FLAG signal in this situation, gate 285 first combines NSTCK from control module 11 with EQUL (indicating that the read and write addresses are the same from address comparator 25. is then generated and supplied to inverter 287 for conversion into the desired signal. The RAX signal from NOR gate 273 is also supplied to inverter 275 and then to NOR gate 279 where it is combined with INCR from control logic module 11. The result of the combination by the NOR gate 279 is RRST or read address pointer reset. This is generated when an increment of the read address pointer is being requested simultaneously with the read address being at its maximum value. The RAM address which is requested for a write operation is likewise examined to determine whether it is all ones. This is accomplished by

NOR gate 271 which combines to generate a WAX signal indicating that all of the address bits are high. WAX is supplied to write address pointer register 19 of

Figure 4 through inverter 277. The resetting is combined by NOR gate 281 with to generate a WRST signal. As with the read increment condition, this resulting write address poin-ter reset signal WRST indicates the simultaneous occurrence of the maximum address value in the address pointer for the write instruction together with a control logic module request for an increase in the write address.

The write address pointer register is designated by block 19 in Figure 4. The write address pointer register comprises eight individual circuit modules, each of which generate respective WA or outputs.

One such circuit module is illustrated by the logic device 301, AND gates 303 and 307, and NOR gates 305 and

309. The circuit element 301 is schematically illustrated in Figure 5 which can be referred to for further details.

The "A" input of the module 301 indicates a toggle (down count) to the write address pointer cell. In the case of

WA∅, this down count input is the POP signal from the control logic module.

In the remaining modules WRi ( 1 ≤ i ≤ 7 ) , the toggle signal is the result of the combination, via a NOR gate, of the NPOP signal from the control logic module together with the signal WAj (0≤ j < i). [grate: no "-" before "i" .

The "B" input to logic element 301 is the output of a combination in NOR gate 309 of the signal from the control logic module and WAX from the status logic module. For the seven remaining modules WAi (1 ≤ j ≤ 7), the signals (0≤ j < i) are also included in the NOR gate combination.

The "C" input to each of the logic modules is used to reset the given write address pointer cell. The "C" input is generated from an AND gate (303 in the case of. WAø) which receives a WRST signal from the status module and an LENi signal from the data input multiplexer and length register. The "D" input to all of the modules is STKS from the control logic module. By simultaneously resetting each of the write address pointer cells to zero, STKS thus resets the entire write address to zero. The "E" input to the logic cell 301 is the output of NOR gate 305 and sets the data input to the write address pointer cell. This is generated by NOR gate 305 combining the and signals. The signal is generated by DI/LR∅ in the data input multiplexer. The "F" input to WAO 301 is generated by AND gate 307 which combines and LD. The LD signal causes a load of the address pointer register and the "F" input to cell 301 corresponds to the "C" input of RA0 in the read address pointer register.

The "G" input to the address cell 301 is the clock signal PH2. The output of register cell 301 is either WA1 or which reflect the address within the RAM which is being accessed for a memory write.

Figure 5 is a logical implementation of the cells in the write address pointer register labeled 301 in Figure 4. One skilled in the art would be able to follow the input signals "A" through "G" previously explained in the module 301 to see how the outputs WA. and WAi are generated. It is felt that a more further explanation of the cell as shown in Figure 5 is not required.

Figure 6 shows a logical embodiment of the mask length selector 37 the length register 33, the length multiplexer 35 and the data input multiplexer 29. The masked length comprises the switches 600-607 depicted in the portion of Figure 6 labeled 37. The switches enable the masked length to be selected from one to eight bits long by placing the programmable switch such that Vcc is connected to the switch terminal rather than ground.

In Figure 6 the masked length is shown to be eight bits long. The length multiplexer is indicated by the dashed portion 35 of Figure 6. The length multiplexer comprises eight sets of gates such as 611 and 613 which form length code cells LENO- -LEN7 . These length cells are suitably connected to the write address pointer register as previously explained. The cells are set to a high condition when the switches in the mask length register 37 are appropriately thrown or there is an output from the program length register 33. These outputs are labeled PLi (0 ≤i≤7) and are coupled by switches to the output from the flip-flop formed from NOR gates 615 and 617 to generate LENi. The NOR gate 615 has as one input the power ON signal and the other input is the output of NOR gate 617. NOR gate 617 has as one input the output of NOR gate 615 and the LLP signal (pulsed low length register). LLP is generated by AND gate 619 which combines the PHI clock signal with LPLR from the control module 11.

The logical elements embodied within the hatched portion labeled 33 comprise both the data input multiplexer and the masked length register. The DIR is an external signal which designates which data port is supplying the data and which is to receive the data. DIR is supplied as an input to each of the register modules 621 shown in Figure 6. Another input to the modules is the complement which is supplied by inverter 631. The DIR and signals respectively comprise the C and D inputs to the register cells 621. The B input is RAMWT which is a RAM write pulse from the control logic module 11. The F input to the register cells 621 comprises the LLP signal previous defined as the pulse to low length register and the G input to the memory cells comprises the LLP signal from inverter 608. The B input to the register cell 621 is coupled to port A such that the B input to DI/LRi (0≤i≤7) comprises the PAi signal from port A. Similarly, the E input to DI/LR (0≤i≤7 ) is coupled to port B and is the PBi signal.

Figure 7 shows the logical circuit elements which are employed to fabricate each of the register cells 621

One skilled in the art can consider this embodiment of the register cell along with the previously provided logic equations for the general data buffer to determine how the outputs from the cells are generated. The DTi (0≤i≤7) designates a data input to cell I within the address pointer registers, RAMOi (0≤i≤7) is the data path to random access memory 13. The (0≤i≤7) is also supplied as a data input to the RAM 13 and the PLi signal (0≤i≤7) is, as previously mentioned an input to the length register 35. Finally the NRAMI08 and the RAMI08 signals are generated by logic gates 641 and 643 and inverters 645-651.

Figure 8 is a logical embodiment of the read address pointer register designated 21 in Figure 1. The read address pointer register is an 8-bit binary up/down counter with parallel load facilities. The read address pointer register addresses the RAM when data is being read inputs are generated by a series of AND gates 807 which generate the RAE_i signals (0≤i≤7) by combining the read address pointer reset signal RRST from the status logic module with the length signal LEN_i from the length multiplexer of Figure 6. The F input to the circuit modules RA_i is the RAF_i signal defined as LD.DI_i (0≤i≤7). This signal is also supplied to the E inputs of the circuit modules WA_i in the previously explained write address pointer register. The G input to the circuit modules RA_i is the signal RAG_i and is equal to the PH1 clock signal.

Figure 9 is an implementation of each of the read address register cells RA_i (0≤i≤7) which combines the read address pointer register. The inputs A though G to each of the register cells have been previously explained in conjunction with Figure A and it is felt that one skilled

RA. in the art would realise how the outputs RA. for the read address register cells are generated as a function of the input signals.

Figures 10A and 10B show the logical embodiment of the data output register 31, the port A logic 15 and port B logic 17 as shown in block diagram form in Figure 1. The port A logic comprises a plurality of port A cells 1001 which are designated PTA_i (0≤i≤7) . Similarly, the port B 10 logic 17 comprises a plurality of port B cells 1005 designated PTB_i (0≤i≤7). The output register comprises a plurality of output register cells 1003 designated OR_i (0≤i≤7). The exact logical implementation of the port A cells 1001, the port B cells 1005 and the output register from the memory. The read address pointer register can be loaded with external data from either port A or port B or with contents of the program length register or the mask length. The data from either port A or port B would normally comprise an address within the RAM.

Referring to Figure 8, the read address pointer register comprises a plurality of circuit modules RA0-RA7.

The output of the read address pointer registers are an address within the RAM designated RA0-RA7 or The read address pointer register receives the NPOP and POP signals from the control logic module 11. The POP signal is supplied to the A input of circuit module RA0 whose Q output is connected to the signal line RA0. The remaining A inputs of the circuit modules RA_i (1≤i≤7) receive the logical NOR of RA_i (0≤j≤i) and NPOP. The Q outputs for the circuit modules RA0-RA7 are all connected to an associated signal line RA0-RA7, respectively. The A input to the circuit module RA. (0≤i≤7) is given by the logic equation RAAi=POP · RAO · RA1 · · · RA (I-1) (0≤i≤7). The B input to the circuit modules RA. is the RAB. signal whose logic equation is INCR·RAX·RAO · RA1 · · · RA(i-1) for 0≤i≤7.

The RAB_i signals are generated by the NOR gates 805 associated with the circuit modules. The C input to the circuit modules RA. is defined by the signal RAC_i which equals LD;DI_i (0≤i≤7). The DI_i signal is provided from the data input multiplexer previously described in Figure 6. The D input to the circuit modules RA_i comprises the stack set signal STKS from the control logic module 11. The E cells 1003 are respectively shown in Figures 11A, 11B and

11C.

Referring to the port A 10 logic 15 as shown in

Figures 10A and 10B, the port A cell PTA _i each receive inputs A through F and generate an output PA. (0≤i≤8). The A input is connected to the voltage source V and the B input is the BTA signal signifying the data flow direction as being from port B to port A. BTA is generated by NOR gate 1001 which combines the direction signal DIR and the complement of the output enable signal OE as provided from inverter 1009. The C inputs to the port A cells PTA_i correspond to the OR_i outputs of the output registers OR_i. The D input is the BTA signal inverted by inverter 1001 and the E input is the OR_i signal which is the Q output of the output register cell OR_i (0≤i≤7). The F inputs of all the port A cells are tied to ground.

The port B logic is designated as 17 in Figures 10A and 10B. The operation of the individual circuit modules 1005 corresponding to PTB0-PTB8 is very similar to the operation of the previously described circuit modules PTA0-PTA8. The circuit modules generate an output PBI (0≤i≤8) which as previously explained are inputs to the circuit modules DI/LRi in the data input multiplexer. The A inputs of all the circuit modules are tied to the voltage source V_cc and the B inputs are the directional inputs ATB translated as A to B . This means that the A port is on input and the B port is on output when the ATB is high. The ATB signal is generated by NOR gate 1021 which combines the OE signal from inverter 1009 and the

NDIR signal from the control logic module. The C inputs to the circuit modules PTBi are identical to the C inputs to the circuit modules PTA_i. This signal is the signal from the output register circuit modules ORi. The D input correspond to the inverse of the ATB signal generated by inverter 1023. The E inputs to the circuit modules are identical to the E inputs to the port A circuit modules OR_i generated by the Q output of the output register modules OR_i. The F inputs are tied to ground.

The output register is identified as 31 in Figures 10A and 10B. The logical implementation of the output register circuit modules OR_i is given in Figure 11C and is easily understood by one skilled in the art. The output circuit modules OR_i generate signals OR_i and O (0≤i≤8) which as previously explained are inputs to the port A and port B circuit modules. The A input to the output register circuit modules is the signal RAMIOi from the dat input multiplexer. The B inputs all equal the PH2 clock signal and the C inputs are the inverse of the PH2 clock signal generated by inverter gate 1025.

Figure 12 schematically shows a suitable random access memory for use with the disclosed general purpose data buffer. While the RAM memory shown in Figure 12 is 256 9-bit words, one skilled in the art would understand that larger and smaller memories could be employed. The inputs and output data from the random access memory comprise the signals NRAMIOO-NRAMI08 and RAMIO0-RAMIO8.

These signals are generated by the data input multiplexer as exhibited in Figure 6. The address lines to the RAM comprise RAMAD0-RAMAD7 and R from the RAM address multiplexer shown in Figure 3.

The following is a summary of the operation of the general purpose data buffer in each of its accessing modes i.e. RAM, FIFO, STACK and shift register.

When the general purpose data buffer as being operated as a block writable random access memory, the instruction inputs 10-12 are initially set to CLEAR. The address to be written into within the RAM is provided to the write address pointer register and the clock cycle is generated to load the address into the write address pointer register. Next, the instruction input to the control logic module is set to WRITE and the data input flag is set. A clock cycle is generated to load the data bite into the RAM from whichever of the data ports has been selected by DIR to be an input port. The data input is continuously set in the clock cycles for loading the data are generated for many bites of data as are desired to be loaded into the random access memory. If a block of data is to be read from the RAM the instruction inputs to the control logic module are set to CLEAR and the address is provided by the data port which DIR indicates is to receive the data from the RAM. A clock cycle is generated to load the address into the read address pointer register and the instruction input to the control logic module is set to READ. Another clock cycle is generated to read the data from the RAM and transfer to the output register and to the output data port.

Successive clock cycles are generated for each bite of data which is to be read from the RAM, When the general purpose data buffer is operated as a first-in-first-out buffer the instruction inputs I0-I2 to the control logic module are set to CLEAR. A clock cycle is generated to clear the FIFO buffer and the instruction input 10-12 is set to WRITE. The data input is set and a clock cycle is generated to load the data bite into the buffer which is being operated in the FIFO_ module. The data bite is supplied by the data port which DIR has selected as the input port. When data is to be read from the FIFO buffer the instruction inputs to the control logic module are set to READ and clock cycles are generated to transfer data characters from the RAM to the output register and the output data port.

When the general purpose data buffer is operated in the shift register mode the instruction inputs 10, 12 are set to LOAD LENGTH. The data input from the port. selected by DIR is set to equal the 2's complement of the required length and a clock cycle is generated to set tha length into the length register 33. The data inputs I0-I2 are set to SHIFT and a data input is set from the port supplying the data as indicated by DIR. A clock cycle is generated to shift the information in the RAM (which is being operated in the shift register mode) one position and successive clock cycles may be generated to further shift the information. To recirculate the information in the shift register the inputs I0-I2 are set to recirculate and clock cycles are successively generated to recirculate the information. In the stack mode 'the instruction inputs I0-I2 to the control logic module are set to INITIALISE and a clock cycle is generated. The instruction inputs are then set to WRITE and the data inputs are supplied by the input ports selected by DIR. End clock cycles equal in number to the number of stages in the stack, are generated to push or load data from the input data port. When data is to be popped or read from the stack the instruction inputs are set to READ and clock pulses are generated for each position within the stack that the information is to be popped. When a push or write instruction is executed the data from the input port will be loaded into the top location in the stack and the data characters already in the stack will be pushed down one location in the RAM. If 256 pushes have been executed FLAG will be set. When a pop or read is executed all data characters will be moved up one position in the stack and the character ahead of the stack will be discarded or transferred to the output data port as selected by DIR. When all the characters have been read from the stack the FLAG will be set. The forgoing describes the acritecture and operation of a general purpose data buffer for the temporary storage of data transferred between two or more bidirectional data ports sharing the general purpose data buffer. The general purpose data buffer is selectably operable in a random access mode, by a first-in-first-out upper mode, shift register mode and a stack accessing mode. A practical application of such a general purpose data buffer is within peripheral controllers to replace conventional data storage devices with this multi-mode flexible buffer. The general purpose data buffer as disclosed incorporates a control logic module for selecting the mode of buffer operation as well as enabling the output and selecting a data port for input and a data port for output. A random access memory is employed for temporarily storing the data to be transferred to and from the selective ports. The read address pointer register and a right address pointer register are coupled with a random access comparator and a random access multiplexer for accessing selected locations in the random access memory. Certain accessing and storing conditions are detected by a status logic module and flags are according set. The random access memory receives data from a selected data port through data input multiplexer and transfers data to a selected port through a data output register. Each data port has its appropriate data module for controlling the transfer of data between the port and random access memory. The general purpose data buffer further includes a length register, a max-length selector and a length multiplexer for establishing the length of the data information to be transferred to or from the random access memory.

Claims

WHAT I CLAIM IS : -

1. A device for storing data and transferring it between any selectable pair out of a plurality of data ports, said device comprising a control port, input selection means operable in response to a first external command applied to said control port to select a first one of said ports as a data input port, output selection means, operable in response to a second external command applied to said control port to select a second one of said ports as a data output port, a memory for retrievably storing a plurality of data characters, writing means, operable in response to a third external command applied to said control port to store in said memory, a succession of data characters received at said first port, and reading means, operable in response to a fourth external command applied to said control port to retrieve said characters from said memory and present them, one by one to said second port, in any selectable one out of a plurality of serial orders.

2. A device according to claim 1 comprising monitoring means for monitoring the difference between the number of characters stored in said memory by said writing means and the number of characters retrieved from said memory by said reading means and operable to provide, to said control port, first indication when said difference is equal to a selectable number and second indication when said difference is zero.

3. A device according to Claim 2 comprising assimil ation means operable to receive a number indicating character from said first port and to provide said number to said monitoring means as said selectable number.

4. A device according to Claim 3 wherein said memory comprises a plurality of character storage locations said assimilation means is operable to provide said number to said writing means and said reading means, and said writing means and said reading means are operable in response to said number to deposit characters into or retrieve characters from a common set of said character storage locations having a population equal to said number.

5. A device according to Claim 4 wherein said writing means and said reading means are operable, in response to said number, to interact with a selectable one out of said plurality of character storage locations, which one being determined by said number.

6. A device according to any of the preceding Claim wherein said plurality of serial orders includes the retrieval said data characters from said memory in the same order as the order of their storage, and the retrieval of said characters from said memory in the reverse order to the order of their storage.

7. A device according to claim 4 or 5, or claim 6 when dependent on claim 4, wherein said storage locations are individually addressible responsively to an address signal applied to sa.id memory, said reading means comprises read address generating means for generating a read address signal for addressing a particular location for the retrieval of a data character therefrom, said writing means comprises write address generating means for generating a write address signal for addressing the same or another particular location for the deposition of a data character therein, and wherein there is provided signal selection means, operable in responsive to a selection signal from said control port to provide either said write address signal or said read address signal to said memory.

8. A device according to any of the preceding claims wherein said input selection means comprises an input signal selector for receiving signals from all of said plurality of data ports and operable to provide in response to an input selection signal from said control port, as an output, the signal received from a selectable one out of said plurality of data ports.

9. A device according to any of the preceding claims wherein said output selection means comprises an output signal selector, coupled to all of said plurality of data ports and operable to provide, in response to an output selection signal from said control port,; to a selectable one out of said plurality of data ports, the signal received on an input.

10. A device according to claim 7 or claim 8 or 9 when dependent on claim 7, wherein said read address generating means comprises one or more selectably incrementable or decrementable resettable read-address counters.

11. A device according to claim 7, or claim 8 or 9 when dependent on claim 7, or claim 10, wherein said write address generating means comprises one or more selectably incrementable or decrementable resettable write-address counters.

12. A device according to claim 11 when dependent upon claim 2 wherein said monitoring means comprises a numerical comparator for comparing the output of said read address counter or counters with the output of said write address counter or counters.

13. A device according to claim 3, 4, 5, 7 or 10, or claim 6 when dependent upon claim 3, or claim 8 or claim 9 when dependent upon claim 3 , wherein said assimilation means comprises latch means operable in response to a latch signal from said control port to acquire and hold the character presented at said first port.

14. A device substantially as herein described with reference to the accompanying drawings.