EP0026588B1

EP0026588B1 - Zero-crossing comparators with threshold validation

Info

Publication number: EP0026588B1
Application number: EP80303119A
Authority: EP
Inventors: Robert Keith Portway Galpin
Original assignee: Plessey Overseas Ltd
Current assignee: Plessey Overseas Ltd
Priority date: 1979-09-14
Filing date: 1980-09-05
Publication date: 1985-04-17
Also published as: KR830003988A; CA1157523A; IE801922L; NZ195212A; IE51652B1; DE3070515D1; ZA805412B; HK77685A; EP0026588A1; GB2059725A; KR830002630B1; US4352999A; JPS5647126A; NO148657C; SG30085G; ATE12865T1; PT71785A; ES8105532A1; PT71785B; GB2059725B

Abstract

In carrier and timing recovery systems for high performance data modems it is essential to employ threshold comparators and to be able to determine accurately zero-crossing instants. The circuit of the invention comprises a comparator with feedback which produces a positive transition of the comparator output in response to the negative zero-crossing transition of the input signal on condition that the previous half-cycle of the input signal has exceeded the positive reference threshold. In a practical arrangement two comparators are provided together with a pair of bistable storage elements which produces a narrow pulse in response to the negative zero-crossing transition of an input signal provided that the input signal has exceeded the positive reference threshold applied to the second comparator.

Description

Voltage comparators and other circuits for slicing analogue signals are well known in the art and employed in many situations. In some applications where the need exists to distinguish a valid signal from low level noise, a voltage threshold may be applied to the reference input of the comparator in order that only signals exceeding that threshold voltage will cause the comparator to switch. Unfortunately when this method is used, the transition of the comparator output will be delayed with reference to the zero-crossing of the input in one direction and advanced in the other direction by an amount depending upon the amplitude of the input signal. In some applications like carrier recovery and timing recovery systems in high performance data modems it is essential to preserve accurately the zero-crossing instant of the input while providing a threshold to prevent the comparator responding to signals of less than a predetermined amplitude.
United States Patent No. 3,718,864, particularly at Figs. 3 and 5 and column 3 (line 7) to column 5 (line 16), discloses a circuit arrangement suitable for such purposes. Similarly U.S. Patent No. 3,639,779, at Figs. 1 and 2 and column 4 (lines 49 to 66) discloses a circuit arrangement adapted to generate an output signal when an input signal crosses zero on condition that the excursion of the input signal has exceeded a reference threshold signal during the previous half cycle. It is an aim of the present invention to provide a circuit arrangement which produces an accurate and short duration indication of the zero-crossing instant.
According to the invention there is provided a circuit arrangement for use in carrier and timing recovery circuits of a digital data transmission system, the arrangement being adapted to generate an output signal when an input signal crosses zero on condition, that the excursion of the input signal has exceeded a reference threshold signal during the previous half cycle, including first and second differential amplifiers both of which are connected to receive the input signal and further including a toggle characterised in that the first differential amplifier is arranged to produce an output signal when the input signal passes through zero in a first direction, the second differential amplifier being arranged to produce an output signal when the input signal falls in the said first direction below a predetermined threshold value, the output signal of the first differential amplifier is fed to the clock input of the toggle and the output signal of the second differential amplifier being fed to the clock input of a second toggle the first and second toggles are D type toggles of which the data inputs are held at a constant logic state level and which are interconnected such that the clear input of the first toggle is fed from the true output of the second toggle and the clear input of the second toggle is fed from the inverse output of the first toggle, the duration of the output pulse being defined by the time it takes to clear the first and second toggles.
In order that the invention may be more readily understood reference is made to the accompanying drawing which illustrates an embodiment of the present invention comprising two comparators and bistable storage elements which produce a narrow pulse in response to the negative zero-crossing transition of the input signal provided that the input signal has exceeded the positive reference threshold applied to the second comparator.
The drawing shows two differential amplifier comparators C1 and C2 driving a pair of "D" type toggles D1 and D2 which are interconnected so as to generate a narrow pulse on the output lead OPS when the input lead IPS passes through zero after having exceeded the positive threshold provided by the threshold level +VT. The output signals from the comparators C1 and C2 are connected respectively to the clock inputs of the "D" type toggles while the data inputs to the "D" type toggles are held at the logic "1" state level. The clear output Q2 from toggle D2 is used to control the clear input to toggle D1 while the inverse output ërf from toggle D1 is used to control the clear input to toggle D2. In operation when the positive half cycle of the input signal falls below the threshold level +VT toggle D2 is set by the output from causing comparator C2. This causes toggle D1 to be primed on its clear input by the "1" state signal on Q2. When the input waveform IPS reaches zero comparator C1 generates an output condition to switch D1 to the "1" state. The "0" transition on Q1 causes toggle D2 to be cleared which in turn switches Q2 to the "0" state thereby clearing D1. The output signal OPS, therefore, exists for the time it takes to clear toggles D2 and D1.
The above description has concentrated on circuit arrangements operating on positive signals, whereas it will be obvious to those skilled in the art how the circuits could be amended to operate on negative half cycles.

Claims

A circuit arrangement for use in carrier and timing recovery circuits of a digital data transmission system, the arrangement being adapted to generate an output signal (OPS) when an input signal (IPS) crosses zero on condition that the excursion of the input signal has exceeded a reference threshold signal (+VE) during the previous half cycle, including first (C1) and second (C2) differential amplifiers both of which are connected to receive the input signal (IPS) and further including a toggle (D1) characterised in that the first differential amplifier (C1) is arranged to produce an output signal when the input signal passes through zero in a first direction, the second differential amplifier (C2) being arranged to produce an output signal when the input signal falls in the said first direction below a predetermined threshold value, the output signal of the first differential amplifier (C1) is fed to the clock input (CLK) of the toggle (D1) and the output signal of the second differential amplifier (C2) being fed to the clock input of a second toggle (D2), the first (D1) and second (D2) toggles are D type toggles of which the data inputs (D) are held at a constant logic state level (VCC) and which are interconnected such that the clear input (CLR) of the first toggle (D1) is fed from the true output (Q2) of the second toggle and the clear input (CLR) of the second toggle is fed from the inverse output
of the first toggle, the duration of the output pulse being defined by the time it takes to clear the first (D1) and second (D2) toggles.