EP0016386B1 - Erasably programmable semiconductor memories of the floating-gate type - Google Patents

Erasably programmable semiconductor memories of the floating-gate type Download PDF

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Publication number
EP0016386B1
EP0016386B1 EP80101184A EP80101184A EP0016386B1 EP 0016386 B1 EP0016386 B1 EP 0016386B1 EP 80101184 A EP80101184 A EP 80101184A EP 80101184 A EP80101184 A EP 80101184A EP 0016386 B1 EP0016386 B1 EP 0016386B1
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Prior art keywords
floating gate
memory cell
floating
gate
semiconductor memory
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EP80101184A
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German (de)
French (fr)
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EP0016386A1 (en
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Burkhard Dipl.-Ing. Giebel
Adolf Dr. Ing. Dipl.-Phys. Scheibe
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Siemens AG
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling

Definitions

  • the invention relates to a reprogrammable semiconductor memory cell according to the preamble of claim 1. in the under the title “Electrically Erasable and Reprogrammable Read-Only Memory Using the n-Channel SIMOS One-Transistor Cell” in “IEEE Trans. on Electron Devices” Vol. ED-24, No. 5, May 1977, pages 606-610.
  • a high threshold voltage swing ⁇ U T consequently also requires a high coupling capacitance C FC and thus, for example, a large overlap area between the floating gate hereinafter referred to exclusively as the floating gate and the control gate.
  • C FC coupling capacitance
  • the invention proposes to solve this problem an additional potential carrier, by means of which a further potential U x can be capacitively coupled to the floating gate during programming (see FIG. 2).
  • a semiconductor memory cell of the type mentioned at the outset is already known from DE eing OS 22 01 028.
  • a semiconductor memory cell with floating gate, source and drain is presented, which additionally has an electrode and an electrically conductive layer ("third gate electrode").
  • a semiconductor memory cell with source, drain, floating gate and control gate is known from document JP-A-53-86179.
  • an additional layer is arranged under the two gates outside the channel area between the source and drain.
  • loading or unloading is neither via the source or drain to or from the floating gate (avalanche breakdown) nor within the channel area (channel injection), but outside of this area directly from the additional location into the floating gate or vice versa.
  • FIGS. 3 to 4 Suitable examples according to the invention for creating additional potential carriers are explained below with reference to FIGS. 3 to 4.
  • the left side of a figure represents the top view and the right side thereof shows a section along the line A-B through the broken-illustrated memory cell of the floating gate type.
  • the memory cell has a semiconductor substrate 7, which is formed in the usual manner with source 4 and drain 5 and carries an insulating, in particular SiO 2 layer 6 applied to this substrate with control gate 1 and floating gate 2 arranged in this layer .
  • an additional diffusion region 3 which serves as a potential carrier, is capacitively coupled to the floating gate 2, by which the applied voltage swing AU T by the amount when voltage is applied is increased.
  • the high coupling capacitance between the floating gate and the additional diffusion region '3 is in this case achieved by reducing the oxide thickness between the diffusion region 3 and the floating gate. 2
  • This memory cell is suitable, for example, as an electrically erasable SIMOS memory cell (EEPROM or EAROM application) with a separate erase diffusion area.
  • EEPROM electrically erasable SIMOS memory cell
  • EAROM electrically erasable SIMOS memory cell
  • This figure also shows a memory cell with a control gate 11 and a floatin gate 12.
  • an Si electrode 13 is additionally capacitively coupled to the floating gate 12. The threshold voltage stroke increases by the amount already mentioned in Example 1.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)

Description

Die Erfindung betrifft eine umprogrammierbare Halbleiter-Speicherzelle nach dem Oberbegriff des Patentanspruches 1. Eine solche ist z.B. in dem unter dem Titel "Electrically Erasable and Reprogrammable Read-Only Memory Using the n-Channel SIMOS One-Transistor Cell" in "IEEE Trans. on Electron Devices" Vol. ED-24, No. 5, Mai 1977, Seiten 606-610, veröffentlichten Aufsatz beschrieben.The invention relates to a reprogrammable semiconductor memory cell according to the preamble of claim 1. in the under the title "Electrically Erasable and Reprogrammable Read-Only Memory Using the n-Channel SIMOS One-Transistor Cell" in "IEEE Trans. on Electron Devices" Vol. ED-24, No. 5, May 1977, pages 606-610.

Gemäß dem gleichfalls in dieser Literaturstelle, Seiten 600 ff. erschienenen Aufsatz "Technology of a New n-Channel One-Transistor EAROM Cell Called SIMOS" ist dabei der beim Programmieren dieser Speicherzellen erreichte Einsatzspannungsshub AUT, d.h. die Einsatzspannungsverschiebung gemäß der Beziehung

Figure imgb0001
im wesentlichen eine Funktion der in der Si2-Gate-Struktur enthaltenen, in Fig. 1 im Ersatzschaltbild dargestellten Koppelkapazitäten. Es bedeutet dabei:

  • Us=am Sourceanschluß anliegende Spannung
  • USub=am Substrat anliegende Spannung
  • UD=am Drainanschluß anliegende Spannung
  • Up=Programmierspannung am Steuergate
  • U'Ds=das auf Source bezogene Potential des Kanalabschnittes, von dem aus die Ladungsträgerinjektion auf das Floating-Gate erfolgt
  • CFs=Koppelkapazität zwischen Floating-Gate und Source
  • CFD=Koppelkapazität zwischen Floating-Gate und Drain
  • CFc=Koppelkapazität zwischen Steuergate und Floating Gate
  • CFSub=Koppelkapazität zwischen Floating-Gate und Substrat.
According to the article "Technology of a New n-Channel One-Transistor EAROM Cell Called SIMOS" also published in this reference, page 600 ff., The threshold voltage swing AU T achieved when programming these memory cells is the threshold voltage shift according to the relationship
Figure imgb0001
 essentially a function of the coupling capacitances contained in the Si 2- gate structure, shown in FIG. 1 in the equivalent circuit diagram. It means:
  • U s = voltage present at the source connection
  • U Sub = voltage applied to the substrate
  • U D = voltage present at the drain connection
  • Up = programming voltage at the control gate
  • U ' Ds = the source-related potential of the channel section from which the charge carrier injection onto the floating gate takes place
  • C Fs = coupling capacitance between floating gate and source
  • C FD = coupling capacitance between floating gate and drain
  • C Fc = coupling capacitance between control gate and floating gate
  • C FSub = coupling capacitance between floating gate and substrate.

Ein hoher Einsatzspannungshub △UT erfordert demzufolge auch eine hohe Koppelkapazität CFC und damit z.B. eine große Überlappfläche zwischen dem im folgenden ausschließlich als Floating-Gate bezeichneten schwebenden Gate und dem Steuergate. Der Verkleinerung der je Speicherzelle erforderlichen Fläche und damit einer Erhöhung der Speicherdichte sind folglich enge Grenzen gesetzt.A high threshold voltage swing △ U T consequently also requires a high coupling capacitance C FC and thus, for example, a large overlap area between the floating gate hereinafter referred to exclusively as the floating gate and the control gate. The reduction of the area required for each memory cell and thus an increase in the storage density are consequently narrow limits.

Der vorliegenden Erfindung liegt die Aufgabe zugrunde, eine Halbleiter-Speicherzelle der eingangs genannten Art zu schaffen.

  • 1. Bei der bei gleichem Einsatzspannungshub AUT die Koppelkapazität CFc zwischen dem Floating-Gate und Steuergate bzw. die Überlappfläche zwischen diesen beiden Gates verringert ist oder
  • 2. bei der bei gleicher Überlappfläche zwischen den beiden Gates der Einsatzspannungshub AUT erhöht wird oder
  • 3. bei der bei gleichem Einsatzspannungshub AUT und gleicher Überlappfläche zwischen den beiden Gates die Programmierspannung Up, d.h. die zum Einschreiben der Information in die Speicherzellen erforderliche Steuergäte-Spannung, erniedrigt wird.
The present invention has for its object to provide a semiconductor memory cell of the type mentioned.
  • 1. At which the coupling capacitance C Fc between the floating gate and control gate or the overlap area between these two gates is reduced or at the same threshold voltage stroke AU T
  • 2. where the threshold voltage stroke AU T is increased with the same overlap area between the two gates or
  • 3. With the same threshold voltage stroke AU T and the same overlap area between the two gates, the programming voltage Up, ie the control device voltage required to write the information into the memory cells, is reduced.

Bei einer gattungsgemäßen Halbleiter-Speicherzelle schlägt die Erfindung zur Lösung dieser Aufgabe einen zusätzlichen Potentialträger vor, durch den ein weiteres Potential Ux während des Programmierens kapazitiv an das Floating-Gate ankoppelbar ist (siehe Fig. 2).In the case of a generic semiconductor memory cell, the invention proposes to solve this problem an additional potential carrier, by means of which a further potential U x can be capacitively coupled to the floating gate during programming (see FIG. 2).

Da hierbei gilt:

Figure imgb0002
bewirkt der zusätzliche Potentialträger eine Erhöhung des Einsatzspannungshubes AUT um den Betrag
Figure imgb0003
wobei CFX=Koppelkapazität zwischen Floating-Gate und zusätzlichem Potentialträger.The following applies here:
Figure imgb0002
 causes the additional potential carrier to increase the threshold voltage stroke AU T by the amount
Figure imgb0003
 where C FX = coupling capacitance between floating gate and additional potential carrier.

Wird auf eine Vergrößerung des Einsatzspannungshubes △UT verzichtet, so kann gemäß Beziehung (2) entweder die Programmierspannung Up oder über die Koppelkapazität CFc die Fläche der Speicherzellen verringert werden, was die Schaffung von Festwertspeichern mit höherer Speicherdichte ermöglicht.If an increase in the threshold voltage swing hub U T is dispensed with, then according to relationship (2) either the programming voltage Up or the coupling capacitance C Fc can be used to reduce the area of the memory cells, which enables the creation of read-only memories with a higher storage density.

Aus der DE―OS 22 01 028 ist bereits eine Halbleiterspeicherzelle der eingangs genannten Art bekannt. Dort wird eine Halbleiterspeicherzelle mit Floating-Gate, Source und Drain vorgestellt, die zusätzlich eine Elektrode und eine elektrisch leitende Lage ("dritte Gate-Elektrode") aufweist. Diese zusätzliche, elektrisch leitende Lage ist oberhalb des Floating-Gates, außerhalb eines Bereiches zwischen Source und Drain (=Kanal) angeordnet. Dies ist ersichtlich aus der DE-OS 22 01 028, Fig. 4 in Verbindung mit S. 11, zweiter Absatz bis S. 13.A semiconductor memory cell of the type mentioned at the outset is already known from DE eing OS 22 01 028. There a semiconductor memory cell with floating gate, source and drain is presented, which additionally has an electrode and an electrically conductive layer ("third gate electrode"). This additional, electrically conductive layer is arranged above the floating gate, outside of an area between the source and drain (= channel). This can be seen from DE-OS 22 01 028, Fig. 4 in connection with p. 11, second paragraph to p. 13.

Im Gegensatz zum Gegenstand der vorliegenden Erfindung wird jedoch an diese elektrisch leitende Lage nicht ein weiteres Potential angelegt, sondern eine der auch anderweitig verwendeten Versorgungsspannungen.In contrast to the object of the present invention, however, no further potential is applied to this electrically conductive layer, but one of the supply voltages also used in another way.

Ein grundlegender Unterschied liegt auch im verwendeten Arbeitsprinzip bei der bekannten Halbleiter-Speicherzelle: es wird das Prinzip des Lawinendurchbruches (Avalanche Breakdown) verwendet. Das Laden bzw. Entladen des Floating-Gates wird unter Anlegen von Versorgungspotentialen (Erdpotential, Versorgungsspannung) an die dritte Gate-Elektrode durch Lawinendurchbruch vom Floating-Gate in Source und Drain bzw. umgekehrt durchgeführt. Dabei fließt kein Strom zwischen Source und Drain. Beim Gegenstand der vorliegenden Erfindung wird das Programmieren jedoch durch einen hohen Stromfluß zwischen Source und Drain mittels Kanalinjektion in das Floating-Gate erreicht, wobei erfindungsgemäß das an den zusätzlichen Potentialträger (3, 13) angelegte weitere Potential Ux kapazitiv an das Floating-Gate angekoppelt wird. Vor der Verwendung dieses Ladungsübertragungsmechanismus bei der bekannten Halbleiterspeicherzelle wird in der DE-OS 22 01 028 ausdrücklich gewarnt (Zerstörung der Speicherzelle).There is also a fundamental difference in the working principle used in the known semiconductor memory cell: the principle of avalanche breakdown is used. The charging or discharging of the floating gate is carried out by applying supply potentials (ground potential, supply voltage) to the third gate electrode by avalanche breakdown from the floating gate into the source and drain and vice versa. No current flows between the source and drain. In the subject of the present invention, however, programming is achieved by a high current flow between source and drain by means of channel injection into the floating gate, the additional potential U x applied to the additional potential carrier (3, 13) being capacitively coupled to the floating gate becomes. DE-OS 22 01 028 expressly warns against the use of this charge transfer mechanism in the known semiconductor memory cell (destruction of the memory cell).

Aus dem Dokument JP-A-53-86179 ist eine Halbleiterspeicherzelle bekannt mit Source, Drain, Floating-Gate und Steuergate. Zusätzlich ist unter den beiden Gates jedoch außerhalb des Kanalbereiches zwischen Source und Drain, eine zusätzliche Lage angeordnet. Das Laden bzw. Entladen erfolgt jedoch weder über Source bzw. Drain zum bzw. vom Floating-Gate (Lawinendurchbruch) noch innerhalb des Kanalbereiches (Kanalinjektion), sondern außerhalb dieses Bereiches direkt von der zusätzlichen Lage aus in das Floating-Gate bzw. umgekehrt.A semiconductor memory cell with source, drain, floating gate and control gate is known from document JP-A-53-86179. In addition, however, an additional layer is arranged under the two gates outside the channel area between the source and drain. However, loading or unloading is neither via the source or drain to or from the floating gate (avalanche breakdown) nor within the channel area (channel injection), but outside of this area directly from the additional location into the floating gate or vice versa.

Keine dieser bekannten Halbleiterspeicherzellen löst also die gestellte Aufgabe.None of these known semiconductor memory cells therefore accomplishes the task.

Nachstehend werden anhand der Figuren 3 bis 4 geeignete Beispiele nach der Erfindung zur Schaffung zusätzlicher Potentialträger erläutert. Die jeweils linke Seite einer Figur stellt die Draufsicht und ihre jeweils rechte Seite einen Schnitt gemäß der Linie A-B durch die gebrochen veranschaulichte Speicherzelle vom Floating-Gate-Typ dar.Suitable examples according to the invention for creating additional potential carriers are explained below with reference to FIGS. 3 to 4. The left side of a figure represents the top view and the right side thereof shows a section along the line A-B through the broken-illustrated memory cell of the floating gate type.

1. Ausführungsbeispiel (siehe Fig. 3)1st embodiment (see FIG. 3)

Die Speicherzelle weist ein Halbleiter-Substrat 7 auf, das in üblicher Weise mit Source 4 und Drain 5 ausgebildet ist und eine auf diese Substrat aufgebrachte Isolier-, insbesondere Si02-Schicht 6 mit in dieser Schicht angeordnetem Steuergate 1 und Floating-Gate 2 trägt. Versetzt zur Source 4 ist an das Floating-Gate 2 ein zusätzliches, als Potentialträger dienendes Diffusionsgebiet 3 kapazitiv angekoppelt, durch das bei Anlegen von Spannung der Einsatzspannungshub AUT um den Betrag

Figure imgb0004
erhöht wird. Die hohe Koppelkapazität zwischen dem Floating-Gate und dem zusätzlichen Diffusionsgebiet' 3 wird dabei durch die Verringerung der Oxiddicke zwischen dem Diffusiongebiet 3 und dem Floating-Gate 2 erzielt.The memory cell has a semiconductor substrate 7, which is formed in the usual manner with source 4 and drain 5 and carries an insulating, in particular SiO 2 layer 6 applied to this substrate with control gate 1 and floating gate 2 arranged in this layer . Staggered to the source 4, an additional diffusion region 3, which serves as a potential carrier, is capacitively coupled to the floating gate 2, by which the applied voltage swing AU T by the amount when voltage is applied
Figure imgb0004
 is increased. The high coupling capacitance between the floating gate and the additional diffusion region '3 is in this case achieved by reducing the oxide thickness between the diffusion region 3 and the floating gate. 2

Geeignet ist diese Speicherzelle beispielsweise als elektrisch löschbare SIMOS-Speicherzelle (EEPROM oder EAROM Anwendung) mit gesondertem Lösch-Diffusionsgebiet.This memory cell is suitable, for example, as an electrically erasable SIMOS memory cell (EEPROM or EAROM application) with a separate erase diffusion area.

2. Ausführungsbeispiel (siehe Fig. 4)2nd embodiment (see FIG. 4)

Diese Figur zeigt gleichfalls eine Speicherzelle mit einem Steuergate 11 und einem Floatin-Gate 12. Zur Erhöhung des Einsatzspannungshubes AU-r ist eine Si-Elektrode 13 zusätzlich an das Floating-Gate 12 kapazitiv angekoppelt. Der Einsatzspannungshub vergrößert sich dabei um den im Beispiel 1 bereits genannten Betrag.This figure also shows a memory cell with a control gate 11 and a floatin gate 12. To increase the threshold voltage swing AU-r, an Si electrode 13 is additionally capacitively coupled to the floating gate 12. The threshold voltage stroke increases by the amount already mentioned in Example 1.

Claims (3)

1. An erasably programmable semiconductor memory cell consisting of a semiconductor substrate (7) having a source region (4) and a drain region (5), an insulating layer (6), which is placed on the semiconductor substrate (7), a floating gate (2, 12), and a control gate (1, 11), which memory cell is programmable by means of channel injection, characterised by an additional potential carrier (3, 13), by means of which a further potential Ux can be capacitively coupled to the floating gate (2, 12) during programming.
2. A semiconductor memory cell as claimed in Claim 1, characterised in that the additional potential carrier (3, 13) consists of a separate diffusion region.
3. A semiconductor memory cell as claimed in Claim 1, characterised in that the additional potential carrier (3, 13) consisting of a Si-electrode.
EP80101184A 1979-03-07 1980-03-07 Erasably programmable semiconductor memories of the floating-gate type Expired EP0016386B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE2908796 1979-03-07
DE2908796A DE2908796C3 (en) 1979-03-07 1979-03-07 Re-programmable semiconductor read-only memory of the floating gate type

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EP0016386A1 EP0016386A1 (en) 1980-10-01
EP0016386B1 true EP0016386B1 (en) 1985-10-09

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EP (1) EP0016386B1 (en)
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4331968A (en) * 1980-03-17 1982-05-25 Mostek Corporation Three layer floating gate memory transistor with erase gate over field oxide region
JPS5759387A (en) * 1980-09-26 1982-04-09 Toshiba Corp Semiconductor storage device
DE3136517C2 (en) * 1980-09-26 1985-02-07 Tokyo Shibaura Denki K.K., Kawasaki, Kanagawa Non-volatile semiconductor memory device
DE3037744A1 (en) * 1980-10-06 1982-05-19 Siemens AG, 1000 Berlin und 8000 München METHOD FOR PRODUCING A MONOLITHICALLY INTEGRATED TWO-TRANSISTOR MEMORY CELL IN MOS TECHNOLOGY
JPS57141969A (en) * 1981-02-27 1982-09-02 Toshiba Corp Nonvolatile semiconductor memory
JPS5857750A (en) * 1981-10-01 1983-04-06 Seiko Instr & Electronics Ltd Non-volatile semiconductor memory
US5598367A (en) * 1995-06-07 1997-01-28 International Business Machines Corporation Trench EPROM
US7075127B2 (en) * 2004-01-29 2006-07-11 Infineon Technologies Ag Single-poly 2-transistor based fuse element

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3919711A (en) * 1973-02-26 1975-11-11 Intel Corp Erasable floating gate device
US4016588A (en) * 1974-12-27 1977-04-05 Nippon Electric Company, Ltd. Non-volatile semiconductor memory device
US4274012A (en) * 1979-01-24 1981-06-16 Xicor, Inc. Substrate coupled floating gate memory cell
US4361847A (en) * 1980-04-07 1982-11-30 Eliyahou Harari Non-volatile EPROM with enhanced drain overlap for increased efficiency

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DE2908796B2 (en) 1981-07-30
US4459608A (en) 1984-07-10
EP0016386A1 (en) 1980-10-01
JPS55143074A (en) 1980-11-08
DE2908796C3 (en) 1982-04-01

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