EP0000489A1 - Method for the non-destructive testing of semiconductor substrates - Google Patents

Abstract

In the method for the non-destructive testing of semiconductor substrates, these are immersed in a dilute electrolyte solution (23), then the substrates (21) are negatively biased against the electrolyte solution (23) with a voltage in the range between approximately 50 and approximately 65 volts and at the same time, the substrate surfaces are illuminated with an illuminance in the range between approximately 538 and approximately 807 1x. The hydrogen bubble pattern developing at the fault locations can be recorded photographically. The method is particularly suitable for locating and registering electrically active fault locations on semiconductor surfaces, defective P / N junctions and disturbed areas in large-area P / N junctions and is therefore a test method both in semiconductor wafer production and in the manufacture of integrated ones Circuits can be used.

Description

The invention relates to a method for locating electrically active defects in a single-crystalline semiconductor substrate, the semiconductor substrate being placed in a dilute electrolyte solution, biased negatively against it and illuminated.

A number of methods have been described to remove imperfections or defects in single crystal semiconductor articles such as. B. silicon wafers to discover. The discovery of such defects is of particular importance in the manufacture of integrated circuits, where defects in the surface layers of the semiconductor substrates can reduce the yield of usable chips with integrated circuits. These methods include, for example, the preparation of bevel cuts and the etching of the ground surface, the raster oscillator topography (SOT) and capacitor leakage current measurements. Recently, cathode current measurements have been used to characterize P-type semiconductor substrates by negatively biasing the substrate in a dilute aqueous acid electrolyte solution with a voltage of a few volts. It is believed that under the influence of the electric field, a layer of positive ions originating from the electrolyte coalesce at the interface between the semiconductor and the solution while the holes are pushed from the semiconductor surface into the substrate material to a depth W. Only the negative acceptor ions remain in this depletion zone, and their charge balances the positive charge of the ion layer at the interface between the semiconductor and the solution. If, under these conditions, a defect is generated between the electron and hole pairs within the depletion zone, the holes are pushed into the semiconductor material by the electric field, while the electrons are drawn to the interface between the semiconductor and the solution, where they interact with the positive ions in the Solution can react at the interface. This mechanism generates a current that can be measured outside the measuring cell. It is assumed that the reaction between the electrons and the positive ions in the solution proceeds according to the following reaction equation:

Since the H30 + ion concentration is greater than that of the minority carrier at the interface between the semi-conductor and the solution, the reaction is controlled by the speed of the generation of electron-hole pairs or, in other words, by the electrically active defects in the depletion zone. The measurement of the cathode current can thus be used to characterize the quality of the semiconductor substrate. The semiconductor material does not participate in the electrochemical reaction, so that the substrate is not changed. It is also known that artificial defects in a silicon wafer could be created using a high intensity flash of light when a bias of about 5 volts was applied to the substrate. In this case, considerable gas evolution was observed on the plate when the cell was illuminated.

Although the cathode current measurements are not destructive and can be carried out quickly, such measurements give no indication of the nature or the location of the impurities. For example, a single large defect at one location of a semiconductor die and a large number of small but significant defects, which are distributed over a relatively large area of a second die, can result in the same cathode current. In the first case, the die would be suitable for the production of integrated circuits because the defect is limited to one chip or could even be in the part of the die which is omitted during cutting, so that at most a small loss in yield would occur. This die would be considered a "good" die, while the second die, which has a large number of small impurities, would be unsuitable for manufacturing integrated circuits.

A method for imaging the quality of a semiconductor die in the form of a “map” of the die is disclosed in the article “Inline Wafer Quality Monitor” in the IBM Technical Disclosure Bulletin, Volume 18, No. 12, May 1976, page 4012. In this method, an array of light emitting diodes is used to illuminate different areas of the die so that cathode current information is obtained from different areas of the die. The article "Scanning Cathodic Current Spectroscopy" in the IBM Technical Disclosure Bulletin, Volume 18, No. 11, April 1976, page 3623 describes the use of a reader beam for scanning the semiconductor material, which serves to reduce the quality of the depletion zone in the form of a " Map "'. The "map" of semiconductor quality can be obtained because the flawed areas cause a decrease in current under the conditions mentioned. It is also known to localize cracks in top layers on semiconductors or metals, by applying a bias to the substrate in an electrolyte so that hydrogen evolves where the substrate material is exposed to the solution. Metals have been tested for voltage (stress) inhomogeneities by placing them in a sulfuric acid electrolyte solution under a 6 volt bias, producing nascent hydrogen which is absorbed by the inhomogeneities. The metal surface is then covered with a plastic film and then heated to desorb the hydrogen, causing bubble formation in the film where it is located.

It is the object of the invention, a simple, non-annoying and quickly feasible method for detecting and registering, in particular, electrically active defects in semiconductor substrates, defective P / N junctions and disturbed areas of large-area P / N junctions with respect to their position and the extent of the disruption.

This object is achieved with a method of the type mentioned at the outset with the features of the characterizing part of claim 1.

gelegter Weise variiert wird. Allgemein

daß das erfindungsgemäße Verfahren als Drüfmethode sowohl in der Halbleiterplättchen-Fertigung als auch bei der Herstellung von integrierten Schaltkreisen in vorteilhafter integrierten Schaltkreisen in vorteilhafter Weise verwendbar ist. Außerdem lassen sich mit dem erfindungsgemäßen Verfahren die Wirkung von verschisdenen Getterprozessen auf die elektrisch aktiven Störstellen ermitteln.The method according to the invention results in good agreement with other destructive and / or time-consuming methods which have hitherto been used to localize electrically active defects in the surface of semiconductor substrates. By means of the pattern which is formed when the method according to the invention is carried out and which consists of the hydrogen bubbles adhering to the substrate surface, it is not only possible to localize the locations at which the interference _E telephones are located, but rather it is also possible to measure the extent of the interference determine by the length of time during which is the bias to the substrate

is varied occasionally. General

that the method according to the invention can be used advantageously as a screening method both in semiconductor die production and in the production of integrated circuits in advantageous integrated circuits. In addition, the effect of various getter processes on the electrically active defects can be determined with the method according to the invention.

Advantageous refinements of the method according to the invention result from the subclaims.

• tels des erfindungsgemäßen Verfahrens erhalten wurde, und bei der Fig. 4B um eine Aufnahme, welche mittels der Raster-Oszillations-Topographie (SOT) erhalten wurde,
• Fign. 5A-D Fotografien eines Siliciumplättchens, in welches Stufen geätzt sind, wobei die-Figuren 5A bis 5C Wasserstoffbläschenmuster zeigen, welche unter unterschiedlichen Beleuchtungs- und Vorspannungsbedingungen erhalten worden sind, und die Fig. 5D zum Vergleich eine Raster-Oszillations-Topographie-Aufnahme desselben Siliciumplättchens vom P-Typ zeigt,
• Fign. 6A Fotografien eines Siliciumplättchens, wobei und 6B Fig. 6A ein Wasserstoffbläschenmuster zeigt und die Fig. 6B zum Vergleich eine retuschierte Aufnahme desselben Siliciumplättchens vom P-Typ zeigt, aus welcher die Bereiche elektrischer Defekte, wie sie mittels Kondensator-Leckstrommessungen ermittelt worden sind, zu ersehen sind,
• Fign. 7A Fotografien eines Siliciumplättchens vom und 7B P-Typ, wobei die Fig. 7A ein Wasserstoffbläschenmuster zeigt und die Fig. 7B zum Vergleich eine retuschierte Fotografie, aus welcher die Bereiche elektrischer Effekte, wie sie mittels Kondensator-Leckstrommessungen ermittelt worden sind, zu ersehen sind, zeigt, und
• Fig. 8 eine retuschierte Fotografie eines Siliciumplättchens vom P-Typ, welches eines Subkollektorbereich vom N⁺-Typ und eine oberflächliche Epitaxieschicht vom N^--Typ aufweist, wobei aus
  

The invention is described on the basis of exemplary embodiments explained by drawings. Show it:

• was obtained by means of the method according to the invention, and in FIG. 4B an image which was obtained by means of the raster oscillation topography (SOT)
• Fig. 5A-D photographs of a silicon die in which steps are etched, FIGS. 5A to 5C showing hydrogen bubble patterns obtained under different lighting and biasing conditions, and FIG. 5D for comparison, a raster oscillation topography image thereof P-type silicon wafer shows
• Fig. 6A photographs of a silicon wafer, and and 6B; FIG. 6A shows a hydrogen bubble pattern and FIG. 6B shows a retouched image of the same P-type silicon wafer for comparison, from which the areas of electrical defects as determined by means of capacitor leakage current measurements are shown are seen
• Fig. 7A photographs of a and 7B P-type silicon wafer, FIG. 7A showing a hydrogen bubble pattern and FIG. 7B for comparison a retouched photograph from which the areas of electrical effects, as determined by means of capacitor leakage current measurements, can be seen , shows, and
• 8 is a retouched photograph of a P-type silicon die having an N ⁺ -type subcollector region and a N ^- -type epitaxial layer
  

1 to 2 1/2 vol.% Solution of 96% sulfuric acid in deionized water can be used. Other concentrations could also be used. Other electrolytes, which are a source of H ₃ 0 ⁺ ions, such as. B. hydrofluoric acid and acetic acid can also be used.

Materials that can be tested using the method according to the invention are single-crystalline semiconductor materials, such as, for. B. P-type silicon or germanium, and P-type semiconductor substrates which have an N-type surface layer either epitaxially or by diffusion. The semiconductor substrate, such as. B. a silicon wafer should have a surface that is clean and oxide-free. As a result, the substrate is first cleaned to remove any oxides, organic material deposits, or other films and dirt from the surface. Any conventional semiconductor cleaning process can be used with which a clean, dirt-free surface can be obtained.

After cleaning, the substrate is attached to the cell and the electrolyte is poured into the cell. Care should be taken to ensure that the electrolyte is not moved during the test. Movement of the electrolyte can remove hydrogen bubbles from their place on the surface, resulting in loss of information. The substrate is uniformly irradiated with white light, the light intensity of which lies on the substrate surface in the range between approximately 538 and approximately 805 lx. It has been found that light intensities below about 538 1x, except for the most damaged locations, do not create any bubbles at the locations where the electrical defects are located. On the other hand, with light intensities of about 860 lx and above, a substantial amount is also found in the areas of hydrogen bubbles.

The wafer was then cleaned to remove any oxides and films from organic material. Oxide can prevent bubbles from developing, and films made of organic material can cause bubbles in places where there are no defects.

The plate was cleaned by immersing it in hydrofluoric acid, immersing it in 5% sodium hypochlorite solution for 10 min under ultrasonic excitation and rinsing it in deionized water. The plate was then immersed in a 10: 1 mixture of water and HCl under ultrasound excitation, rinsed again with deionized water, then immersed in a 10: 1 mixture of water and hydrofluoric acid for 30 seconds and finally rinsed in deionized water . After cleaning, the wafer was placed in the test cell 19 and then a 2 1/2 vol.% Aqueous sulfuric acid electrolyte solution was added. Illumination was by means of a 75 watt tungsten headlamp, which was set so that it produced an illuminance of 753.48 lx on the plate surface. Switch 17 was closed to apply a negative 60 volt bias to the plate for 5 seconds. The bubble pattern was photographed. The photograph is shown in Fig. 4A. It can be seen that hydrogen bubbles have formed on the first four stages. A raster oscillator topography (SOT) image, which is shown in FIG. 4B, was also taken (for details see, for example, in the article "New X-Ray Diffraction Microscopy Technique for the Study of Imperfections in Semiconductor Crystals ", by Schwuttke in the Journal of Applied Physics, volume 36, Mr. 9, Sepremter 1965, pages 2712-2721). The dark areas of the topography indicate that voids occur in the first four stages, which corresponds to the bubble pattern in Figure 4A.

The plate was then cut perpendicular to the steps, then the exposed cut surface was ground at an angle and diluted Sirtl etching solution (stock solution = 1 gram Cr ₂ O ₃ in 4 ml deionized water, diluted Sirtl acetic solution = 1 part stock solution) Part of hydrofluoric acid) to make the imperfections visible. The etchant is made by mixing a portion of a stock solution containing 1 gram of Cr ₂ O ₃ per 4 milliliters of deionized water with a portion of hydrofluoric acid. Starting from a point approximately 2 millimeters from the platelet notch, which can be seen in the photograph as a V-shaped incision in the platelet edge, the depths of the defects were measured optically, measuring approximately one millimeter apart, so that per step 4 to 5 measurements carried out. The

It can be seen that the determination by means of angled grinding and etching also makes flaws visible in the first four stages, so that the results show a good agreement between all three methods.

Example 2:

In order to explain the method according to the invention in more detail and to demonstrate the importance of maintaining the correct voltage and lighting conditions, a stepped silicon plate of the P type with a diameter of 82.5 millimeters and a specific resistance of 2 Ω cm was tested. This was preceded by cutting the plate from a large crystal and etching the steps.

führt. Die Ergebnisse, welche unter verschiedenen Spannung-und Beleuchtungsbedingungen erhalten worden sind, werden zum Vergleich zusammen mit Kondensator-Leckstrommessungen dargestellt.The heights of the steps are listed in Table III.

leads. The results obtained under different voltage and lighting conditions are presented for comparison together with capacitor leakage current measurements.

A 5000 angstroms thick silicon dioxide layer was thermally grown on the substrate at 1000 ° C. Aluminum dots approximately 1.5 mm in diameter were deposited on the oxide layer and then the capacitor leakage currents were measured at every third point. A map of the points at which the _'leakage currents were greater than 6 nanoamperes, is shown in FIG. 6B. Since only every third point was checked, an arrangement of nine points, including the "8 points surrounding the measuring point," was made black in the photograph whenever an examined point exceeded 6 nanoamperes Weighting of the components with leakage currents above and below the 6 nanoampere level. The aluminum points were removed using an aluminum etchant and the oxide was removed with hydrofluoric acid. The substrate was cleaned by placing it in an ultrasonically excited semiconductor cleaning bath for 5 minutes, then was rinsed in deionized water, followed by a second immersion in dilute hydrofluoric acid (10 vol.% HF in water) for 30 to 60 seconds, a rinse in deionized water, a 1 minute immersion in the cleaning bath and a final water rinse.

The cleaned substrate was placed in test cell 19, which contained a 2% by volume sulfuric acid solution, and then a -5 volt bias was applied to the substrate in the dark for 5 seconds. No hydrogen evolution was observed under these conditions become. A current of 9 milliamps flowed. Next, a 5 volt negative bias was applied to the substrate for 5 seconds and also the wafer surface was illuminated with an illuminance greater than 2690 lx. A current of 112 mA flowed. Under these conditions, hydrogen evolution took place in two quadrants of the surface. It was the case, however, that the hydrogen evolution in one of these quadrants does not coincide with the impurities which have been entered in FIG. 6D due to capacitor leakage current measurements. Next, a 60 volt negative bias was applied to the wafer for 5 seconds, illuminating the wafer surface with an illuminance of approximately 645 lx. The process according to the invention is carried out at voltages and illuminance levels of this order of magnitude. The pattern of hydrogen bubbles that developed was photographed. The result is shown in FIG. 6A. It can be seen that the impurity locations determined by the bubble test (see Fig. 6A) are in good agreement with those shown in Fig. 6B. The defects are located along the periphery of the substrate and extend into the upper right quadrant of the substrate.

The tests described above were repeated with a sample which was also a copper-polished silicon substrate with a diameter of 82.5 mm and a specific resistance of 2 Ω cm. There was a 5,000 Angstroms thick silicon dioxide layer on the substrate which had been thermally grown at 1,000 ° C. Aluminum points were deposited on the oxide layer and capacitor leakage currents were measured at every third point. A map with the capacitor leakage currents, which are larger than 6 nanoamperes, is shown in FIG. 7B. After the aluminum and oxide had been stripped off, da3

Substrate in the cleaning bath and cleaned in hydrofluoric acid as described above. The vesicle test was then carried out on the sample in test cell 19, using an electrolyte which was a 2% by volume solution of sulfuric acid in deionized water. A 5 volt negative bias was first applied to the silicon substrate in the dark for 5 minutes. No hydrogen evolution was found. A current of 3 mA flowed. When the platelet surface was irradiated for 5 seconds with an illuminance that was greater than 2690 1x, with a negative bias of 5 volts being applied, only a very small amount of hydrogen was formed. A current of 120 mA flowed. A hydrogen bubble pattern was generated under test conditions according to the invention, with a negative bias of 60 volts being applied to the silicon substrate for 5 seconds and the substrate surface being irradiated with an illuminance of approximately 645 1x, as shown in FIG. 7A. It can be seen that there is a good match between the bubble pattern shown in FIG. 7A and the map created based on the capacitor leakage current measurements and shown in FIG. 7B.

Example 4:

Leakage currents were measured and a map of the leakage currents, which are larger than 6 nanoamperes, was created. The ! Map is shown in Fig. 8. The points at which more than 6 nanoamperes were measured were darkened with ink in the photograph.

The aluminum dots and part of the oxide layer were detached from the substrate. An oxide ring extending around the entire periphery of the substrate, from the bottom to the top surface, was left to prevent the electrolyte from shorting the epitaxial layer to the substrate. Such a short-circuit would get in the way of the test. The substrate was cleaned using the method described in Example 3 and then placed in the test cell 19. A negative bias of 60 volts was applied to the substrate for 1 second and the substrate surface was illuminated with an illuminance of approximately 645 lx. The hydrogen bubble pattern (not shown) was photographed. In the photograph you can see the oxide ring at the edge of the substrate where the bubbles stop. There is a good correlation between the two tests, which is particularly evident in the large impurity region in the lower right quadrant of the substrate shown in FIG. 8.

fahren benötigt werden. Für die Verfahren wird eine relativ einfache Testvorrichtung benötigt und mittels üblicher fotografischer Methoden kann die Plättchenqualität leicht dokumentiert werden. Es ist mit dem erfindungsgemäßen Verfahren möglich, zwischen verschiedenen Graden der Störung zu unterscheiden, indem die Zeitdauer, während der die Vorspannung an das Substrat angelegt wird, in festgelegter Weise variiert wird. Die Prüfung kann nicht nur dazu be- nutzt werden, um die Plättchenqualität und den Grad der Störung nach dem Versägen, dem chemischen Dünnen, dem Po- lieren usw. festzustellen, sondern es kann auch dazu benutzt werden, um die Qualität von Epitaxieschichten und/ oder P/N-übergängen zu überprüfen und um den Einfluß von verschiedenen Getterprozessen auf die elektrischen Defekte zu ermitteln.In the above, a non-destructive method for the rapid determination of the electrical quality of semiconductor substrates and large-area P / N junctions was presented. As can be seen from the explanations, it can easily be compared to the

driving are needed. A relatively simple test device is required for the methods, and the platelet quality can be easily documented using conventional photographic methods. With the method according to the invention, it is possible to differentiate between different degrees of disturbance by varying the time period during which the bias voltage is applied to the substrate in a fixed manner. The test can not only be used to determine the platelet quality and the degree of disruption after failure, chemical thinning, polishing, etc., but can also be used to determine the quality of epitaxial layers and / or P / N transitions to check and to determine the influence of different getter processes on the electrical defects.

Claims (10)

1. A method for locating electrically active defects in a single-crystalline semiconductor substrate, the semiconductor substrate being placed in a dilute electrolyte solution, biased negatively against it and illuminated, characterized in that the. Substrate surface is illuminated with an illuminance in the range between about 538 and about 807 lx that the substrate (21) is biased for a specified 'time compared to the electrolyte solution (23) with a voltage in the range between about 50 and about 65 volts, so that Develop hydrogen bubbles at the electrically active fault locations and that the position of the hydrogen bubbles is registered. 2. The method according to claim 1, characterized in that an aqueous acid solution is used as the electrolyte solution. 3. The method according to claim 2, characterized in that an acid from the group of sulfuric acid, hydrofluoric acid and acetic acid is used. 4. The method according to claim 3, characterized in that an aqueous, about 1 to about 2.5 vol.%; Sulfuric acid solution is used. 5. The method according to one or more of claims 1 to 4, characterized in that the voltage is applied between about 1 and about 15 seconds. 6. The method according to one or more of claims 1 to 5, characterized; that the hydrogen bubbles and their location are recorded photographically. 7. The method according to one or more of claims 1 to 6, characterized in that it is applied to a P-type semiconductor substrate. 8. The method according to claim 7, characterized in that it is applied to substrates made of silicon or germanium. 9. The method according to one or more of claims 1 to 8, characterized in that it is applied to a semiconductor substrate which contains at least one P / N junction. 10. The method according to claim 9, characterized in that it is applied to a P-type semiconductor substrate to which an N-type epitaxial layer is applied.

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