EA041302B1 - METHOD AND DEVICE FOR FREQUENCY MODULATION OF COMPUTING DEVICE MICROCIRCUIT, HASH BOARD, COMPUTING DEVICE AND DATA CARRIER - Google Patents

Description

Background of the Invention

The present invention relates to the field of frequency modulation of a computing device chip and, in particular, to a method and apparatus for frequency modulation of a computing device chip, a hash board, a computing device and a storage medium.

State of the art

In general, a large number of work chips are embedded in a large data computing device, and due to limitations in the manufacturing process of work chips, the performance, hash rate, and frequency of various work chips differ. Meanwhile, one working chip is often formed from many individual cores, and differences such as process variation and voltage drop at different positions of the working chip also make it possible to distinguish the actual performance of the respective cores. With regard to the differences in performance of various operating chips and cores, the urgent task is to find a way to dynamically modulate the actual desired operating chip frequencies and establish self-adaptive circuits of the respective cores. The frequencies that are supplied to each working chip and core in a modern computing device are coordinated, so it is impossible to take advantage of the computing advantages of a high performance core, and a low performance core affects the performance of working chips, thereby affecting the performance of the computing device as a whole.

In addition, Chinese Patent Application CN201611169618.6 discloses a serial power chip and system, a virtual digital mining machine, and a server comprising a regulator circuit connected to the serial power chips, respectively, and adjusting the voltages, temperatures, or frequencies of the chips with sequential power supply. By adjusting the frequencies of the respective series-powered chips, the regulator circuit determines whether the operating state of the units to be powered in the series-powered chips is normal, according to a predetermined cycle with respect to the serial-powered chips, and if the working state the state of the units to be powered is abnormal, raises or lowers the operating frequencies of the units to be powered in the abnormal running state according to the specified frequency step within the specified frequency range. According to the state indicated in the status register of the unit to be energized, it is determined whether the operation state of the unit to be energized is normal, and the state indicated by the status register includes the voltage state, the temperature state, and the operating frequency state; or according to the feedback data from the data sent from the units to be powered to the unit to be powered, it is determined whether the operation state of the unit to be powered is normal.

In one embodiment disclosed in Chinese Patent Application CN201611169618.6, when adjusting the frequencies of the respective series-powered chips, the regulator circuit, as the frequency regulator circuit, can specifically determine whether the operating state of the units to be energized is in series-powered chips, normal, by means of a detector according to a predetermined cycle with respect to serial-powered chips, and if the working state of the units to be powered is abnormal, it can specifically increase or decrease the operating frequencies of the units to be powered, in an abnormal working state, by the detector according to the specified frequency step within the specified frequency range. As you can see, document CN201611169618.6 discloses that the regulator can adjust chip frequencies, but only adjusts the operating frequencies of the chips according to operating conditions, for example, depending on whether the blocks that need to receive power are normally sending and receiving data. , depending on the voltage state, temperature state and frequency state, and the frequency control mechanism lacks accuracy and cannot fully achieve the performance of the chips.

Summing up, it is obvious that the solutions of the prior art have inconveniences and disadvantages in practical use, so improvements need to be made.

Brief summary of the present invention

In view of the above disadvantages, it is an object of the present invention to provide a method and apparatus for modulating the frequency of a computing device chip, a hashboard, a computing device and a storage medium, which can automatically modulate the frequency corresponding to each core according to the actual computing performance of each core in the working computing device chip. , thereby maximizing the computing performance of the cores and improving the performance of the working chip and the working device as a whole.

The present invention proposes a method for modulating the frequency of a computer chip.

- 1 041302 device, the computing device contains at least one working chip, and the working chip contains a plurality of cores, comprising the following steps:

setting a plurality of operating frequencies for a working chip of the computing device and ensuring that the plurality of cores in the working chip operate at respective operating frequencies;

analysis of the indicator of computing characteristics of each core at its current operating frequency; and modulating the current core operating frequency up or down according to the core performance indicator.

In the chip frequency modulation method according to the present invention, the step of setting a plurality of operating frequencies for a working chip of a computing device and making the plurality of cores in the working chip operate at respective operating frequencies further comprises:

setting a plurality of operating frequencies for the operating chip by a plurality of phase locked loops, the operating frequencies and the phase locked loops are in one-to-one correspondence;

wherein the step of modulating the current core operating frequency up or down according to the core performance indicator further comprises:

modulating the current operating frequency of the core up or down by the phase-locked loops according to the core computing performance indicator.

In the frequency modulation method, the chips according to the present invention, the phase locked loop circuits are located inside or outside the working chip.

In the chip frequency modulation method of the present invention, the difference between adjacent operating frequencies is 1 to 10%.

In the chip frequency modulation method according to the present invention, the step of analyzing the performance indicator of each core at its current operating frequency further provides for the following:

analyzing whether an indicator of core computing performance reaches predetermined first, second, and/or third indicator thresholds during a predetermined modulation period, wherein the first indicator threshold is the same as or different from the second indicator threshold;

wherein the step of modulating the current core operating frequency up or down according to the core performance indicator further comprises:

if the core computing performance indicator reaches the first threshold of the indicator, modulating the current core operating frequency upward to a higher operating frequency;

if the core performance indicator does not reach the second indicator threshold, modulating the current core operating frequency downward to a lower operating frequency; and/or if the core performance indicator reaches the indicator's third threshold, modulating the current core operating frequency down to a lower operating frequency.

The chip frequency modulation method according to the present invention further provides for the following:

if the cores operating at the predetermined at least one optimized operating frequency exceed the predetermined first ratio, stopping the core frequency modulation; or if the number of cores operating at at least one optimized operating frequency is the maximum, stop modulating the core frequencies.

In the chip frequency modulation method according to the present invention, the step of analyzing the performance indicator of each core at its current operating frequency further provides for the following:

analyzing whether the kernel calculation correctness ratio reaches the predetermined first and/or second correctness ratio thresholds during the predetermined modulation period, the first correctness ratio threshold is the same as or different from the second correctness ratio threshold;

wherein the step of modulating the current core operating frequency up or down according to the core performance indicator further comprises:

if the core calculation correctness ratio reaches the first correctness ratio threshold, modulating the current core operating frequency upward to a higher operating frequency; and/or if the core calculation correctness ratio does not reach the second correctness ratio threshold, modulating the current core operating frequency down to a lower operating frequency.

In the chip frequency modulation method according to the present invention, the step of analyzing whether

- 2 041302 whether the kernel calculation correctness ratio reaches the predetermined first and/or second threshold values of the correctness ratio during the predetermined modulation period, further provides for the following:

analyzing whether the random numbers provided by the core are correct during the modulation period;

counting the number of correct random numbers and the number of incorrect core random numbers during the modulation period;

calculating a kernel random number calculation correctness ratio during the modulation period according to the number of correct random numbers and the number of incorrect random numbers, and determining whether the random number calculation correctness ratio reaches predetermined first and/or second correctness ratio thresholds;

wherein the step of modulating the current core operating frequency up or down according to the core performance indicator further comprises:

if the core random number calculation correctness ratio reaches the first correctness ratio threshold value, modulating the current core operating frequency upward to a higher operating frequency; and/or if the core random number calculation correctness ratio does not reach the second correctness ratio threshold, modulating the current core operating frequency down to a lower operating frequency.

In the chip frequency modulation method according to the present invention, the step of analyzing whether the random numbers provided by the core are correct during the modulation period further comprises the following:

calculating, by the core, a first result based on the random numbers by a predetermined algorithm, each time the core provides one random number during the modulation period, the first result contains the first parameter;

calculating, using the working chip tester, a second result based on random numbers using the same algorithm, the second result contains a second parameter;

if the first parameter is the same as the second parameter, determining, by means of a tester, that the random numbers are correct random numbers or the random numbers are incorrect random numbers.

In the frequency modulation method of the chip according to the present invention, the step of analyzing whether the calculation correctness ratio of the core reaches the given threshold values of the correctness ratio during the given modulation period further comprises:

analyzing in real time whether the kernel calculation correctness ratio during the modulation period reaches the first correctness ratio threshold and the second correctness ratio threshold according to a preset real-time modulation instruction;

evaluating whether the kernel calculation correctness ratio during the modulation period reaches the first correctness ratio threshold and the second correctness ratio threshold according to the pre-set advance modulation instruction within the modulation time period set by the advance modulation instruction; or analyzing whether the kernel calculation correctness ratio reaches, during the modulation period, the first correctness ratio threshold and the second correctness ratio threshold according to the received immediate modulation instruction;

wherein the step of modulating the current core operating frequency up or down according to the core performance indicator further comprises:

if the core calculation correctness ratio during the modulation period reaches the first correctness ratio threshold value, real-time modulation of the current core operating frequency upward to a higher operating frequency; if the core calculation correctness ratio during the modulation period does not reach the second correctness ratio threshold, real-time modulation of the current core operating frequency down to a lower operating frequency;

if the core calculation correctness ratio during the modulation period reaches the first correctness ratio threshold during the modulation time period, modulating the current core operating frequency upward to a higher operating frequency; if the core calculation correctness ratio during the modulation period does not reach the second correctness ratio threshold during the modulation time period, modulating the current core operating frequency down to a lower operating frequency; or according to the received immediate modulation instruction, if the core calculation correctness ratio during the modulation period reaches the first correctness ratio threshold, modulating the current core operating frequency up to a higher operating

- 3 041302 frequency; if the core calculation correctness ratio during the modulation period does not reach the second correctness ratio threshold, modulating the current core operating frequency down to a lower operating frequency; according to the received instruction to stop modulation, stop modulation of the current operating frequency of the core.

In the chip frequency modulation method according to the present invention, the step of analyzing the performance indicator of each core at its current operating frequency further comprises the following:

presetting a node reference value, a correct calculation weight, an incorrect calculation weight, a correct calculation threshold, and a core calculation incorrect threshold;

analysis of whether each kernel calculation is correct;

adding one correct calculation weight value to the node reference value each time the core performs at least one correct calculation, and subtracting one incorrect calculation weight value from the node reference value each time the core performs at least one incorrect calculation;

determining whether the reference value of the core node reaches a correct calculation threshold or an incorrect calculation threshold;

wherein the step of modulating the current core operating frequency up or down according to the core performance indicator further comprises:

if the current core node reference value reaches a correct calculation threshold, modulating the current core operating frequency upward to a higher operating frequency;

if the current core node reference value reaches the miscalculation threshold, modulating the current core operating frequency down to a lower operating frequency.

In the chip frequency modulation method according to the present invention, the step of analyzing whether each kernel calculation is correct further comprises the following:

analysis of whether the random numbers provided each time by the kernel are correct;

the step of adding one correct calculation weight value to the node reference value each time the core performs at least one correct calculation, and subtracting one incorrect calculation weight value from the node reference value each time the core performs at least one incorrect calculation, further comprising following:

adding one correct calculation weight value to the node reference value each time the core provides at least one correct random number, and subtracting one incorrect calculation weight value from the node reference value each time the kernel provides at least one incorrect random number.

In the chip frequency modulation method according to the present invention, the step of analyzing whether the random numbers provided each time by the core are correct further comprises the following:

calculating, by the kernel, a first result based on the random numbers by a predetermined algorithm, after the kernel provides one random number, the first result contains the first parameter;

calculating, using the working chip tester, a second result based on random numbers using the same algorithm, the second result contains a second parameter;

if the first parameter is the same as the second parameter, determining, by means of a tester, that the random numbers are correct random numbers or the random numbers are incorrect random numbers.

In the chip frequency modulation method according to the present invention, the method further comprises the following:

setting and adjusting the node reference value, the correct calculation weight, the incorrect calculation weight, the correct calculation threshold and/or the kernel incorrect calculation threshold according to actual requirements, wherein the correct calculation weight is the same as the incorrect calculation weight or different from it, the threshold value of the correct calculation is the same as the threshold value of the incorrect calculation, or different from it;

adjusting an expected acceptable core constant deviation ratio by adjusting a ratio of a correct calculation weight to an incorrect calculation weight;

adjusting the modulation period by adjusting the absolute value of the correct calculation weight and the incorrect calculation weight;

adjusting the modulation period by adjusting the absolute value of the correct calculation threshold and the incorrect calculation threshold.

In the chip frequency modulation method according to the present invention, the constant deviation ratio calculation formula is as follows: the constant deviation ratio equals the weight

- 4 041302 to the total value of the correct calculation divided by the sum of the weight value of the correct calculation and the weight value of the incorrect calculation.

In the chip frequency modulation method according to the present invention, the step of determining whether the reference value of the core node reaches the correct calculation threshold or the incorrect calculation threshold further comprises:

determining in real time whether a reference value of the core node reaches a correct calculation threshold or an incorrect calculation threshold according to a preset real-time modulation instruction;

determining whether a reference value of the core node reaches a correct calculation threshold or an incorrect calculation threshold according to a predetermined advance modulation instruction within a modulation time period set by the advance modulation instruction; or analyzing whether the reference value of the core node reaches a correct calculation threshold or an incorrect calculation threshold according to the received immediate modulation instruction;

wherein the step of modulating the current core operating frequency up or down according to the core performance indicator further comprises:

if the current reference value of the core node reaches the threshold value of the correct calculation, real-time modulation of the current operating frequency of the core upward to a higher operating frequency; if the current core node reference value reaches a miscalculation threshold, real-time modulation of the current core operating frequency down to a lower operating frequency;

if the current reference value of the core node reaches the threshold value of the correct calculation in the modulation time period, modulating the current core operating frequency upward to a higher operating frequency; if the current core node reference value reaches the miscalculation threshold in the modulation time period, modulating the current core operating frequency down to a lower operating frequency; or according to the received immediate modulation instruction, if the current core node reference value reaches the correct calculation threshold, modulating the current core operating frequency upward to a higher operating frequency; if the current reference value of the core node reaches the miscalculation threshold, modulating the current core operating frequency downward to a lower operating frequency; according to the received instruction to stop modulation, stop modulation of the current operating frequency of the core.

In the chip frequency modulation method according to the present invention, after the step of modulating the current core operating frequency up or down according to the core performance indicator, the method further comprises the following:

determining the current state of the allocation of cores after modulating the frequency at the respective operating frequencies;

frequency modulation at the operating frequency according to the current distribution state and the specified frequency modulation mechanism of the cores, the frequency modulation mechanism is the correspondence between the distribution state and the frequency modulation of the cores.

In the chip frequency modulation method according to the present invention, the operating frequency provides at least one high operating frequency, at least one medium operating frequency, and at least one low operating frequency, the maximum frequency at the high operating frequency is the maximum operating frequency, the minimum frequency at low operating frequency represents the minimum operating frequency;

the frequency modulation step at the operating frequency according to the current distribution state and the predetermined core frequency modulation mechanism further provides for the following:

if cores exceeding the predetermined second ratio operate at at least one high operating frequency, changing at least one operating frequency to at least one optimized high operating frequency, wherein the frequency at the optimized high operating frequency is higher than the frequency at the maximum operating frequency; and/or if cores greater than the predetermined third ratio operate at at least one low operating frequency, changing at least one operating frequency to at least one optimized low operating frequency, wherein the frequency at the optimized low operating frequency is lower than the frequency at the minimum operating frequency. frequency.

In the chip frequency modulation method according to the present invention, the step of changing at least one operating frequency to at least one optimized high operating frequency if cores greater than the predetermined second ratio operate at at least one high operating frequency further comprises:

if the cores exceeding the second ratio are running at the maximum operating frequency, changing one operating frequency to one optimized high operating frequency; and/or

- 5 041302 the step of changing at least one operating frequency to at least one optimized low operating frequency, if cores exceeding the predetermined third ratio operate at least one low operating frequency, further provides for the following:

if cores greater than the third ratio are running at the minimum operating frequency, change one operating frequency to one optimized low operating frequency.

In the chip frequency modulation method according to the present invention, the operating frequency provides at least one high operating frequency, at least one medium operating frequency, and at least one low operating frequency, the maximum frequency at the high operating frequency is the maximum operating frequency, the minimum frequency at low operating frequency represents the minimum operating frequency;

the frequency modulation step at the operating frequency according to the current distribution state and the predetermined frequency modulation mechanism further provides for the following:

if the number of cores running at least one high operating frequency is the maximum, changing at least one operating frequency to at least one optimized high operating frequency, wherein the frequency at the optimized high operating frequency is higher than the frequency at the maximum operating frequency; and/or if the number of cores operating at at least one low operating frequency is the maximum, changing at least one operating frequency to at least one optimized low operating frequency, wherein the frequency at the optimized low operating frequency is lower than the frequency at the minimum operating frequency .

In the chip frequency modulation method according to the present invention, the step of changing at least one operating frequency to at least one optimized high operating frequency, if the number of cores operating at at least one high operating frequency is the maximum, further comprises the following:

if the number of cores running at the maximum operating frequency is the maximum, changing one operating frequency to one optimized high operating frequency; and/or the step of changing at least one operating frequency to at least one optimized low operating frequency, if the number of cores operating at at least one low operating frequency is the maximum, further provides for the following:

if the number of cores running at the minimum operating frequency is the maximum, change one operating frequency to one optimized low operating frequency.

In the chip frequency modulation method according to the present invention, the operating frequency includes at least one high operating frequency, at least one medium operating frequency, and at least one low operating frequency;

the frequency modulation step at the operating frequency according to the current distribution state and the predetermined frequency modulation mechanism further provides for the following:

if cores exceeding the predetermined fourth ratio operate at least one middle operating frequency, stopping the frequency modulation at the operating frequency; or if the number of cores operating at at least one average operating frequency is the maximum, stopping the frequency modulation at the operating frequency.

In the chip frequency modulation method according to the present invention, the computing device is configured to mine a virtual digital currency.

The present invention also provides an apparatus for frequency modulation of a computing device chip, the computing device comprising at least one working chip, the working chip comprising a plurality of cores comprising:

a frequency setting module for setting a plurality of operating frequencies for a working chip of the computing device and allowing the plurality of cores in the working chip to operate at respective operating frequencies;

a computing performance analysis module for analyzing a performance indicator of each core at its current operating frequency; and a frequency modulation module for modulating the current operating frequency of the core up or down according to the core performance indicator.

In the chip frequency modulation apparatus of the present invention, the frequency setting unit sets a plurality of operation frequencies for the operation chip through a plurality of phase-locked loops, the operation frequencies and the phase-locked loops are in one-to-one correspondence; the frequency modulation module modulates the current operating frequency of the core up or down by the phase locked loop circuits according to the indicator of the core computing performance.

In the frequency modulation apparatus of the present invention, the phase locked loop circuits are located inside or outside the working chip.

In the chip frequency modulation apparatus of the present invention, the difference between adjacent operating frequencies is 1 to 10%.

- 6 041302

In the chip frequency modulation apparatus according to the present invention, the computational performance analysis module analyzes whether the indicator of the core computational performance reaches the predetermined first, second, and/or third indicator thresholds during the predetermined modulation period, wherein the first indicator threshold is the same as the second threshold. indicator, or different from it;

if the core computing performance indicator reaches the first indicator threshold, the frequency modulation module modulates the current core operating frequency up to a higher operating frequency;

if the core performance indicator does not reach the second indicator threshold, the frequency modulation module modulates the current core operating frequency down to a lower operating frequency; and/or if the core performance indicator reaches the indicator's third threshold, the frequency modulation module modulates the current core operating frequency down to a lower operating frequency.

In the chip frequency modulation apparatus according to the present invention, the frequency modulation module further comprises:

a frequency modulation submodule for modulating a current core operating frequency up or down according to a core performance indicator;

a frequency modulation stop submodule for stopping the frequency modulation of the cores if the cores running at the predetermined at least one optimized operating frequency exceed the predetermined first ratio; or to stop modulating the frequencies of the cores if the number of cores running at least one optimized operating frequency is the maximum.

In the frequency modulation apparatus of the chip according to the present invention, the computational performance analysis module analyzes whether the calculation correctness ratio of the core reaches the predetermined first and/or second correctness ratio threshold values during the predetermined modulation period, the first correctness ratio threshold being the same as the second threshold value the relationship of correctness, or differs from it;

the frequency modulation module modulates the current operating frequency of the core upward to a higher operating frequency if the core calculation correctness ratio reaches the first correctness ratio threshold; and/or modulates the current core operating frequency down to a lower operating frequency if the core calculation correctness ratio does not reach the second correctness ratio threshold.

In the chip frequency modulation apparatus of the present invention, the computational performance analysis module further comprises:

a first analysis sub-module for analyzing whether the random numbers provided by the core are correct during the modulation period;

a counting sub-module for counting the number of correct random numbers and the number of incorrect core random numbers during the modulation period; and a first determination module for calculating a core random number calculation correctness ratio during the modulation period according to the number of correct random numbers and the number of incorrect random numbers, and determining whether the random number calculation correctness ratio reaches predetermined first and/or second correctness ratio threshold values;

wherein the frequency modulation module is configured to modulate the current core operating frequency upward to a higher operating frequency if the core random number calculation correctness ratio reaches a first correctness ratio threshold; and/or modulating the current core operating frequency down to a lower operating frequency if the kernel random number calculation correctness ratio does not reach a second correctness ratio threshold.

In the chip frequency modulation apparatus according to the present invention, the first analysis sub-module further comprises:

a first calculation unit for calculating a first result based on the random numbers by a predetermined algorithm, each time the core provides one random number during the modulation period, the first result contains the first parameter, the first calculation unit is provided in the core; and a first checker for calculating a second result based on the random numbers by the same algorithm, the second result contains the second parameter, and if the first parameter is the same as the second parameter, for determining that the random number is a valid random number or random number is a wrong random number, the first check block is provided in the working chip.

In the chip frequency modulation apparatus according to the present invention, the computing performance analysis module analyzes in real time whether the ratio reaches

- 7 041302 Determining the correctness of the calculation of the core during the modulation period of the first threshold value of the correctness ratio and the second threshold value of the correctness ratio, according to a preset real-time modulation instruction;

the computational performance analysis unit analyzes whether the core calculation correctness ratio during the modulation period reaches the first correctness ratio threshold and the second correctness ratio threshold according to the pre-set advance modulation instruction within the modulation time period set by the advance modulation instruction; or the computational performance analysis module analyzes whether the core calculation correctness ratio during the modulation period reaches the first correctness ratio threshold and the second correctness ratio threshold according to the received immediate modulation instruction;

the frequency modulation module modulates in real time the current operation frequency of the core upward to a higher operation frequency if the core calculation correctness ratio during the modulation period reaches the first correctness ratio threshold; and modulating in real time the current operating frequency of the core down to a lower operating frequency if the core calculation correctness ratio during the modulation period does not reach the second correctness ratio threshold;

the frequency modulation module modulates the current operating frequency of the core up to a higher operating frequency if the core calculation correctness ratio during the modulation period reaches the first threshold value of the correctness ratio during the modulation time period; and modulating the current operating frequency of the core down to a lower operating frequency if the core calculation correctness ratio during the modulation period does not reach the second threshold value of the correctness ratio during the modulation time period; or the frequency modulation module, according to the received immediate modulation instruction, modulates the current operating frequency of the core up to a higher operating frequency if the core calculation correctness ratio during the modulation period reaches the first correctness ratio threshold; modulates the current operating frequency of the core down to a lower operating frequency if the ratio of correctness of the calculation of the core during the modulation period does not reach the second threshold value of the ratio of correctness; and stops modulating the current core operating frequency according to the received modulation stop instruction.

In the chip frequency modulation apparatus of the present invention, the computational performance analysis module further comprises:

a setting sub-module for presetting a node reference value, a correct calculation weight, an incorrect calculation weight, a correct calculation threshold, and a core calculation incorrect threshold;

a second analysis sub-module for analyzing whether each kernel calculation is correct;

a counting submodule for adding one correct calculation weight value to the node reference value each time the core performs at least one correct calculation, and subtracting one incorrect calculation weight value from the node reference value each time the core performs at least one incorrect calculation; and a second determination sub-module for determining whether the reference value of the core node reaches a correct calculation threshold or an incorrect calculation threshold;

wherein the frequency modulation module is configured to modulate the current core operating frequency upward to a higher operating frequency if the current reference value of the core node reaches a correct calculation threshold; and modulating the current core operating frequency down to a lower operating frequency if the current core node reference value reaches a miscalculation threshold.

In the chip frequency modulation apparatus according to the present invention, the second analysis sub-module analyzes whether the random numbers provided each time by the core are correct;

the scoring submodule adds one correct calculation weight to the node reference value each time the kernel provides at least one correct random number, and subtracts one incorrect calculation weight from the node reference value each time the kernel provides at least one incorrect random number .

In the frequency modulation device of the chip according to the present invention, the second analysis sub-module further comprises:

a second calculation unit for computing, by the kernel, a first result based on the random number by a predetermined algorithm, after the kernel provides one random number, the first result contains the first parameter; and a second checker for calculating a second result based on the random number by the same algorithm, the second result contains the second parameter; and if the first parameter is

- 8 041302 same as the second parameter for determining whether the random number is a correct random number or the random number is an incorrect random number.

In the chip frequency modulation apparatus according to the present invention, the setting sub-module sets and adjusts the node reference value, the correct calculation weight, the incorrect calculation weight, the correct calculation threshold, and/or the kernel incorrect calculation threshold according to actual requirements, wherein the correct calculation weight is the same as or different from the incorrect calculation weight, the correct calculation threshold is the same as or different from the incorrect calculation threshold;

the setting sub-module adjusts the expected acceptable kernel constant deviation ratio by adjusting the ratio of the correct calculation weight value to the incorrect calculation weight value;

the setting submodule adjusts the modulation period by adjusting the absolute value of the correct calculation weight and the incorrect calculation weight;

the setting submodule adjusts the modulation period by adjusting the absolute value of the correct calculation threshold and the incorrect calculation threshold.

In the chip frequency modulation apparatus according to the present invention, the constant deviation ratio calculation formula is as follows: the constant deviation ratio equals the correct calculation weight value divided by the sum of the correct calculation weight value and the incorrect calculation weight value.

In the chip frequency modulation apparatus according to the present invention, the computational performance analysis module determines in real time whether the reference value of the core node reaches the correct calculation threshold or the incorrect calculation threshold according to a preset real-time modulation instruction;

the computational performance analysis module determines whether the reference value of the core node reaches the correct calculation threshold or the incorrect calculation threshold according to the preset advance modulation instruction within a modulation time period set by the advance modulation instruction; or the computational performance analysis module analyzes whether the reference value of the core node reaches a correct calculation threshold or an incorrect calculation threshold according to the received immediate modulation instruction;

the frequency modulation module modulates in real time the current operating frequency of the core up to a higher operating frequency if the current reference value of the core node reaches a threshold value of correct calculation; and modulating in real time the current operating frequency of the core down to a lower operating frequency if the current reference value of the core node reaches a miscalculation threshold;

the frequency modulation module modulates the current operating frequency of the core up to a higher operating frequency if the current reference value of the core node reaches a correct calculation threshold in the modulation time period; and modulating the current core operating frequency down to a lower operating frequency if the current core node reference value reaches a miscalculation threshold in the modulation time period; or the frequency modulation module, according to the received immediate modulation instruction, modulates the current core operating frequency upward to a higher operating frequency if the current core node reference value reaches a correct calculation threshold; modulates the current operating frequency of the core down to a lower operating frequency if the current reference value of the core node reaches a miscalculation threshold; and stops modulating the current core operating frequency according to the received modulation stop instruction.

In the chip frequency modulation tool according to the present invention, the tool further comprises:

a frequency determination module for determining the current state of the distribution of cores after frequency modulation at the respective operating frequencies;

frequency modulation module to modulate the frequency at the operating frequency according to the current distribution state and the specified frequency modulation mechanism of the cores, the frequency modulation mechanism is the correspondence between the distribution state and the frequency modulation of the cores.

In the chip frequency modulation apparatus of the present invention, the operating frequency provides at least one high operating frequency, at least one medium operating frequency, and at least one low operating frequency, the maximum frequency at the high operating frequency is the maximum operating frequency, the minimum frequency at low operating frequency is the minimum operating frequency;

the frequency modulation module additionally contains:

the first frequency modulation submodule to change at least one operating frequency according to

- 9 041302 at least one optimized high operating frequency, if the cores exceeding the predetermined second ratio operate at least one high operating frequency, and the frequency at the optimized high operating frequency is higher than the frequency at the maximum operating frequency; and/or a second frequency modulation submodule for changing at least one operating frequency to at least one optimized low operating frequency if cores greater than the predetermined third ratio operate at at least one low operating frequency, wherein the frequency is at the optimized low operating frequency below the frequency at the minimum operating frequency.

In the chip frequency modulation apparatus according to the present invention, the first frequency modulation submodule changes one operating frequency to one optimized high operating frequency if the cores exceeding the second ratio operate at the maximum operating frequency; and/or the second frequency modulation submodule changes one operating frequency to one optimized low operating frequency if cores greater than the third ratio operate at the minimum operating frequency.

In the chip frequency modulation apparatus of the present invention, the operating frequency provides at least one high operating frequency, at least one medium operating frequency, and at least one low operating frequency, the maximum frequency at the high operating frequency is the maximum operating frequency, the minimum frequency at low operating frequency is the minimum operating frequency;

the frequency modulation module additionally contains:

a third frequency modulation submodule for changing at least one operating frequency to at least one optimized high operating frequency, if the number of cores operating at at least one high operating frequency is the maximum, and the frequency at the optimized high operating frequency is higher than the frequency at the maximum operating frequency; and/or a fourth frequency modulation submodule for changing at least one operating frequency to at least one optimized low operating frequency, if the number of cores operating at at least one low operating frequency is the maximum, and the frequency at the optimized low operating frequency is lower frequency at the minimum operating frequency.

In the chip frequency modulation apparatus of the present invention, the third frequency modulation submodule changes one operating frequency to one optimized high operating frequency if the number of cores operating at the maximum operating frequency is the maximum; and/or the fourth frequency modulation submodule changes the operating frequency to one optimized low operating frequency if the number of cores operating at the minimum operating frequency is the maximum.

In the chip frequency modulation apparatus of the present invention, the operating frequency includes at least one high operating frequency, at least one medium operating frequency, and at least one low operating frequency;

the frequency modulation module additionally contains:

a first modulation stop module for stopping frequency modulation at an operating frequency if cores larger than a predetermined fourth ratio operate at at least one middle operating frequency; or a second modulation stop module for stopping the frequency modulation at the operating frequency if the number of cores operating at the at least one middle operating frequency is the maximum.

In the frequency modulating device of the chip according to the present invention, the frequency modulating device of the chip is located inside or outside the working chip.

In the chip frequency modulation apparatus according to the present invention, the computing device is configured to mine a virtual digital currency.

The present invention further provides a hash board comprising any of the frequency modulation devices of the chip.

The present invention further provides a computing device comprising any of the chip frequency modulation devices.

The present invention further provides a computer program carrier for storing a computer program, wherein, when executed by a processor, the program implements a frequency modulation method for a computing device chip, the computing device comprises at least one working chip, and the working chip comprises a plurality of cores, the method comprising:

setting a plurality of operating frequencies for a working chip of the computing device and ensuring that the plurality of cores in the working chip operate at respective operating frequencies;

analysis of the indicator of computing characteristics of each core at its current operating frequency; and modulating the current core operating frequency up or down according to the core performance indicator.

- 10 041302

According to the present invention, the frequencies of the cores of the working microcircuit of the computing device are automatically modulated, and first a set of suitable operating frequencies are set and the plurality of cores in the working microcircuit are operated at the corresponding operating frequencies, and then the current operating frequency of the core is modulated up or down according to the indicator of the computing performance of each cores at the current operating frequency, i.e. upward modulation of the high performance core and downward modulation of the low performance core. Thus, according to the present invention, the frequency corresponding to each core is automatically modulated according to the actual computing performance of each core in the working chip of the computing device, thereby maximizing the computing performance of the cores and improving the performance of the working chip and the working device as a whole.

Brief description of the figures

In FIG. 1 is a schematic diagram of a frequency modulating device for a computing device chip according to the present invention.

In FIG. 2 is a circuit diagram of the frequency modulation apparatus of the computing device chip according to the first embodiment of the present invention.

In FIG. 3 is a schematic diagram of a frequency modulation apparatus for a computing device chip according to a second embodiment of the present invention.

In FIG. 4 is a schematic diagram of a frequency modulation apparatus for a computing device chip according to a third embodiment of the present invention.

In FIG. 5 is an exemplary parameter setting diagram according to the third embodiment of the present invention.

In FIG. 6 is a schematic diagram of a frequency modulation apparatus for a computing device chip according to a fourth embodiment of the present invention.

In FIG. 7 is a state diagram of the distribution of cores operating at respective operating frequencies according to the fourth embodiment of the present invention.

In FIG. 8 is a flow diagram of a method for frequency modulating a computing device chip according to the present invention.

In FIG. 9 is a flowchart of the frequency modulation method of the computing device chip according to the first embodiment of the present invention.

In FIG. 10 is a flowchart of the frequency modulation method of the computing device chip according to the second embodiment of the present invention.

In FIG. 11 is a flowchart of a preferred frequency modulation method of a computing device chip according to the second embodiment of the present invention.

In FIG. 12 is a flowchart of the frequency modulation method of the computing device chip according to the third embodiment of the present invention.

In FIG. 13 is a flowchart of a preferred frequency modulation method of a computing device chip according to the third embodiment of the present invention.

In FIG. 14 is a flowchart of the frequency modulation method of the computing device chip according to the fourth embodiment of the present invention.

In FIG. 15 is a block diagram of one preferred frequency modulation method of a computing device chip according to a fourth embodiment of the present invention.

In FIG. 16 is a flow chart of a second preferred frequency modulation method of a computing device chip according to a fourth embodiment of the present invention.

In FIG. 17 is a schematic diagram of a computing device according to the present invention.

Preferred Embodiments of the Present Invention

The present invention is further described in detail with reference to the accompanying drawings, as well as embodiments, to explain the purpose, technical solution and their advantages. It should be understood that the detailed embodiments described herein are only intended to explain the present invention and not to limit it.

It should be noted that references to one embodiment, embodiments, exemplary embodiment, and the like. in the disclosure refer to the fact that this embodiment may include specific features, structures, or characteristics, but it is not necessary for each embodiment to include those features, structures, or characteristics. In addition, such an expression does not refer to the same embodiment. In addition, with reference to specific features, structures, or characteristics described in this embodiment, whether explicitly described or not, it is believed that the incorporation of specific functions, structures, or characteristics into other embodiments is within the knowledge of those skilled in the art. this field of technology.

In addition, in the description and the following claims, certain terms are used to refer to certain components or details. Specialists in the field of technology

- 11 041302 must understand that the manufacturer may give a different name to the same component or part. In the description and the following claims, components or parts are distinguished from each other by the different functions of the components, and not by names. The terms contain and include, as used throughout the specification and the following claims, are open terms and are meant to include without limitation. In addition, the connection in this document includes any means of direct or indirect electrical connection. Means of indirect electrical connection includes connection through other devices.

In FIG. 1 is a schematic diagram of a frequency modulating device for a computing device chip according to the present invention. The computing device is preferably designed to work with data arrays, for example, to mine a virtual digital currency. The computing device includes at least one working chip, and the working chip contains a plurality of cores 80. Preferably, the computing device includes a control board and a hash board connected to the control board, and the hash board contains at least one working chip, and the working chip contains a plurality of cores 80. Of course, the computing device may also include a heatsink, a connection board, a power supply module, and the like.

It should be noted that the frequency modulation method of the chip according to the present invention actually refers to two levels of the frequency modulation mechanism, i.e. the frequency modulation mechanism of the working microcircuit and the frequency modulation mechanism at the core level. The frequency modulation mechanism of the working chip refers to setting a plurality of suitable operating frequencies for each working chip, and ensuring that the respective cores 80 of the working chip operate at the respective operating frequencies, thereby fully achieving the performance of each core 80. The core-level frequency modulation mechanism refers to modulating the cores 80 according to suitable operating frequencies according to the actual computing performance of the core 80, the frequency modulation of the high performance core 80 upwards and the frequency modulation of the low computing performance core 80 downwards, thereby fully achieving the computing performance of each core 80.

The chip frequency modulation tool 100 at least includes a frequency setting module 10 , a computing performance analysis module 20 , and a frequency modulation module 30 .

The frequency setting unit 10 sets a plurality of operating frequencies for a working chip of the computing device, and causes the plurality of cores 80 in the working chip to operate at respective operating frequencies, the frequencies at each operating frequency being different from each other.

Those. a plurality of different operating frequencies are set for each work chip, and the respective work chip cores 80 are set to operate at respective work frequencies according to the work chip frequency modulation mechanism. For example, six operating frequencies are set: 500, 550, 600, 650, 700 and 750 MHz. The number of operating frequencies and the spacing between frequencies according to the present invention can be set according to actual requirements, and the more operating frequencies, the more likely the computing performance of the respective cores 80 will be fully achieved. When the frequency modulation switch is turned on (without frequency modulation of the cores 80) , cores 80 may be uniformly distributed, non-uniformly distributed, or randomly distributed to operate at operating frequencies depending on a predetermined rule. Preferably, the frequency setting unit 10 can set a plurality of operating frequencies for a working chip through a plurality of phase locked loop circuits 70 shown in FIG. 2. Of course, the frequency setting unit 10 can also set a plurality of operating frequencies for the operating chip through other hardware or software.

The computing performance analysis module 20 analyzes the performance indicator of each core 80 at its current operating frequency. The computing performance indicator represents the actual computing performance of the core 80 at the current operating frequency, and includes, without limitation, calculation correctness ratio, number of correct calculations, calculation speed, and the like. If the performance indicator of core 80 is high, it means that the performance of core 80 can be improved, and if the performance indicator of core 80 is low, it means that the performance of core 80 may not be sufficient to operate at the frequency corresponding to the current operating frequency.

The frequency modulation unit 30 modulates the current operating frequency of the core 80 up or down according to an indication of the computing performance of the core 80 at the current operating frequency. Those. according to the core-level frequency modulation mechanism, the core 80 is modulated according to a suitable operating frequency according to the actual computing performance of the core 80, the frequency of the core 80 with high computing performance is modulated upwards, and the frequency of the core 80 with poor computing performance is modulated downwards , thereby fully achieving the computing performance of each core 80. Preferably, the frequency modulation of the core 80 is performed periodically; if the calculation correctness ratio of the core 80 during the frequency modulation period reaches the first threshold value of the correctness ratio, this indicates that the core 80 does not achieve the best computing performance.

- 12 041302 ristic, as a result of which the current operating frequency of the core 80 is modulated upward to a higher operating frequency, and if the calculation correctness ratio of the core 80 during the frequency modulation period does not reach the second threshold value of the correctness ratio, this indicates that the computational characteristics of the core 80 is not enough to operate at the current operating frequency, as a result of which the current operating frequency of the core 80 is modulated downward to a lower operating frequency.

The device 100 for modulating the frequency of the chip according to the present invention may be located inside or outside the working chip. According to the present invention, the operating frequency of the core 80 is estimated, the corresponding frequency of the core 80 is modulated, the computational advantages of the high performance core 80 are fully achieved, the low performance core is prevented from affecting the performance of the working chip, and the computing performance of the respective cores 80 is maximized according to the actual computing performance of the respective 80 cores in the working chip, thereby increasing the calculation speed and the ratio of correct calculation of the working chip and the computing device as a whole. Moreover, in the core 80 of the working chip according to the present invention, there is no frequency hopping, and the working frequency is relatively stable.

In FIG. 2 is a circuit diagram of the frequency modulation apparatus of the computing device chip according to the first embodiment of the present invention. The computing device is preferably designed to work with data arrays, for example, to mine a virtual digital currency. Preferably, the computing device comprises a control board and a hash board connected to the control board, wherein the hash board contains at least one working chip, and the working chip contains a plurality of cores 80. Of course, the computing device may also contain a heat sink, a connection board, a power module and so on. The chip frequency modulation tool 100 at least includes a frequency setting module 10 , a computing performance analysis module 20 , and a frequency modulation module 30 .

The frequency setting unit 10 sets a plurality of operating frequencies for the operating chip through a plurality of phase locked loop circuits 70, and causes the plurality of cores 80 in the operating chip to operate at respective operating frequencies, the frequencies at the respective operating frequencies differ from each other, operating frequencies and phase locked loops 70 frequencies are in one-to-one correspondence. Preferably, the phase locked loop circuits 70 are located inside or outside the working chip. The number of respective operating frequencies and the interval between frequencies according to the present invention can be set according to actual requirements, and the more operating frequencies, the more likely the computing performance of the respective cores 80 will be fully achieved. For example, six operating frequencies are set: 500, 550, 600, 650, 700 and 750 MHz. Thus, according to the present invention, more phase-locked loops 70 can be configured to provide more operating frequencies, thereby fully achieving the computing performance of the respective cores 80.

It should be noted that the difference between operating frequencies according to the present invention can be controlled within an acceptable range, because when the core 80 improves by one operating frequency, the operating frequency of the core improves by one difference between frequencies, thereby improving certain computing performance due to the increase in speed. calculations. However, improving the operating frequency of the core may cause a loss of certain computational characteristics due to a decrease in the calculation correctness ratio. Thus, the frequency setting unit 10 must properly adjust the difference between adjacent operating frequencies so that when the core 80 is modulated up from the current operating frequency to a higher operating frequency, the computational benefit of the core 80 is greater than this loss. Preferably, the difference between adjacent operating frequencies is between 1 and 10%.

The computing performance analysis module 20 analyzes the performance indicator of each core 80 at its current operating frequency. The computing performance indicator represents the actual computing performance of the core 80 at the current operating frequency, and includes, without limitation, calculation correctness ratio, number of correct calculations, calculation speed, and the like. If the performance indicator of core 80 is high, it means that the performance of core 80 can be improved, and if the performance indicator of core 80 is low, it means that the performance of core 80 may not be sufficient to operate at the frequency corresponding to the current operating frequency. Preferably, the computational performance analysis module 20 analyzes whether the indicator of the computing performance of the core 80 reaches the predetermined first, second, and/or third indicator thresholds in a predetermined modulation period, wherein the first indicator threshold is the same as or different from the second indicator threshold.

The frequency modulation unit 30 modulates the current operating frequency of the core 80 up or down by the phase-locked loops 70 according to the calculation indicator.

- 13 041302 characteristics of the core 80. Of course, the frequency modulation module 30 can also modulate the current operating frequency of the core 80 up or down through other hardware or software. Preferably, if the indicator of the computing performance of the core 80 reaches the first indicator threshold, the frequency modulation module 30 modulates the current operating frequency of the core 80 up to a higher operating frequency; and/or if the performance indicator of the core 80 does not reach the second indicator threshold, the frequency modulation module 30 modulates the current operating frequency of the core 80 down to a lower operating frequency; and/or if the performance indicator of the core 80 reaches the third indicator threshold, the frequency modulation module 30 modulates the current operating frequency of the core 80 down to a lower operating frequency.

For example, consider the expression for example, six operating frequencies are set to 500, 550, 600, 650, 700, and 750 MHz, for example, the current operating frequency of core 80 is 600 MHz, the computational performance indicator is the ratio of the calculation correctness of core 80 during the modulation period, and the first the indicator threshold and the second indicator threshold are both 90%. If the calculation accuracy ratio of the core 80 during the modulation period reaches 90%, it means that the computing performance of the core 80 is satisfactory, so the current operating frequency of 600 MHz of the core 80 is modulated up to a higher operating frequency of 650 MHz. If the calculation correctness ratio of the core 80 during the modulation period does not reach 90%, this means that the computing performance of the core 80 is not satisfactory, so the current operating frequency of 600 MHz of the core 80 is modulated down to a lower operating frequency of 550 MHz. Those skilled in the art will appreciate that the higher operating frequency is not limited to the higher adjacent operating frequency, one or more higher adjacent operating frequencies may also be the higher operating frequency; the lower operating frequency is not limited to the lower adjacent operating frequency, one or more lower adjacent operating frequencies may also be the lower operating frequency. Those. the current 600 MHz operating frequency of the core 80 is modulated up to a higher operating frequency of 700 MHz, the current 600 MHz operating frequency of the core 80 is modulated down to a lower operating frequency of 500 MHz, and so on. In this case, the interval between the higher operating frequency and the lower operating frequency is not limited. Preferably, the difference between the current operating frequency and the higher operating frequency is 1 to 10%, and the difference between the current operating frequency and the lower operating frequency is 1 to 10%, whereby the core 80 is modulated from the current operating frequency to the higher operating frequency. frequency or lower operating frequency, and the computational benefit of the core 80 must be greater than the loss.

In another example, the performance indicator is the ratio of the calculation correctness of the core 80 during the modulation period, the first threshold of the indicator is 90%, and the second threshold of the indicator is 80%. If the calculation accuracy ratio of the core 80 during the modulation period reaches 90%, it means that the computing performance of the core 80 is satisfactory, so the current operating frequency of 600 MHz of the core 80 is modulated up to a higher operating frequency of 650 MHz. If the calculation correctness ratio of the core 80 during the modulation period does not reach 80%, this means that the computing performance of the core 80 is not satisfactory, so the current operating frequency of 600 MHz of the core 80 is modulated down to a lower operating frequency of 550 MHz.

In yet another example, the performance indicator is the number of correct computations and the number of incorrect computations of the core 80 during the modulation period, where the first threshold of the indicator is 100 and the second threshold of the indicator is 10. If the number of correct computations of the core 80 during the modulation period reaches 100, this means that the computing performance of the core 80 is satisfactory, so the current operating frequency of 600 MHz of the core 80 is modulated up to a higher operating frequency of 650 MHz. If the number of incorrect calculations of the core 80 during the modulation period reaches 10, this means that the computing performance of the core 80 is not satisfactory, so the current operating frequency of 600 MHz of the core 80 is modulated down to a lower operating frequency of 550 MHz.

Preferably, the frequency modulation module 30 further comprises a frequency modulation submodule 31 and a frequency modulation stop submodule 32 .

The frequency modulation submodule modulates the current operating frequency of the core 80 up or down according to the core computing performance indicator 80. Preferably, the frequency modulation submodule 31 modulates the current operating frequency of the core 80 up or down through the phase locked loop circuits 70 according to the core computing performance indicator 80. Of course, the frequency modulation sub-module 31 may also modulate the current operating frequency of the core 80 up or down through other hardware or software.

- 14 041302

The frequency modulation stop sub-module 32, if the cores 80 operating at the predetermined at least one optimized operating frequency exceed the predetermined first ratio, stops the frequency modulation of the cores 80; or, if the number of cores 80 operating at at least one optimized operating frequency is the maximum, stop modulating the frequencies of the cores 80.

For example, one or more optimized operating frequencies can be selected and preset from a plurality of operating frequencies, and if the operating frequencies of most of the cores 80 have reached the optimized operating frequencies, this indicates that the operating frequencies of the respective cores 80 in the working chip were in an optimized state, so most fully achieving the computing characteristics of the respective cores 80 without additional frequency modulation, therefore, the modulation of the operating frequencies of the cores 80 stops. as optimized operating frequencies, and if more than 80% of the cores 80 operate at operating frequencies of 600 and 650 MHz, the frequency modulation of the cores 80 stops.

In FIG. 3 is a schematic diagram of a frequency modulation apparatus for a computing device chip according to a second embodiment of the present invention. The computing device is preferably designed to work with data arrays, for example, to mine a virtual digital currency. Preferably, the computing device comprises a control board and a hash board connected to the control board, wherein the hash board contains at least one working chip, and the working chip contains a plurality of cores 80. Of course, the computing device may also contain a heat sink, a connection board, a power module and so on. The chip frequency modulation tool 100 at least includes a frequency setting module 10 , a computing performance analysis module 20 , and a frequency modulation module 30 .

The frequency setting unit 10 sets a plurality of operating frequencies for the operating chip of the computing device, and causes the plurality of cores 80 in the operating chip to operate at respective operating frequencies, the frequencies at each operating frequency being different from each other. Those. according to the frequency modulation mechanism at the level of the working chip, several different operating frequencies are set for each working chip, and the respective cores 80 of the working chip are operated at the respective operating frequencies. For example, six operating frequencies are set: 500, 550, 600, 650, 700 and 750 MHz. The number of operating frequencies and the spacing between frequencies according to the present invention can be set according to actual requirements, and the more operating frequencies, the more likely the computing performance of the respective cores 80 will be fully achieved. When the frequency modulation switch is turned on (without frequency modulation of the cores 80) , cores 80 may be uniformly distributed, non-uniformly distributed, or randomly distributed to operate at operating frequencies depending on a predetermined rule. Preferably, the frequency setting unit 10 sets a plurality of operating frequencies for the working chip through a plurality of phase locked loop circuits 70 shown in FIG. 2 and ensures that the plurality of cores 80 in the working chip operate at their respective operating frequencies, the operating frequencies and phase locked loop circuits 70 are in one-to-one correspondence. Thus, according to the present invention, more phase-locked loops 70 can be configured to provide more operating frequencies, thereby fully achieving the computing performance of the respective cores 80. Of course, the frequency setting unit 10 can also set multiple operating frequencies for the operating chip through other hardware or software.

It should be noted that the difference between operating frequencies according to the present invention can be controlled within an acceptable range, because when the core 80 improves by one operating frequency, the operating frequency of the core improves by one difference between frequencies, thereby improving certain computing performance due to speed increase. calculations. However, improving the operating frequency of the core may cause a loss of certain computational characteristics due to a decrease in the calculation correctness ratio. Thus, the frequency setting unit 10 must properly adjust the difference between adjacent operating frequencies so that when the core 80 is modulated up from the current operating frequency to a higher operating frequency, the computational benefit of the core 80 is greater than this loss. Preferably, the difference between adjacent operating frequencies is between 1 and 10%.

The computational performance analysis module 20 analyzes whether the calculation correctness ratio of the core 80 reaches the predetermined first and/or second correctness ratio thresholds in a predetermined modulation period, the first correctness ratio threshold is the same as or different from the second correctness ratio threshold. If the calculation correctness ratio of the core 80 reaches the predetermined first threshold value of the correctness ratio, it means that the computational performance of the core 80 can be improved. If the calculation correctness ratio of the core 80 does not reach the predetermined second threshold of the correctness ratio, this means that the computing performance of the core 80 may not be sufficient to operate at a frequency corresponding to the current operating frequency.

- 15 041302

The frequency modulation unit 30, if the calculation correctness ratio of the core 80 reaches the first correctness ratio threshold and the core 80 does not achieve the best computing performance, modulates the current operating frequency of the core 80 up to a higher operating frequency; and/or if the computational correctness ratio of core 80 does not reach the second threshold value of the ratio of correctness and computational performance of core 80 is insufficient to operate at the current operating frequency, modulates the current operating frequency of core 80 down to a lower operating frequency. The frequency modulation module 30 may modulate the frequency of the core 80 via the phase locked loop circuits 70 shown in FIG. 2, or software. Those. according to the core-level frequency modulation mechanism, the core 80 is modulated according to a suitable operating frequency according to the actual computing performance of the core 80, the frequency of the core 80 with high computing performance is modulated upwards, and the frequency of the core 80 with poor computing performance is modulated downwards , thereby fully achieving the computational performance of each core 80.

For example, the first correct ratio threshold and the second correct ratio threshold are both 90%. When the core 80 is running at 600 MHz, if the calculation correctness ratio of the core 80 during the specified modulation period exceeds 90% (this indicates that the core 80 does not achieve the best computing performance), the current 600 MHz operating frequency of the core 80 is modulated upward to higher operating frequency, i.e. operating frequency increases to 650 MHz. If the calculation accuracy ratio of core 80 is less than 90% (this indicates that the computing performance of core 80 is insufficient to operate at the current operating frequency of 600 MHz), the current operating frequency of core 80 is modulated downward to a lower operating frequency, i.e. the operating frequency is reduced to 550 MHz. Those skilled in the art will appreciate that the higher operating frequency is not limited to the higher adjacent operating frequency, one or more higher adjacent operating frequencies may also be the higher operating frequency; the lower operating frequency is not limited to the lower adjacent operating frequency, one or more lower adjacent operating frequencies may also be the lower operating frequency. Those. the current 600 MHz operating frequency of the core 80 is modulated up to a higher operating frequency of 700 MHz, the current 600 MHz operating frequency of the core 80 is modulated down to a lower operating frequency of 500 MHz, and so on. In this case, the interval between the higher operating frequency and the lower operating frequency is not limited. Preferably, the difference between the current operating frequency and the higher operating frequency is 1 to 10%, and the difference between the current operating frequency and the lower operating frequency is 1 to 10%, whereby the core 80 is modulated from the current operating frequency to the higher operating frequency. frequency or lower operating frequency, and the computational benefit of the core 80 must be greater than the loss.

In another example, the first correct ratio threshold is 90% and the second correct ratio threshold is 80%. When the core 80 is running at 600 MHz, if the calculation correctness ratio of the core 80 during the specified modulation period exceeds 90% (this indicates that the core 80 does not achieve the best computing performance), the current operating frequency of the core 80 is modulated upward to a higher operating frequency, i.e. operating frequency increases to 650 MHz. If the core 80 calculation correctness ratio is less than 90% (this indicates that the computing performance of the core 80 is not sufficient to operate at the current operating frequency of 600 MHz), the current operating frequency of the core 80 is modulated downward to a lower operating frequency, i.e. the operating frequency is reduced to 550 MHz.

Preferably, the calculation correctness ratio may be the calculation correctness ratio of the nonces (Nonce, a number that can be used once, random numbers) provided by the cores 80 during the modulation period. Those. for a given time, in all nonces provided by the cores 80, the calculation correctness ratio is the ratio occupied by the correct nonces. The block header on the blockchain contains a nonce (four bits), the nonce is a random value, and the miners actually need to guess the nonce value, so the block header hash can be less than the Target value and can be written to the blockchain. In particular, this attribute starts from 0 to 2 ³² to calculate the hash of the block header, and if the obtained hash result matches the conditions, the mining is considered successful.

Preferably, the computational performance analysis module 20 shown in FIG. 3, additionally contains:

a first analysis sub-module 21 for analyzing whether the nonces provided by the core 80 are correct within a given modulation period;

a counting sub-module 22 for counting the number of correct nonces and the number of incorrect nonces provided by the core 80 during the modulation period;

the first determination module 23 for calculating the ratio of the calculation correctness of one-time

- 16041302 numbers of the core 80 during the modulation period according to the number of correct nonces and the number of incorrect nonces, and determining whether the calculation correctness ratio of the nonces reaches the predetermined first and/or second correctness ratio thresholds.

The frequency modulation unit 30 modulates the current operating frequency of the core 80 up to a higher operating frequency if the calculation correctness ratio of the nonces of the core 80 reaches the first correctness ratio threshold; and/or modulates the current operating frequency of the core 80 down to a lower operating frequency if the calculation correctness ratio of the core 80 nonces does not reach a second correctness ratio threshold.

Most preferably, the first analysis sub-module 21 further comprises:

the first calculation unit 211 for calculating the first result based on the nonce by a predetermined algorithm each time the core 80 provides one nonce during the modulation period, the first result contains the first parameter, the first calculation unit 211 is preferably provided in the core 80. The nonce provided each core 80 contains identification information (ID) of the nonce, using which the calculation result of the calculation of each core 80 is calculated;

first checker 212 for calculating the second result based on the nonce provided by the core 80 by the same algorithm, the second result contains the second parameter, if the first parameter is the same as the second parameter, to determine that the nonce is the correct nonce number or nonce is an invalid nonce. The first checker 212 is preferably located in the working chip.

For example, after the core 80 calculates and provides one nonce, the nonce is embedded in the block header to calculate the first hash result, and the value of the first twenty bits of the first hash result is 0 (first parameter). The first validation block 212 also embeds the nonce in the block header to calculate the second hash result, and if the value of the first twenty bits of the second hash result is also 0 (second parameter), the nonce is considered to be provided correctly.

It should be noted that in order to increase the likelihood that the nonce values will satisfy the entry in the blockchain computed by one core 80, the hash can also be determined using Target_Lite in a simpler way than target value Target, and each core can provide nonces more often. The first checker 212 checks the nonces provided by core 80, and if the hash computed by the nonces provided by core 80 also passes the determination of Target_Lite, the core 80 is considered to provide the correct numbers or provide the wrong numbers. The present invention is not limited to the use of nonces that can be written to the final blockchain. The interactive nonce between the first verifier 212 and the core 80 satisfies a lower threshold, has a higher grant density, and facilitates frequency modulation.

Preferably, the computational performance analysis module 20 analyzes in real time whether the calculation correctness ratio of the kernel 80 during the modulation period reaches the first correctness ratio threshold and/or the second correctness ratio threshold, according to a preset real-time modulation instruction, wherein the first threshold the correctness ratio value is the same as or different from the second correctness ratio threshold.

If the calculation correctness ratio of the core 80 during the modulation period reaches the first correctness ratio threshold, the frequency modulation unit 30 modulates in real time the current operating frequency of the core 80 up to a higher operating frequency. If the calculation correctness ratio of the core 80 does not reach the second correctness ratio threshold during the modulation period, the frequency modulation unit 30 modulates in real time the current operating frequency of the core 80 down to a lower operating frequency, whereby the operating frequency of the core 80 is dynamically modulated. in real time.

Preferably, the computational performance analysis module 20 analyzes whether the calculation correctness ratio of the kernel 80 during the modulation period reaches the first correctness ratio threshold and/or the second correctness ratio threshold according to the pre-set advance modulation instruction during the modulation time period set by the premodulation, wherein the first correctness ratio threshold is the same as or different from the second correctness ratio threshold.

If the calculation correctness ratio of the kernel 80 during the modulation period reaches the first threshold value of the correctness ratio in the modulation time period, the modulation module 30 hour

- 17 041302 modulates the current operating frequency of core 80 upwards to a higher operating frequency. If the calculation correctness ratio of the core 80 during the modulation period does not reach the second threshold value of the correctness ratio during the modulation time period, the frequency modulation unit 30 modulates the current operating frequency of the core 80 down to a lower operating frequency, whereby the operating frequency of the core 80 is synchronized modulated. If only Saturday (24 hours) in a week is set to count the calculation correctness ratio of the core 80, the frequency modulation is carried out according to the calculation correctness ratio.

Preferably, the computational performance analysis module 20 analyzes whether the calculation correctness ratio of the core 80 during the modulation period reaches the first correctness ratio threshold and/or the second correctness ratio threshold according to the received immediate modulation instruction, the first correctness ratio threshold being the same as the second threshold value of the ratio of correctness, or different from it.

According to the immediate modulation instruction received, if the calculation correctness ratio of the core 80 during the modulation period reaches the first correctness ratio threshold, the frequency modulation unit 30 modulates the current operating frequency of the core 80 upward to a higher operating frequency, and if the calculation correctness ratio of the core 80 does not reach the second correctness ratio threshold during the modulation period, the frequency modulation unit 30 modulates the current operating frequency of the core 80 downward to a lower operating frequency. According to the received modulation stop instruction, the frequency modulation module 30 stops modulating the current operating frequency of the core 80.

For example, users can send an immediate modulation instruction to the computing device in advance according to requirements, and the computing device immediately starts to perform analysis of the calculation correctness ratio of the cores 80 according to the immediate modulation instruction. If the calculation accuracy ratio of the cores 80 exceeds the first accuracy ratio threshold (eg, more than 99%) during the modulation period (eg, 10 min), the operating frequency of the nuclei 80 is modulated upwards, and if the calculation accuracy ratio of the nuclei 80 is less than the second threshold correctness ratio (eg, below 99%) during the modulation period (eg, 10 min), the operating frequency of the cores 80 is modulated downward. In addition, users can send the modulation stop instruction to the computing device in advance as required, and upon receiving the modulation stop instruction, the computing device immediately stops the frequency modulation of the core 80.

In FIG. 4 is a schematic diagram of a frequency modulation apparatus for a computing device chip according to a third embodiment of the present invention. The computing device is preferably designed to work with data arrays, for example, to mine a virtual digital currency. Preferably, the computing device comprises a control board and a hash board connected to the control board, wherein the hash board contains at least one working chip, and the working chip contains a plurality of cores 80. Of course, the computing device may also contain a heat sink, a connection board, a power module and so on. The chip frequency modulation tool 100 includes a frequency setting module 10 , a computing performance analysis module 20 , and a frequency modulation module 30 .

The frequency setting unit 10 sets a plurality of operating frequencies for the operating chip of the computing device, and causes the plurality of cores 80 in the operating chip to operate at respective operating frequencies, the frequencies at each operating frequency being different from each other. Those. according to the frequency modulation mechanism of the work chip, a plurality of different operating frequencies are set for each work chip, and the respective cores 80 of the work chip are operated at the respective operating frequencies. For example, six operating frequencies are set: 500, 550, 600, 650, 700 and 750 MHz. The number of operating frequencies and the spacing between frequencies according to the present invention can be set according to actual requirements, and the more operating frequencies, the more likely the computing performance of the respective cores 80 will be fully achieved. When the frequency modulation switch is turned on (without frequency modulation of the cores 80) , cores 80 may be uniformly distributed, non-uniformly distributed, or randomly distributed to operate at operating frequencies depending on a predetermined rule. Preferably, the frequency setting unit 10 can set a plurality of operating frequencies for a working chip through a plurality of phase locked loop circuits 70 shown in FIG. 2. Of course, the frequency setting unit 10 can also set a plurality of operating frequencies for the operating chip through other hardware or software.

It should be noted that the difference between operating frequencies according to the present invention can be controlled within an acceptable range, because when the core 80 improves by one operating frequency, the operating frequency of the core improves by one difference between frequencies, thereby improving certain computing performance due to the increase in speed. calculations. However, improving the operating frequency of the core may cause the loss of certain computational characteristics.

- 18 041302 stick due to a decrease in the calculation correctness ratio. Thus, the frequency setting unit 10 must properly adjust the difference between adjacent operating frequencies so that when the core 80 is modulated up from the current operating frequency to a higher operating frequency, the computational benefit of the core 80 is greater than this loss. Preferably, the difference between adjacent operating frequencies is between 1 and 10%.

The computing performance analysis module 20 analyzes the performance indicator of each core 80 at its current operating frequency. Computational performance analysis module 20 further comprises:

setting sub-module 24 for presetting the node reference value, the correct calculation weight, the incorrect calculation weight, the correct calculation threshold, and the incorrect calculation threshold of the kernel 80. The correct calculation weight may be the same as the incorrect calculation weight, or different from it, and the correct calculation threshold may be the same as or different from the incorrect calculation threshold. The node reference value, the correct calculation weight, the incorrect calculation weight, the correct calculation threshold and the incorrect calculation threshold are all adjustable parameters, and can be optimized according to actual requirements such as frequency modulation rate;

a second analysis sub-module 25 for analyzing whether each calculation of the core 80 is correct. The core 80 may perform various calculations to analyze the correctness of each or more of the calculations of the core 80. Preferably, it is analyzed whether the nonces computed by the cores 80 are correct;

a counting sub-module 26 for adding one correct calculation weight value to the node reference value each time the core 80 performs at least one correct calculation, and subtracting one incorrect calculation weight value from the node reference value each time the core 80 performs at least one wrong calculation. Preferably, one correct calculation weight value is added to the node reference value each time the core 80 performs one correct calculation. Of course, one correct calculation weight value can be set to be added to the node reference value each time the core 80 performs N correct calculations (N is a natural number greater than 1). One miscalculation weight value is subtracted from the node reference value each time the core 80 performs one miscalculation. Of course, one miscalculation weight value can be set to be subtracted from the node reference value each time the core 80 performs N miscalculations (N is a natural number greater than 1);

a second determination sub-module 27 for determining whether the reference value of the core node 80 reaches a correct calculation threshold or an incorrect calculation threshold. If the node's current reference value reaches the correct computation threshold, it means that the computational performance of the core 80 is satisfactory and can be improved. If the node's current reference value reaches the miscalculation threshold, it means that the computational performance of the core 80 is poor and may not be sufficient to operate at the current operating frequency.

The frequency modulation unit 30, if the current reference value of the node of the core 80 reaches the threshold value of the correct calculation, and it is obvious that the core 80 does not achieve the best computing performance, modulates the current operating frequency of the core 80 upward to a higher operating frequency; and, if the current node reference of core 80 reaches the miscalculation threshold, and it is clear that the computing performance of core 80 is insufficient to operate at its current operating frequency, modulates the current operating frequency of core 80 down to a lower operating frequency. The frequency modulation module 30 may modulate the frequency of the core 80 via the phase locked loop circuits 70 shown in FIG. 2, or software. Those. according to the core-level frequency modulation mechanism, the core 80 is modulated according to a suitable operating frequency according to the actual computing performance of the core 80, the frequency of the core 80 with high computing performance is modulated upwards, and the frequency of the core 80 with poor computing performance is modulated downwards , thereby fully achieving the computing performance of each core 80. Those skilled in the art will appreciate that a higher operating frequency is not limited to a higher adjacent operating frequency, one or more higher adjacent operating frequencies may also represent a higher operating frequency; the lower operating frequency is not limited to the lower adjacent operating frequency, one or more lower adjacent operating frequencies may also be the lower operating frequency. Those. the current 600 MHz operating frequency of the core 80 is modulated up to a higher operating frequency of 700 MHz, the current 600 MHz operating frequency of the core 80 is modulated down to a lower operating frequency of 500 MHz, and so on. In this case, the interval between a higher working

- 19 041302 frequency and lower operating frequency is not limited. Preferably, the difference between the current operating frequency and the higher operating frequency is 1 to 10%, and the difference between the current operating frequency and the lower operating frequency is 1 to 10%, whereby the core 80 is modulated from the current operating frequency to the higher operating frequency. frequency or lower operating frequency, and the computational benefit of the core 80 must be greater than the loss.

For example, as shown in FIG. 5, the node reference value is set to 400000, the correct calculation weight is set to 180, the incorrect calculation weight is set to 9000, the correct calculation threshold and the incorrect calculation threshold are set to 100000.

180 (correct computation weight) is added to the node reference value each time the core 80 performs one correct computation, 9000 (incorrect computation weight) is subtracted from the node reference value each time the core 80 performs one incorrect computation, and considering the reference node value for the reference, a higher frequency or lower frequency is stepped up or down each time 100000 (correct calculation threshold and incorrect calculation threshold) is added or subtracted.

This mechanism is similar to the incorrect or correct tug-of-war mechanism, and the correct and incorrect mechanisms may have different weight values. The reference value of the node is set. One correct calculation weight value is added each time one correct result is received, one incorrect calculation weight value is subtracted each time one incorrect result is received, and if the reward or punishment exceeds the corresponding threshold value, up or down frequency modulation is performed. It should be understood that the system contains a token, with the node reference value being the initial value of the token: the +180 token means a correct grant, and the -9000 token means each bad grant. After the Nth (N is a natural number greater than or equal to 1) number of correct values and the Mth (M is a natural number greater than or equal to 1) incorrect values, the marker must be at position 400000+Nx180-Mx9000, and if the marker exceeds one threshold, the frequency is modulated accordingly (i.e. up or down modulation). Then, each time the frequency is modulated into a new frequency, the value returns to its initial state, i.e. the node's current reference value is reset to the node's initial reference value.

Preferably, the setup submodule 24 sets and adjusts the node reference value, the correct calculation weight, the incorrect calculation weight, the correct calculation threshold, and/or the incorrect calculation threshold of the core 80 according to actual requirements, wherein the correct calculation weight is the same as the incorrect calculation weight. calculation, or different from it, and the correct calculation threshold is the same as the incorrect calculation threshold, or different from it.

Preferably, setup submodule 24 adjusts the expected acceptable constant deviation ratio S of core 80 by adjusting the ratio of the correct calculation weight to the incorrect calculation weight. The formula for calculating the constant deviation ratio S is as follows: the constant deviation ratio S is equal to the correct calculation weight value divided by the sum of the correct calculation weight value and the incorrect calculation weight value.

Preferably, the setting submodule 24 adjusts the modulation period by adjusting the absolute value of the correct calculation weight and the incorrect calculation weight.

Preferably, the setting submodule adjusts the modulation period by adjusting the absolute value of the correct calculation threshold and the incorrect calculation threshold.

Preferably, the correct calculation may be considered when the core 80 correctly calculates the nonce.

The second analysis sub-module 25 analyzes whether the nonce provided each time by the core 80 is correct.

Counting submodule 26 adds one correct calculation weight to the node reference value each time the core 80 provides at least one correct nonces, and subtracts one incorrect calculation weight from the node reference value each time the core 80 provides at least one invalid nonce. Preferably, one correct calculation weight value is added to the node reference value each time core 80 provides one correct nonces. Of course, it is also possible to set one correct calculation weight value to be added to the node reference value each time the core 80 provides N correct nonces (N is a natural number

- 20 041302 more than 1). One miscalculation weight value is subtracted from the node reference value each time the core 80 provides one incorrect nonce. Of course, it is also possible to set one miscalculation weight value to be subtracted from the node reference value each time the core 80 provides N bad nonces (N being a natural number greater than 1).

More preferably, the second analysis sub-module 25 further comprises:

a second calculation unit 251 for calculating, by the core 80, a first result based on the nonce by a predetermined algorithm, after the core 80 provides one nonce, the first result contains the first parameter;

the second checker 252 for calculating the second result based on the nonce by the same algorithm, the second result contains the second parameter. If the first parameter is the same as the second parameter, it is determined that the nonce is a valid nonce or the nonce is an invalid nonce.

For example, after the core 80 calculates and provides one nonce, the nonce is embedded in the block header to calculate the first hash result, and the value of the first twenty bits of the first hash result is 0 (first parameter). The second validator 252 also embeds the nonce in the block header to calculate the second hash result, and if the value of the first twenty bits of the second hash result is also 0 (second parameter), the nonce is considered to be provided correctly.

It should be noted that in order to increase the likelihood that nonce values will satisfy the entry in the blockchain computed by one core 80, the hash can also be determined using Target_Lite more simply than target value Target, and each core can provide nonces more often. The first checker 212 checks the nonces provided by core 80, and if the hash computed by the nonces provided by core 80 also passes the determination of Target_Lite, the core 80 is considered to provide the correct numbers or provide the wrong numbers. The present invention is not limited to the use of nonces that can be written to the final blockchain. The interactive nonce between the first verifier 212 and the core 80 satisfies a lower threshold, has a higher grant density, and facilitates frequency modulation.

In one particular application embodiment of the present invention, six phase locked loops 70 are used and six operating frequencies are set at 500, 550, 600, 650, 700, and 750 MHz. As shown in FIG. 5, the node reference value is set to 400000, the correct calculation weight is set to 180, the incorrect calculation weight is set to 9000, the correct calculation threshold and the incorrect calculation threshold are set to 100000.

The number of cores distributed over the respective frequencies is counted by four hashplates as follows:

hash fee 0 hash fee 1 hash fee 2 hash fee 3

[294 26 96 224 1023 1665], [274 47 111 212 963 1721],

[350 25 153 369 1381 1050], [488 33 184 367 1342 950].

First of all, the mechanism is further explained with reference to the data. According to the formula in which the ratio of constant deviations S is equal to the weight value of the correct calculation divided by the sum of the weight value of the correct calculation and the weight value of the incorrect calculation, it can be assumed that the ratio of constant deviations S (which should be understood as a long-term stay at the same frequency) of the core 80 is 180/(180+9000)=1.29%, taking into account the data presented. Accordingly, the core 80 operates at the same frequency for a long time (because the desired step is 0), and the operating frequency is not modulated up or down. It can be assumed that if the calculation deviation ratio of the core 80 is greater than 1.29% (constant deviation ratio S), the operating frequency is modulated upwards, and if the calculation deviation ratio of the kernel 80 is less than 1.29% (constant deviation ratio S), the operating frequency is modulated downward.

In accordance with the complexity of the installations (complexity is related to the check reference value and affects the ratio of correctness of the calculation of the core 80, and the larger the complexity factor, the lower the correctness ratio; and vice versa, the smaller it is, the higher the correctness factor), a significant modulation period can be assumed at deviation occurs. Assuming that the deviation ratio is e, the desired step of each nonce is calculated as follows: (1-e)χ180-eχ9000=180-9180e. If e=0.5%, for example, the desired step is 134.1, if e=1%, for example, the desired step is 88.2, and if e=2%, for example, the desired step is -3.6.

The calculation is performed using 650 MHz, and the expected value of one nonce provided by the core 80 is 1.3 per second (ie, 1.3 nonces provided per second). Explanations are given using the situation in which e

- 21 041302 is 0.5%, i.e. after providing 746 nonces, the expected value may be modulated upward once. When e is 1.0%, 1134 nonces are provided, and the expected value can be modulated upward once; if the deviation ratio is 2.0%, 27778 nonces are provided, the expected number can be modulated down once, and so on.

Preferably, the computational performance analysis module 20 determines in real time whether the current reference value of the core node 80 reaches a correct calculation threshold or an incorrect calculation threshold according to a preset real-time modulation instruction, wherein the correct calculation threshold is the same as the the value of the incorrect calculation, or differs from it.

The frequency modulation unit 30, if the current reference value of the core node 80 reaches the correct calculation threshold, modulates in real time the current operating frequency of the core 80 up to a higher operating frequency; if the current reference value of the core node 80 reaches the miscalculation threshold, modulates the current operating frequency of the core 80 down to a lower operating frequency in real time, thereby dynamically modulating the operating frequency of the core 80 in real time.

Preferably, the computational performance analysis module 20 determines whether the current reference value of the core node 80 reaches the correct calculation threshold or the incorrect calculation threshold according to the preset pre-modulation instruction within the modulation time period set by the pre-modulation instruction.

The frequency modulation unit 30, if the current reference value of the core node 80 reaches the correct calculation threshold in the modulation time period, modulates the current operating frequency of the core 80 up to a higher operating frequency; if the current core node reference 80 reaches the miscalculation threshold during the modulation time period, modulates the current core 80 operating frequency down to a lower operating frequency, whereby the core 80 operating frequency is synchronized modulated. 80 is set to only Saturday (24h) in a week, the frequency modulation is carried out according to the calculation correctness ratio.

Preferably, the computational performance analysis module 20 analyzes whether the current reference value of the core node 80 reaches the correct calculation threshold or the incorrect calculation threshold according to the received immediate modulation instruction, wherein the correct calculation threshold is the same as the incorrect calculation threshold or different from him.

The frequency modulation unit 30, according to the received immediate modulation instruction, if the current reference value of the core node 80 reaches the correct calculation threshold, modulates the current operating frequency of the core 80 up to a higher operating frequency; if the current node reference value of the core 80 reaches the miscalculation threshold, modulates the current operating frequency of the core 80 down to a lower operating frequency. According to the received modulation stop instruction, the frequency modulation module 30 stops modulating the current operating frequency of the core 80.

For example, users can send an immediate modulation instruction to the computing device according to requirements in advance, and users add a weight value A to the reference node each time the core 80 correctly calculates one nonce, and subtract the weight value B from the reference node each time the core 80 80 incorrectly calculates one nonce. When the current added value reaches the threshold value of the number of correct calculations C, the core 80 raises to a higher frequency. When the current subtracted value reaches the threshold value of the number of incorrect calculations D, the core 80 performs a reduction to a lower frequency. In addition, users can send the modulation stop instruction to the computing device in advance as required, and upon receiving the modulation stop instruction, the computing device immediately stops the frequency modulation of the core 80.

In FIG. 6 is a schematic diagram of a frequency modulation apparatus for a computing device chip according to a fourth embodiment of the present invention. The computing device is preferably designed to work with data arrays, for example, to mine a virtual digital currency. Preferably, the computing device comprises a control board and a hash board connected to the control board, wherein the hash board contains at least one working chip, and the working chip contains a plurality of cores 80. Of course, the computing device may also contain a heat sink, a connection board, a power module and so on. The chip frequency modulation tool 100 includes a frequency setting module 10 , a computing performance analysis module 20 , a frequency modulation module 30 , a determination module 50

- 22 041302 frequency and frequency modulation module 60.

The frequency setting unit 10 sets a plurality of operating frequencies for the operating chip of the computing device, and causes the plurality of cores 80 in the operating chip to operate at respective operating frequencies. Those. according to the frequency modulation mechanism at the level of the working chip, a plurality of different operating frequencies are set for each working chip, and the cores 80 of the working chip are operated at the corresponding operating frequencies. For example, six operating frequencies are set: 500, 550, 600, 650, 700 and 750 MHz. The number of operating frequencies and the spacing between frequencies according to the present invention can be set according to actual requirements, and the more operating frequencies, the more likely the computing performance of the respective cores 80 will be fully achieved. When the frequency modulation switch is turned on (without frequency modulation of the cores 80) , cores 80 may be uniformly distributed, non-uniformly distributed, or randomly distributed to operate at operating frequencies, depending on a predetermined rule. Preferably, the frequency setting module 10 can set a plurality of operating frequencies for the working chip through a plurality of phase locked loop (PPL) circuits 70 shown in FIG. 2. Of course, the frequency setting unit 10 can also set a plurality of operating frequencies for the operating chip through other hardware or software.

It should be noted that the difference between operating frequencies according to the present invention can be controlled within an acceptable range, because when the core 80 improves by one operating frequency, the operating frequency of the core improves by one difference between frequencies, thereby improving certain computing performance due to the increase in speed. calculations. However, improving the operating frequency of the core may cause a loss of certain computational characteristics due to a decrease in the calculation correctness ratio. Thus, the frequency setting unit 10 must properly adjust the difference between adjacent operating frequencies so that when the core 80 is modulated up from the current operating frequency to a higher operating frequency, the computational benefit of the core 80 is greater than this loss. Preferably, the difference between adjacent operating frequencies is between 1 and 10%.

The computing performance analysis module 20 analyzes the performance indicator of each core 80 at its current operating frequency. The computing performance indicator represents the actual computing performance of the core 80 at the current operating frequency, and includes, without limitation, calculation correctness ratio, number of correct calculations, calculation rate, and the like. If the performance indicator of core 80 is high, it means that the performance of core 80 can be improved, and if the performance indicator of core 80 is low, it means that the performance of core 80 may not be sufficient to operate at the frequency corresponding to the current operating frequency.

The frequency modulation unit 30 modulates the current operating frequency of the core 80 up or down according to the performance indicator of the core 80. That is, according to the core-level frequency modulation mechanism, the core 80 is modulated according to a suitable operating frequency according to the computing performance of the core 80, the frequency of the core 80 with high computing performance is modulated upwards, and the frequency of the core 80 with poor computing performance is modulated downwards, thereby fully achieving the computing performance of each core 80. The frequency modulation unit 30 can modulate the frequency of the core 80 through the phase locked loop circuits 70 shown in FIG. 2, or software. Preferably, if the calculation correctness ratio of the core 80 during the modulation period reaches the first correctness ratio threshold, this indicates that the core 80 is not achieving the best computing performance, thereby modulating the current operating frequency of the core 80 up to a higher operating frequency. If the calculation correctness ratio of the core 80 during the modulation period reaches the second threshold value of the correctness ratio, this indicates that the computing performance of the core 80 is not sufficient to operate at the current operating frequency, as a result of which the current operating frequency of the core 80 is modulated down to a lower operating frequency. . Those skilled in the art will appreciate that the higher operating frequency is not limited to the higher adjacent operating frequency, one or more higher adjacent operating frequencies may also be the higher operating frequency; the lower operating frequency is not limited to the lower adjacent operating frequency, one or more lower adjacent operating frequencies may also be the lower operating frequency. Those. the current 600 MHz operating frequency of core 80 is modulated up to a higher operating frequency of 700 MHz, the current 600 MHz operating frequency of core 80 is modulated down to a lower operating frequency of 500 MHz, and so on. In this case, the interval between the higher operating frequency and the lower operating frequency is not limited. Preferably, the difference between the current operating frequency and the higher operating frequency is 1 to 10%, and the difference between the current operating frequency and the lower operating frequency is 1 to 10%, whereby the core is modulated.

- 23 041302 from the current operating frequency to a higher operating frequency or a lower operating frequency, and the positive effect of the computing performance of the core 80 should be greater than the loss.

The frequency determination unit 50 determines the current allocation state of the cores 80 after frequency modulation at the respective operating frequencies. After automatically modulating the operating frequency according to the computational characteristics themselves, the cores 80 are allocated to operate at the respective operating frequencies, and the frequency determination unit 50 counts the allocated number of cores 80 after frequency modulation at the respective operating frequencies, and can obtain the current distribution status. Preferably, the operating frequency may be subdivided into at least one high operating frequency, at least one medium operating frequency, and at least one low operating frequency, with the maximum frequency at the high operating frequency being the maximum operating frequency and the minimum frequency at the low operating frequency. frequency represents the minimum operating frequency. For example, there are one thousand 80 cores in total, six working frequencies are set: 500, 550, 600, 650, 700 and 750 MHz, and the number of 80 cores sequentially distributed over six working frequencies represents 100, 200, 100, 100, 200 and 300 respectively. 500 and 550 MHz are low operating frequencies, 600 and 650 MHz are medium operating frequencies, and 700 and 750 MHz are high operating frequencies. 500 MHz is the minimum operating frequency and 750 MHz is the maximum operating frequency.

The frequency modulation module 60 modulates the frequency at the operating frequency according to the current distribution state and the predetermined frequency modulation mechanism of the cores 80. The frequency modulation mechanism is a one-to-one correspondence between the distribution state and the frequency modulation of the cores. The distribution state of the cores refers to the distribution state of the cores 80 operating at the respective operating frequencies. Frequency modulation at the operating frequency refers to direct frequency modulation at the operating frequency. Preferably, the frequency modulation module 60 modulates the frequency at the operating frequency by means of the phase locked loop circuits 70 shown in FIG. 2. It will be apparent to those skilled in the art that the method of modulating the operating frequency by the frequency determination module 50 is not limited to this. The ideal state of the present invention is to hope that more than a given ratio (eg, 50%) or the maximum number of cores 80 are at mid operating frequencies, whereby the frequencies of cores 80 can be modulated upward.

For example, if more than a given ratio (e.g. 30%) of the 80 cores are running at a high operating frequency (750 MHz), this may cause the 80 cores to not reach their maximum computing performance (which may be higher), so one operating frequency ( 600 MHz) is changed to at least one optimized high operating frequency (800 MHz), and the 80 cores initially running at the operating frequency (600 MHz) are all moved to the maximum operating frequency (750 MHz). The frequency at the optimized high operating frequency is higher than the frequency at the maximum operating frequency, thereby fully reaching the computing performance of the corresponding 80 cores.

According to one particular embodiment of the present invention, the frequency modulation module 60 further comprises a first frequency modulation submodule 61 and/or a second frequency modulation submodule 62.

If the cores 80, which exceed the predetermined second ratio, operate at least one high operating frequency, and this may cause the cores 80 to not achieve maximum computing performance (which may be higher), the first frequency modulation submodule 61 changes at least one operating frequency by at least one optimized high operating frequency, and the frequency at the optimized high operating frequency is higher than the frequency at the maximum operating frequency. The changed operating frequency may be a low operating frequency, a medium operating frequency, and/or a high operating frequency.

For example, six operating frequencies are set: 500, 550, 600, 650, 700, and 750 MHz, and if more than 30% (second ratio) of 80 cores operate at two high operating frequencies (700 and 750 MHz), two low operating frequencies (500 and 550 MHz) are changed to two optimized high operating frequencies (800 and 850 MHz), or one low operating frequency (500 MHz) and one medium operating frequency (600 MHz) are changed to two optimized high operating frequencies (800 and 850 MHz).

Preferably, if the cores 80 exceeding the second ratio operate at the maximum operating frequency, and this may result in the cores 80 not achieving maximum computing performance (which may be higher), the first frequency modulation submodule 61 changes one operating frequency to one optimized high operating frequency, and the frequency at the optimized high operating frequency is higher than the frequency at the maximum operating frequency. The changed operating frequency may be a low operating frequency, a medium operating frequency, and/or a high operating frequency.

For example, if more than 30% (second ratio) of 80 cores are running at the maximum operating frequency (750 MHz), one low operating frequency (500 MHz) is changed to an optimized high operating frequency (800 MHz), or one medium operating frequency (600 MHz) changed to optimized high operating frequency (800 MHz) or maximum operating frequency (750 MHz) changed to optimized

- 24 041302 fixed high operating frequency (800 MHz).

If the cores 80, which exceed the predetermined third ratio, operate at least one low operating frequency, which means that the computational capabilities of the cores 80 are too low and insufficient to operate at the low operating frequency, the second frequency modulation submodule 62 changes at least one operating frequency per at least one optimized low operating frequency, and the frequency at the optimized low operating frequency is lower than the frequency at the minimum operating frequency, thereby preventing the poor performance cores 80 from affecting the overall performance of the operating chip. The changed operating frequency may be a low operating frequency, a medium operating frequency, and/or a high operating frequency.

For example, six operating frequencies are set at 500, 550, 600, 650, 700, and 750 MHz, and if more than 30% (third ratio) of 80 cores operate at two low operating frequencies (500 and 550 MHz), two low operating frequencies (500 and 550 MHz) are changed to two optimized low operating frequencies (400 and 450 MHz) or one low operating frequency (500 MHz) and one medium operating frequency (600 MHz) are changed to two optimized low operating frequencies (400 and 450 MHz).

Preferably, if the cores 80 above the third ratio operate at the minimum operating frequency, which means that the computational capabilities of the cores 80 are too low and insufficient to operate at the minimum operating frequency, the second frequency modulation submodule 62 changes one operating frequency to one optimized low operating frequency, and the frequency at the optimized low operating frequency is lower than the frequency at the minimum operating frequency. The changed operating frequency may be a low operating frequency, a medium operating frequency, and/or a high operating frequency.

For example, if more than 30% (third ratio) of 80 cores are running at the minimum operating frequency (500 MHz), one low operating frequency (500 MHz) is changed to an optimized low operating frequency (450 MHz) or one medium operating frequency (600 MHz) is changed to the optimized low operating frequency (450 MHz), or the maximum operating frequency (750 MHz) is changed to the optimized low operating frequency (450 MHz).

According to one particular application embodiment of the present invention, six phase locked loops 70 are used and six operating frequencies are set at 500, 550, 600, 650, 700 M, and 750 MHz.

The number of cores distributed over the respective frequencies is counted by four hashplates as follows:

hash fee 0: [294 26 96 224 1023 1665], hash fee 1: [274 47 111 212 963 1721], hash fee 2: [350 25 153 369 1381 1050], hash fee 3: [488 33 184 367 1342 950].

If four hash boards 0-3 are present, for example as shown in FIG. 7, the data is essentially normal distribution, and the minimum operating frequency (500 MHz) is the minimum frequency at which one core 80 operates, and it cannot be modulated down (if the deviation ratio is too high, one can consider closing the minimum frequency). If more than a given ratio (for example, 50%) of the 80 cores are at the maximum operating frequency (750 MHz), this means that the maximum efficiency has not been reached (may be higher), and the entire operating chip can be improved. A relatively ideal state is that more than a given ratio (eg 50%) or the maximum number of cores 80 are in one or more middle operating frequencies, eg the third operating frequency (600 MHz). To take full advantage of the computational performance of the cores 80, one should consider the long tail of the distribution on the high performance side rather than the long tail of the distribution at the low frequency.

If 0-1 hash boards are present, for example, it can be seen that if the 600 MHz frequency is removed, and if a left shift was used in general, then one hundred 80 cores are at 550 MHz, and the current frequency is obviously in the left low frequency region, which does not contribute to the full achievement of the computational characteristics of cores 80. Thus, a shift to the right is generally more appropriate, i.e. full shift. If the frequency of 550 MHz is set shifted generally to the right, above the frequency of 800 MHz by the phase locked loop circuits 70 shown in FIG. 2, several hundred 80 cores are expected to be improved above 800MHz, which will improve overall computing performance.

According to another specific embodiment of the present invention, the frequency modulation module 60 further comprises a third frequency modulation submodule 63 and/or a fourth frequency modulation submodule 64.

If the number of cores 80 operating at at least one high operating frequency is the maximum, and this may result in the cores 80 not achieving maximum computing performance (which may be higher), the third frequency modulation submodule 63 changes at least one operating frequency by at least one optimized high operating frequency,

- 25 041302 and the frequency at the optimized high operating frequency is higher than the frequency at the maximum operating frequency. The changed operating frequency may be a low operating frequency, a medium operating frequency, and/or a high operating frequency.

For example, six operating frequencies are set: 500, 550, 600, 650, 700 and 750 MHz, and a maximum of 80 cores operate at two high operating frequencies (700 and 750 MHz), resulting in two low operating frequencies (500 and 550 MHz) are changed to two optimized high operating frequencies (800 and 850 MHz), or one low operating frequency (500 MHz) and one medium operating frequency (600 MHz) are changed to two optimized high operating frequencies (800 and 850 MHz).

Preferably, if the number of cores 80 operating at the maximum operating frequency is the maximum, and this may result in the cores 80 not achieving maximum computing performance (which may be higher), the third frequency modulation submodule 63 changes one operating frequency to one optimized high operating frequency, and the frequency at the optimized high operating frequency is higher than the frequency at the maximum operating frequency. The changed operating frequency may be a low operating frequency, a medium operating frequency, and/or a high operating frequency.

For example, when the maximum number of 80 cores is running at the maximum operating frequency (750 MHz), one low operating frequency (500 MHz) is changed to an optimized high operating frequency (800 MHz), or one medium operating frequency (600 MHz) is changed to an optimized high operating frequency. frequency (800 MHz) or maximum operating frequency (750 MHz) is changed to the optimized high operating frequency (800 MHz).

If the number of cores 80 operating at at least one low operating frequency is the maximum, which means that the computational capabilities of the cores 80 are too low and insufficient to operate at a low operating frequency, the fourth frequency modulation submodule 64 changes at least one the operating frequency by at least one optimized low operating frequency, and the frequency at the optimized low operating frequency is lower than the frequency at the minimum operating frequency, thereby preventing the poor processing cores 80 from affecting the overall processing performance of the operating chip. The changed operating frequency may be a low operating frequency, a medium operating frequency, and/or a high operating frequency.

For example, six operating frequencies are set: 500, 550, 600, 650, 700 and 750 MHz, and a maximum of 80 cores operate at two low operating frequencies (500 and 550 MHz), resulting in two low operating frequencies (500 and 550 MHz) are changed to two optimized low operating frequencies (400 and 450 MHz) or one low operating frequency (500 MHz) and one medium operating frequency (600 MHz) are changed to two optimized low operating frequencies (400 and 450 MHz).

Preferably, if the number of cores 80 operating at the minimum operating frequency is the maximum, which means that the computational capabilities of the cores 80 are too low and insufficient to operate at the minimum operating frequency, the fourth frequency modulation submodule 64 changes one operating frequency to one optimized low operating frequency, and the frequency at the optimized low operating frequency is lower than the frequency at the minimum operating frequency. The changed operating frequency may be a low operating frequency, a medium operating frequency, and/or a high operating frequency.

For example, when the maximum number of 80 cores is running at the minimum operating frequency (500 MHz), one low operating frequency (500 MHz) is changed to an optimized low operating frequency (450 MHz), or one medium operating frequency (600 MHz) is changed to an optimized low operating frequency. frequency (450 MHz) or maximum operating frequency (750 MHz) is changed to the optimized low operating frequency (450 MHz).

According to one particular application embodiment of the present invention, six phase locked loops 70 are used and six operating frequencies are set at 500, 550, 600, 650, 700, and 750 MHz.

The number of cores distributed over the respective frequencies is counted by four hashplates as follows:

hash fee 0: [294 26 96 224 1023 1665], hash fee 1: [274 47 111 212 963 1721], hash fee 2: [350 25 153 369 1381 1050], hash fee 3: [488 33 184 367 1342 950].

If four hash boards 0-3 are present, for example as shown in FIG. 7, the data is essentially normal distribution, and the minimum operating frequency (500 MHz) is the minimum frequency at which one core 80 operates, and it cannot be modulated down (if the deviation ratio is too high, one can consider closing the minimum frequency). If the number of cores of 80 being at the maximum operating frequency (750 MHz) is the maximum, it means that the maximum efficiency has not been achieved (may be higher) and the entire operating chip can be improved. A relatively ideal state is that more than a given ratio (eg 50%) or the maximum number of cores 80 are in one or more middle operating frequencies, eg the third operating frequency (600 MHz). To fully exploit the computational characteristics of 80 cores, one should

- 26 041302 consider the extended tail of the distribution on the high side, and not the extended tail of the distribution on the low frequency.

If 0-1 hash boards are present, for example, one can see that if the 600 MHz frequency is removed, then one hundred 80 cores are at 550 MHz, and the current frequency is obviously in the left low frequency region. Thus, a shift to the right in general is more appropriate, i.e. full shift. If the frequency of 550 MHz is set shifted generally to the right, above the frequency of 800 MHz by the phase locked loop circuits 70 shown in FIG. 2, several hundred 80 cores are expected to be improved above 800MHz, which will improve the overall performance.

According to another specific embodiment of the present invention, the frequency modulation module 60 further comprises a first modulation stop module 65 or a second modulation stop module 66 .

If the cores 80 exceeding the predetermined fourth ratio operate at least one average operating frequency, the first modulation stop module 65 stops modulating the frequency at the operating frequency, since the relatively ideal state is that more than the predetermined fourth ratio (e.g., 50%) the cores 80 were at one or more middle operating frequencies, such as a third operating frequency (600 MHz), which can fully provide the performance of the cores 80, so that the frequency modulation of the cores 80 is not needed.

If the number of cores 80 operating at at least one average operating frequency is the maximum, the second modulation stop module 66 stops modulating the frequency at the operating frequency, since the relatively ideal state is for the maximum number of cores 80 to be in one or more average operating frequencies. frequencies, such as a third operating frequency (600 MHz), which can fully provide the performance of the cores 80, so that the frequency modulation of the cores 80 is not needed.

The present invention further provides a hash board including a device 100 for chip frequency modulation.

The present invention further provides a computing device comprising a device 100 for modulating the frequency of the chip.

In FIG. 8 is a flow diagram of a computing device chip frequency modulation method according to the present invention, which can be implemented by the computing device chip frequency modulation tool 100. The computing device contains at least one working chip, and the working chip contains a plurality of cores. The computing device is preferably designed to work with data arrays, for example, to mine a virtual digital currency. It should be noted that the frequency modulation method of the chip according to the present invention actually refers to two levels of the frequency modulation mechanism, i.e. the frequency modulation mechanism at the level of the working microcircuit and the frequency modulation mechanism at the core level. The working chip level frequency modulation mechanism refers to setting a plurality of suitable operating frequencies for each working chip and ensuring that the respective working chip cores 80 operate at the respective operating frequencies, thereby fully achieving the performance of each core 80. The core level frequency modulation mechanism refers to modulation core 80 according to suitable operating frequencies according to the actual computing performance of the core 80, modulating the frequency of the high performance core 80 upwards and modulating the frequency of the low performance core 80 downwards, thereby achieving the computing performance of each core 80. The method comprises the following steps: step S801, setting a plurality of operating frequencies for the working chip of the computing device, and causing the plurality of cores 80 in the working chip to operate at the respective operating frequencies.

At this stage, a plurality of operating frequencies are set for each work chip, and the respective cores 80 in the work chip are operated at the respective operating frequencies according to the frequency modulation mechanism of the work chip. For example, six operating frequencies are set: 500, 550, 600, 650, 700 and 750 MHz. The number of operating frequencies and the spacing between frequencies according to the present invention can be set according to actual requirements, and the more operating frequencies, the more likely the computing performance of the respective cores 80 will be fully achieved. When the frequency modulation switch is turned on (without frequency modulation of the cores 80) , cores 80 may be uniformly distributed, non-uniformly distributed, or randomly distributed to operate at operating frequencies depending on a predetermined rule. Preferably, at this stage, a plurality of operating frequencies can be set for the working chip by means of the plurality of phase locked loop circuits 70 shown in FIG. 2. Of course, the method can also set a plurality of operating frequencies for the operating chip through other hardware or software.

Step S802, analyzing the performance indicator of each core 80 at its current operating frequency.

Computational performance indicator represents the actual computational performance

- 27 041302 sticks the core 80 at the current operating frequency, and includes, without limitation, the calculation correctness ratio, the number of correct calculations, the calculation speed, and the like. If the performance indicator of core 80 is high, it means that the performance of core 80 can be improved, and if the performance indicator of core 80 is low, it means that the performance of core 80 may not be sufficient to operate at the frequency corresponding to the current operating frequency.

Step S803, modulating the current operating frequency of the core 80 up or down according to the performance indicator of the core 80.

According to the core frequency modulation mechanism, at this stage, the core 80 is modulated according to a suitable operating frequency according to the actual computing performance of the core 80, the frequency of the high performance core 80 is modulated upward, and the frequency of the low performance core 80 is modulated downward, thereby most fully achieving the computing performance of each core 80. Preferably, if the calculation correctness ratio of the core 80 during the modulation period reaches the first correctness ratio threshold, this indicates that the core 80 does not achieve the best computing performance, thereby modulating the current operating frequency of the core 80 to direction of increase to a higher operating frequency, and if the calculation correctness ratio of the core 80 during the modulation period does not reach the second threshold value of the correctness ratio, this indicates that the computational characteristics of the core and 80 is not enough to operate at the current operating frequency, as a result of which the current operating frequency of the core 80 is modulated downward to a lower operating frequency.

According to the present invention, the operating frequency of the core 80 is estimated, the corresponding frequency of the core 80 is modulated, the computational advantages of the high performance core 80 are fully achieved, the low performance core is prevented from affecting the performance of the working chip, and the computing performance of the respective cores 80 is maximized according to the actual computing performance of the respective 80 cores in the working chip, thereby increasing the calculation speed and the ratio of correct calculation of the working chip and the computing device as a whole. Moreover, in the core 80 of the working chip according to the present invention, there is no frequency change, and the working frequency is relatively stable.

In FIG. 9 is a flowchart of the computing device chip frequency modulation method according to the first embodiment of the present invention, which can be implemented by the computing device chip frequency modulation apparatus 100 shown in FIG. 2. The computing device contains at least one working chip, and the working chip contains a plurality of cores. The computing device is preferably designed to work with data arrays, for example, to mine a virtual digital currency. The method includes the following steps: step S901, setting a plurality of operating frequencies for a working chip by a plurality of phase locked loop circuits 70, operating frequencies and phase locked loop circuits 70 are in one-to-one correspondence.

Preferably, the phase locked loop circuits 70 shown in FIG. 2 are located inside or outside the working chip. The number of operating frequencies and the spacing between frequencies according to the present invention can be set according to actual requirements, and the more operating frequencies, the more likely the computing performance of the respective cores 80 will be fully achieved. For example, six operating frequencies are set: 500, 550, 600 , 650, 700 and 750 MHz. Thus, according to the present invention, more phase-locked loops 70 can be configured to provide more operating frequencies, thereby fully achieving the computing performance of the respective cores 80.

It should be noted that the difference between operating frequencies according to the present invention can be controlled within an acceptable range, because when the core 80 improves by one operating frequency, the operating frequency of the core improves by one difference between frequencies, thereby improving certain computing performance due to speed increase. calculations. However, improving the operating frequency of the core may cause a loss of certain computational characteristics due to a decrease in the calculation correctness ratio. Thus, the frequency setting unit 10 must properly adjust the difference between adjacent operating frequencies so that when the core 80 is modulated up from the current operating frequency to a higher operating frequency, the computational benefit of the core 80 is greater than this loss. Preferably, the difference between adjacent operating frequencies is between 1 and 10%.

Step S902, analyzing the performance indicator of each core 80 at its current operating frequency.

The computing performance indicator represents the actual computing performance of the core 80 at the current operating frequency, and includes, without limitation, calculation correctness ratio, number of correct calculations, calculation rate, and the like. If the performance indicator of core 80 is high, it means that the performance of core 80 can be

- 28 041302 improved, and if the core 80 computing performance indicator is low, it means that the computing performance of the core 80 may not be sufficient to operate at a frequency corresponding to the current operating frequency.

Preferably, at this stage, it is analyzed whether the indicator of the computing performance of the core 80 reaches the predetermined first, second and/or third indicator thresholds during the predetermined modulation period, the first indicator threshold being the same as or different from the second indicator threshold.

Step S903, modulating the current operating frequency of the core 80 up or down by the phase locked loop circuits 70 shown in FIG. 2 according to the performance indicator of the core 80. Of course, it is also possible at this stage to modulate the current operating frequency of the core 80 up or down by other hardware or software.

Preferably, the step further comprises the following:

(1) if the indicator of the computing performance of the core 80 reaches the first indicator threshold, modulating the current operating frequency of the core 80 upward to a higher operating frequency;

(2) if the performance indicator of the core 80 does not reach the second indicator threshold, modulating the current operating frequency of the core 80 down to a lower operating frequency; and/or (3) if the core performance indicator 80 reaches the indicator's third threshold, modulating the current core 80 operating frequency down to a lower operating frequency.

For example, consider the expression for example, six operating frequencies are set to 500, 550, 600, 650, 700, and 750 MHz, for example, the current operating frequency of core 80 is 600 MHz, the computational performance indicator is the ratio of the calculation correctness of core 80 during the modulation period, and the first the indicator threshold and the second indicator threshold are both 90%. If the calculation accuracy ratio of the core 80 during the modulation period reaches 90%, it means that the computing performance of the core 80 is satisfactory, so the current operating frequency of 600 MHz of the core 80 is modulated up to a higher operating frequency of 650 MHz. If the calculation correctness ratio of the core 80 during the modulation period does not reach 90%, this means that the computing performance of the core 80 is not satisfactory, so the current operating frequency of 600 MHz of the core 80 is modulated down to a lower operating frequency of 550 MHz. Those skilled in the art will appreciate that the higher operating frequency is not limited to the higher adjacent operating frequency, one or more higher adjacent operating frequencies may also be the higher operating frequency; the lower operating frequency is not limited to the lower adjacent operating frequency, one or more lower adjacent operating frequencies may also be the lower operating frequency. Preferably, the difference between the current operating frequency and the higher operating frequency is 1 to 10%, and the difference between the current operating frequency and the lower operating frequency is 1 to 10%, whereby the core 80 is modulated from the current operating frequency to the higher operating frequency. frequency or lower operating frequency, and the computational benefit of the core 80 must be greater than the loss. Those. the current 600 MHz operating frequency of the core 80 is modulated up to a higher operating frequency of 700 MHz, the current 600 MHz operating frequency of the core 80 is modulated down to a lower operating frequency of 500 MHz, and so on. In this case, the interval between the higher operating frequency and the lower operating frequency is not limited.

In another example, the performance indicator is the ratio of the calculation correctness of core 80 during the modulation period, the indicator's first threshold is 90% and the indicator's second threshold is 80%. If the calculation accuracy ratio of the core 80 during the modulation period reaches 90%, it means that the computing performance of the core 80 is satisfactory, so the current operating frequency of 600 MHz of the core 80 is modulated up to a higher operating frequency of 650 MHz. If the calculation correctness ratio of the core 80 during the modulation period does not reach 80%, this means that the computing performance of the core 80 is not satisfactory, so the current operating frequency of 600 MHz of the core 80 is modulated down to a lower operating frequency of 550 MHz.

In yet another example, the performance indicator is the number of correct computations and the number of incorrect computations of the core 80 during the modulation period, where the first threshold of the indicator is 100 and the second threshold of the indicator is 10. If the number of correct computations of the core 80 during the modulation period reaches 100, this means that the computing performance of the core 80 is satisfactory, so the current operating frequency of 600 MHz of the core 80 is modulated up to a higher operating frequency of 650 MHz. If the number of kernel miscalculations is 80 during the module period

- 29 041302 If the number reaches 10, this means that the computing performance of the core 80 is not satisfactory, so the current operating frequency of 600 MHz of the core 80 is modulated down to a lower operating frequency of 550 MHz.

Step S904, stopping the frequency modulation of the cores 80 if the cores 80 operating at the predetermined at least one optimized operating frequency exceed the predetermined first ratio; or stop modulating the frequencies of the cores 80 if the number of cores 80 operating at at least one optimized operating frequency is the maximum.

For example, one or more optimized operating frequencies can be selected and preset from a plurality of operating frequencies, and if the operating frequencies of most of the cores 80 have reached the optimized operating frequencies, this indicates that the operating frequencies of the respective cores 80 in the working chip were in an optimized state, so most fully achieving the computing characteristics of the respective cores 80 without additional frequency modulation, therefore, the modulation of the operating frequencies of the cores 80 stops. as optimized operating frequencies, and if more than 50% of the cores 80 operate at operating frequencies of 600 and 650 MHz, the frequency modulation of the cores 80 stops.

In FIG. 10 is a flowchart of a computing device chip frequency modulation method according to the second embodiment of the present invention, which can be implemented by the computing device chip frequency modulation apparatus 100 shown in FIG. 3. The computing device contains at least one working chip, and the working chip contains a plurality of cores. The computing device is preferably designed to work with data arrays, for example, to mine a virtual digital currency. The method includes the following steps: step S1001, setting a plurality of operating frequencies for a working chip of the computing device, and ensuring that the plurality of cores 80 in the working chip operate at the respective operating frequencies.

At this stage, a plurality of operating frequencies are set for each work chip, and the plurality of cores 80 in the work chip are set to operate at the respective operating frequencies according to the frequency modulation mechanism at the work chip level. For example, six operating frequencies are set: 500, 550, 600, 650, 700 and 750 MHz. The number of operating frequencies and the spacing between frequencies according to the present invention can be set according to actual requirements, and the more operating frequencies, the more likely the computing performance of the respective cores 80 will be fully achieved. When the frequency modulation switch is turned on (without frequency modulation of the cores 80) , cores 80 may be uniformly distributed, non-uniformly distributed, or randomly distributed to operate at operating frequencies, depending on a predetermined rule.

Preferably, at this stage, a plurality of operating frequencies are set for the working chip by means of the plurality of phase locked loop circuits 70 shown in FIG. 2 and allow the plurality of cores 80 in the work chip to operate at their respective operating frequencies, the operating frequencies and phase locked loop circuits 70 are in a one-to-one correspondence. According to the present invention, more phase-locked loops 70 can be configured to provide more operating frequencies, whereby the computing performance of the respective cores 80 is fully achieved. Of course, the method can also set multiple operating frequencies for the operating chip through other hardware or software.

It should be noted that the difference between operating frequencies according to the present invention can be controlled within an acceptable range, because when the core 80 improves by one operating frequency, the operating frequency of the core improves by one difference between frequencies, thereby improving certain computing performance due to speed increase. calculations. However, improving the operating frequency of the core may cause a loss of certain computational characteristics due to a decrease in the calculation correctness ratio. Thus, the difference between adjacent operating frequencies can be properly adjusted so that when the core 80 is modulated upward from the current operating frequency to a higher operating frequency, the computational benefit of the core 80 is greater than this loss. Preferably, the difference between adjacent operating frequencies is between 1 and 10%.

Step S1002, examining whether the calculation correctness ratio of the core 80 reaches the predetermined first and/or second correctness ratio threshold values during the predetermined modulation period. The first correct ratio threshold is the same as or different from the second correct ratio threshold. If the calculation correctness ratio of the core 80 reaches the predetermined first threshold value of the correctness ratio, it means that the computational performance of the core 80 can be improved. If the computational correctness ratio of the core 80 does not reach the predetermined second threshold value of the correctness ratio, this means that the computational performance of the core 80 may not be sufficient to operate at a frequency corresponding to those

- 30 041302 operating frequency.

Preferably, step S1002 further provides for:

(1) analyzing in real time whether the calculation correctness ratio of the kernel 80 during the modulation period reaches the first correctness ratio threshold and/or the second correctness ratio threshold, according to a preset real-time modulation instruction;

(2) evaluating whether the calculation correctness ratio of the core 80 during the modulation period reaches the first correctness ratio threshold and/or the second correctness ratio threshold according to the pre-set pre-modulation instruction within the modulation time period set by the pre-modulation instruction ; or (3) examining whether the calculation correctness ratio of the kernel 80 during the modulation period reaches the first correctness ratio threshold and/or the second correctness ratio threshold according to the received immediate modulation instruction.

Step S1003, modulating the current operating frequency of the core 80 up to a higher operating frequency if the calculation correctness ratio of the core 80 reaches the first correctness ratio threshold and it is evident that the core 80 does not achieve the best computing performance.

Preferably, the step further comprises the following:

(1) if the calculation correctness ratio of the core 80 during the modulation period reaches the first correctness ratio threshold, real-time modulation of the current operating frequency of the core 80 upward to a higher operating frequency;

(2) if the calculation correctness ratio of the core 80 during the modulation period reaches the first threshold value of the correctness ratio during the modulation time period, modulating the current operating frequency of the core 80 upward to a higher operating frequency; or (3) according to the received immediate modulation instruction, if the calculation correctness ratio of the core 80 during the modulation period reaches the first correctness ratio threshold, modulating the current operating frequency of the core 80 up to a higher operating frequency; according to the received instruction to stop modulation, stop modulation of the current operating frequency of the core 80.

For example, users can send an immediate modulation instruction to the computing device in advance according to requirements, and the computing device immediately starts to perform analysis of the calculation correctness ratio of the kernel 80 according to the immediate modulation instruction. If the core 80 calculation accuracy ratio exceeds the first accuracy ratio threshold (eg, more than 99%) during the modulation period (eg, 10 minutes), the operating frequency of the core 80 is modulated upwards, and if the core 80 calculation accuracy ratio is less than the second threshold correctness ratio (eg, below 99%) during the modulation period (eg, 10 minutes), the operating frequency of the core 80 is modulated downward. In addition, users can send the modulation stop instruction to the computing device in advance as required, and upon receiving the modulation stop instruction, the computing device immediately stops the frequency modulation of the core 80.

Step S1004, if the calculation correctness ratio of the core 80 does not reach the second correctness ratio threshold, and it is clear that the computing performance of the core 80 is not sufficient to operate at the current operating frequency, modulating the current operating frequency of the core 80 down to a lower operating frequency.

Preferably, the step further comprises the following:

(1) if the calculation correctness ratio of the core 80 during the modulation period does not reach the second correctness ratio threshold, real-time modulation of the current operating frequency of the core 80 down to a lower operating frequency;

(2) if the calculation correctness ratio of the core 80 during the modulation period does not reach the second threshold value of the correctness ratio during the modulation time period, modulating the current operating frequency of the core 80 downward to a lower operating frequency; or (3) if the calculation correctness ratio of the core 80 during the modulation period does not reach the second correctness ratio threshold, modulating the current operating frequency of the core 80 downward to a lower operating frequency; according to the received instruction to stop modulation, stop modulation, the current operating frequency of the core is 80.

According to the present invention, it is possible to modulate the frequency of the core 80 by means of the phase locked loop circuits 70 shown in FIG. 2, or software. Those. according to the core-level frequency modulation mechanism, the core 80 is modulated according to a suitable operating frequency according to the actual computing performance of the core 80, the frequency of the high performance core 80 is modulated upward, and the frequency

- 31 041302 cores 80 with low computing performance is modulated downward, thereby fully achieving the computing performance of each core 80.

For example, the first correct ratio threshold and the second correct ratio threshold are both 90%. When the core 80 is running at 600 MHz, if the calculation correctness ratio of the core 80 during the specified modulation period exceeds 90% (this indicates that the core 80 does not achieve the best computing performance), the current 600 MHz operating frequency of the core 80 is modulated upward to higher operating frequency, i.e. operating frequency increases to 650 MHz. If the calculation accuracy ratio of core 80 is less than 90% (this indicates that the computing performance of core 80 is insufficient to operate at the current operating frequency of 600 MHz), the current operating frequency of core 80 is modulated downward to a lower operating frequency, i.e. the operating frequency is reduced to 550 MHz. Those skilled in the art will appreciate that the higher operating frequency is not limited to the higher adjacent operating frequency, one or more higher adjacent operating frequencies may also be the higher operating frequency; the lower operating frequency is not limited to the lower adjacent operating frequency, one or more lower adjacent operating frequencies may also be the lower operating frequency. Preferably, the difference between the current operating frequency and the higher operating frequency is 1 to 10%, and the difference between the current operating frequency and the lower operating frequency is 1 to 10%, whereby the core 80 is modulated from the current operating frequency to the higher operating frequency. frequency or lower operating frequency, and the computational benefit of the core 80 must be greater than the loss. Those. the current 600 MHz operating frequency of the core 80 is modulated up to a higher operating frequency of 700 MHz, the current 600 MHz operating frequency of the core 80 is modulated down to a lower operating frequency of 500 MHz, and so on. In this case, the interval between the higher operating frequency and the lower operating frequency is not limited.

In another example, the first correct ratio threshold is 90% and the second correct ratio threshold is 80%. If core 80 is running at 600 MHz, if core 80 calculation correctness ratio during a given modulation period exceeds 90% (this indicates that core 80 does not achieve the best computing performance), the current operating frequency of core 80 is modulated upward to a higher operating frequency, i.e. operating frequency increases to 650 MHz. If the calculation accuracy ratio of core 80 is less than 80% (this indicates that the computing performance of core 80 is insufficient to operate at the current operating frequency of 600 MHz), the current operating frequency of core 80 is modulated downward to a lower operating frequency, i.e. the operating frequency is reduced to 550 MHz.

In FIG. 11 is a flow diagram of a preferred computing device chip frequency modulation method according to the second embodiment of the present invention, which can be implemented by the computing device chip frequency modulation tool 100 shown in FIG. 3. The computing device contains at least one working chip, and the working chip contains a plurality of cores. The computing device is preferably designed to work with data arrays, for example, to mine a virtual digital currency. Preferably, the calculation correctness ratio may be the calculation correctness ratio of the nonces provided by the core 80 during the modulation period. Those. for a given time, in all nonces provided by the core 80, the calculation correctness ratio is the ratio occupied by the correct nonces. The block header on the blockchain contains a nonce (four bits), the nonce is a random value, and the miners actually need to guess the nonce value, so the block header hash can be less than the target value and can be written to the blockchain. In particular, this attribute starts from 0 to 2 ³² to calculate the hash of the block header, and if the obtained hash result matches the conditions, the mining is considered successful. The method includes the following steps: step S1101, setting a plurality of operating frequencies for a working chip of the computing device, and ensuring that the plurality of cores 80 in the working chip operate at the respective operating frequencies.

Step S1102, examining whether the nonces provided by the core 80 are correct during the modulation period.

Preferably, the step is as follows:

(1) calculation by the core 80 of the first result based on the nonce by the predetermined algorithm, each time the core 80 provides one nonce during the modulation period, the first result contains the first parameter. The nonce provided by each core 80 contains identification information (ID) of the nonce by which the calculation result of each core 80 is calculated.

(2) calculation by the working chip tester of the second result based on the nonce by the same algorithm, the second result contains the second parameter.

(3) if the first parameter is the same as the second parameter, determining by the checker that the nonce is a valid nonce or a nonce

- 32 041302 lo is a one-time number.

For example, after the core 80 calculates and provides one nonce, the nonce is embedded in the block header to calculate the first hash result, and the value of the first twenty bits of the first hash result is 0 (first parameter). The first validation block 212 also embeds the nonce in the block header to calculate the second hash result, and if the value of the first twenty bits of the second hash result is also 0 (second parameter), the nonce is considered to be provided correctly.

Step S1103, counting the number of correct nonces and the number of incorrect nonces provided by the core 80 during the modulation period.

Step S1104, calculating the ratio of calculation correctness of the nonces of the core 80 during the modulation period according to the number of correct nonces and the number of incorrect nonces.

Step S1105, determining whether the calculation correctness ratio of the nonces reaches the predetermined first and/or second correctness ratio thresholds, if the calculation correctness ratio of the nonces of the core 80 reaches the first correctness ratio threshold, executing step S1106, and if the calculation correctness ratio of the nonces of the core numbers 80 does not reach the second correctness ratio threshold, execution of step S1107.

Step S1106, if the calculation correctness ratio of the nonces of the core 80 reaches the first correctness ratio threshold, modulating the current operating frequency of the core 80 up to a higher operating frequency.

Step SI 107, if the core 80 nonce calculation correctness ratio does not reach the second correctness ratio threshold, modulating the current operating frequency of the core 80 downward to a lower operating frequency.

In FIG. 12 is a flowchart of the computing device chip frequency modulation method according to the third embodiment of the present invention, which can be implemented by the computing device chip frequency modulation apparatus 100 shown in FIG. 4. The computing device contains at least one working chip, and the working chip contains a plurality of cores. The computing device is preferably designed to work with data arrays, for example, to mine a virtual digital currency. The method includes the following steps: step S1201, setting a plurality of operating frequencies for a working chip of the computing device, and ensuring that the plurality of cores 80 in the working chip operate at the respective operating frequencies.

At this stage, a plurality of operating frequencies are set for each work chip, and the plurality of cores 80 in the work chip are set to operate at the respective operating frequencies according to the frequency modulation mechanism at the work chip level. For example, six operating frequencies are set: 500, 550, 600, 650, 700 and 750 MHz. The number of operating frequencies and the spacing between frequencies according to the present invention can be set according to actual requirements, and the more operating frequencies, the more likely the computing performance of the respective cores 80 will be fully achieved. When the frequency modulation switch is turned on (without frequency modulation of the cores 80) , cores 80 may be uniformly distributed, non-uniformly distributed, or randomly distributed to operate at operating frequencies, depending on a predetermined rule. Preferably, a plurality of operating frequencies can be set for a working chip by means of a plurality of phase locked loop circuits 70 shown in FIG. 2. Of course, a plurality of operating frequencies can also be set for the operating chip through other hardware or software.

It should be noted that the difference between operating frequencies according to the present invention can be controlled within an acceptable range, because when the core 80 improves by one operating frequency, the operating frequency of the core improves by one difference between frequencies, thereby improving certain computing performance due to the increase in speed. calculations. However, improving the operating frequency of the core may cause a loss of certain computational characteristics due to a decrease in the calculation correctness ratio. Thus, the frequency setting unit 10 must properly adjust the difference between adjacent operating frequencies so that when the core 80 is modulated up from the current operating frequency to a higher operating frequency, the computational benefit of the core 80 is greater than this loss. Preferably, the difference between adjacent operating frequencies is between 1 and 10%.

Step S1202, presetting a node reference value, a correct calculation weight, an incorrect calculation weight, a correct calculation threshold, and an incorrect calculation threshold of the core 80.

Preferably, the correct calculation weight may be the same as or different from the incorrect calculation weight, and the correct calculation threshold may be the same as or different from the incorrect calculation threshold.

- 33 041302

The node reference value, the correct calculation weight, the incorrect calculation weight, the correct calculation threshold, and the incorrect calculation threshold are all adjustable parameters, and can be optimized according to actual requirements such as frequency modulation rate.

Preferably, the node reference value, the correct calculation weight, the incorrect calculation weight, the correct calculation threshold, and/or the incorrect calculation threshold of the core 80 are set and adjusted according to actual requirements, the correct calculation weight is the same as the incorrect calculation weight, or different. from it, and the correct calculation threshold is the same as or different from the incorrect calculation threshold.

The expected acceptable ratio of core constant deviations 80 is adjusted by adjusting the ratio of the correct calculation weight to the incorrect calculation weight. The formula for calculating the ratio of constant deviations is as follows: the ratio of constant deviations S is equal to the correct calculation weight value divided by the sum of the correct calculation weight value and the incorrect calculation weight value.

The modulation period is adjusted by adjusting the absolute value of the correct calculation weight and the incorrect calculation weight.

The modulation period is adjusted by adjusting the absolute value of the correct calculation threshold and the incorrect calculation threshold.

Step S1203, analyzing whether each calculation of the core 80 is correct.

The core 80 may perform various calculations to analyze the correctness of one or more calculations of the core 80 each time. Preferably, it is analyzed whether the nonces calculated by the core 80 are correct.

Step S1204, adding one correct calculation weight value to the node reference value each time the core 80 performs at least one correct calculation, and subtracting one incorrect calculation weight value from the node reference value each time the core 80 performs at least one incorrect calculation. Preferably, one correct calculation weight value is added to the node reference value each time the core 80 performs one correct calculation. Of course, one correct calculation weight value can be set to be added to the node reference value each time the core 80 performs N correct calculations (N is a natural number greater than 1). One miscalculation weight value is subtracted from the node reference value each time the core 80 performs one miscalculation. Of course, one miscalculation weight value can be set to be subtracted from the node reference value each time the core 80 performs N miscalculations (N is a natural number greater than 1).

Step S1205, determining whether the current reference value of the core node 80 reaches the correct calculation threshold or the incorrect calculation threshold, if the current reference value of the core node 80 reaches the correct calculation threshold, executing step S1206, and if the current node reference value core 80 reaches the miscalculation threshold, executing step S1207.

Preferably, the step is as follows:

(1) determining in real time whether the current reference value of the core node 80 reaches a correct calculation threshold or an incorrect calculation threshold according to a preset real-time modulation instruction; or (2) determining whether the current reference value of the core node 80 reaches a correct calculation threshold or an incorrect calculation threshold according to a preset advance modulation instruction within a modulation time period set by the advance modulation instruction; or (3) examining whether the current reference value of the core node 80 reaches a correct calculation threshold or an incorrect calculation threshold according to the received immediate modulation instruction.

Step S1206, modulating the current operating frequency of the core 80 up to a higher operating frequency if the current node reference value of the core 80 reaches the correct calculation threshold and it is evident that the core 80 does not achieve the best computing performance.

Preferably, the step is as follows:

(1) if the current reference value of the node of the core 80 reaches the threshold value of the correct calculation, real-time modulation of the current operating frequency of the core 80 upward to a higher operating frequency; or (2) if the current reference value of the core node 80 reaches a correct calculation threshold in the modulation time period, modulating the current operating frequency of the core 80 up to a higher operating frequency; or (3) according to the received immediate modulation instruction, if the current reference value

- 34 041302 the node of the core 80 reaches the threshold value of the correct calculation, modulation of the current operating frequency of the core 80 upwards to a higher operating frequency; according to the received instruction to stop modulation, stop modulation of the current operating frequency of the core 80.

Step S1207, if the current node reference value of the core 80 reaches the miscalculation threshold and it is evident that the computing performance of the core 80 is insufficient to operate at the current operating frequency, modulating the current operating frequency of the core 80 down to a lower operating frequency.

Preferably, the step is as follows:

(1) if the current reference value of the core node 80 reaches the miscalculation threshold, real-time modulation of the current operating frequency of the core 80 down to a lower operating frequency; or (2) if the current reference value of the core node 80 reaches a miscalculation threshold in the modulation time period, modulating the current operating frequency of the core 80 down to a lower operating frequency; or (3) if the current reference value of the core node 80 reaches the miscalculation threshold, modulating the current operating frequency of the core 80 down to a lower operating frequency; according to the received instruction to stop modulation, stop modulation of the current operating frequency of the core 80.

For example, users can send an immediate modulation instruction to the computing device according to requirements in advance, and users add a weight value A to the reference node each time the core 80 correctly calculates one nonce, and subtract the weight value B from the reference node each time the core 80 80 incorrectly calculates one nonce. When the current added value reaches the threshold value of the number of correct calculations C, the core 80 raises to a higher frequency. When the current subtracted value reaches the threshold value of the number of incorrect calculations D, the core 80 performs a reduction to a lower frequency. In addition, users can send the modulation stop instruction to the computing device in advance as required, and upon receiving the modulation stop instruction, the computing device immediately stops the frequency modulation of the core 80.

Those skilled in the art will appreciate that the higher operating frequency is not limited to the higher adjacent operating frequency, one or more higher adjacent operating frequencies may also be the higher operating frequency; the lower operating frequency is not limited to the lower adjacent operating frequency, one or more lower adjacent operating frequencies may also be the lower operating frequency. Preferably, the difference between the current operating frequency and the higher operating frequency is 1 to 10%, and the difference between the current operating frequency and the lower operating frequency is 1 to 10%, whereby the core 80 is modulated from the current operating frequency to the higher operating frequency. frequency or lower operating frequency, and the computational benefit of the core 80 must be greater than the loss. Those. the current 600 MHz operating frequency of core 80 is modulated up to a higher operating frequency of 700 MHz, the current 600 MHz operating frequency of core 80 is modulated down to a lower operating frequency of 500 MHz, and so on. In this case, the interval between the higher operating frequency and the lower operating frequency is not limited.

Preferably, the frequency of core 80 can be modulated at this stage by the phase locked loop circuits 70 shown in FIG. 2, or software. Those. according to the core-level frequency modulation mechanism, the core 80 is modulated according to a suitable operating frequency according to the actual computing performance of the core 80, the frequency of the core 80 with high computing performance is modulated upwards, and the frequency of the core 80 with poor computing performance is modulated downwards , thereby fully achieving the computational performance of each core 80.

For example, as shown in FIG. 5, the node reference value is set to 400000, the correct calculation weight is set to 180, the incorrect calculation weight is set to 9000, the correct calculation threshold and the incorrect calculation threshold are set to 100000.

180 (correct computation weight) is added to the node reference each time core 80 performs at least one correct computation, 9000 (incorrect computation weight) is subtracted from the node reference each time core 80 performs at least one incorrect calculation, and given the node reference value for the reference, a higher frequency or lower frequency is stepped up or down each time 100000 (correct calculation threshold and incorrect calculation threshold) is added or subtracted.

This mechanism is similar to the incorrect or correct tug-of-war mechanism,

- 35 041302 and correct and incorrect mechanisms may have different weight values. The reference value of the node is set. One correct calculation weight value is added each time one correct result is received, one incorrect calculation weight value is subtracted each time one incorrect result is received, and if the reward or punishment exceeds the corresponding threshold value, up or down frequency modulation is performed. It should be understood that the system contains a token, with the node reference value being the initial value of the token: token +180 means a correct grant, and a token -9000 means each wrong grant. After the Nth (N is a natural number greater than or equal to 1) number of correct values and the Mth (M is a natural number greater than or equal to 1) incorrect values, the marker must be at position 400000+Nx180-Mx9000, and if the marker exceeds one threshold, the frequency is modulated accordingly (modulation up or down). Then, each time the frequency is modulated into a new frequency, the value returns to its initial state, i.e. the node's current reference value is reset to the node's initial reference value.

In FIG. 13 is a flow diagram of a preferred computing device chip frequency modulation method according to the third embodiment of the present invention, which can be implemented by the computing device chip frequency modulation tool 100 shown in FIG. 4. The computing device contains at least one working chip, and the working chip contains a plurality of cores. The computing device is preferably designed to work with data arrays, for example, to mine a virtual digital currency. The method includes the following steps:

step S1301, setting a plurality of operating frequencies for the working chip of the computing device, and causing the plurality of cores 80 in the working chip to operate at respective operating frequencies;

step S1302, presetting a node reference value, a correct calculation weight, an incorrect calculation weight, a correct calculation threshold, and an incorrect calculation threshold of the core 80;

step S13O3, analyzing whether the nonces provided by the core 80 are correct each time.

Preferably, the step further comprises the following:

(1) calculation by the core 80 of the first result based on the nonce by a predetermined algorithm after the core 80 provides one nonce, the first result contains the first parameter;

(2) calculation by the working chip tester of the second result based on the nonce by the same algorithm, the second result contains the second parameter.

(3) if the first parameter is the same as the second parameter, determining by a checker that the nonce is a valid nonce or the nonce is a nonce.

For example, after the core 80 calculates and provides one nonce, the nonce is embedded in the block header to calculate the first hash result, and the value of the first twenty bits of the first hash result is 0 (first parameter). The second validator 252 also embeds the nonce in the block header to calculate the second hash result, and if the value of the first twenty bits of the second hash result is also 0 (second parameter), the nonce is considered to be provided correctly.

Step S1304, adding one correct calculation weight value to the node reference value each time the core 80 provides at least one correct nonces, and subtracting one incorrect calculation weight value from the node reference value each time the core 80 provides at least one invalid nonce. Preferably, one correct calculation weight value is added to the node reference value each time the core 80 provides one correct nonce. Of course, it is also possible to set one correct calculation weight value to be added to the node reference value each time the core 80 provides N correct nonces (N being a natural number greater than 1). One miscalculation weight value is subtracted from the node reference value each time the core 80 provides one incorrect nonce. Of course, one miscalculation weight can also be set to be subtracted from the node reference value each time the core 80 provides N bad nonces (N being a natural number greater than 1).

Step S1305, determining whether the current reference value of the core node 80 reaches the correct calculation threshold or the incorrect calculation threshold, if the current reference value of the core node 80 reaches the correct calculation threshold, executing step S1306, and if the current node reference value core 80 reaches the miscalculation threshold, executing step S1307.

Step S1306, modulating the current operating frequency of the core 80 up to a higher

- 36 041302 operating frequency, if the current reference value of the core node 80 reaches the threshold value of the correct calculation.

Step S1307, modulating the current operating frequency of the core 80 down to a lower operating frequency if the current reference value of the core 80 node reaches the miscalculation threshold.

According to one particular application embodiment of the present invention, six phase locked loops 70 are used and six operating frequencies are set at 500, 550, 600, 650, 700, and 750 MHz. As shown in FIG. 5, the node reference value is set to 400000, the correct calculation weight is set to 180, the incorrect calculation weight is set to 9000, the correct calculation threshold and the incorrect calculation threshold are set to 100000.

The number of cores distributed over the respective frequencies is counted by four hashplates as follows:

hash fee 0: [294 26 96 224 1023 1665], hash fee 1: [274 47 111 212 963 1721], hash fee 2: [350 25 153 369 1381 1050], hash fee 3: [488 33 184 367 1342 950].

First of all, the mechanism is further explained with reference to the data. According to the formula in which the ratio of constant deviations S is equal to the weight value of the correct calculation divided by the sum of the weight value of the correct calculation and the weight value of the incorrect calculation, it can be assumed that the ratio of constant deviations S (which should be understood as a long-term stay at the same frequency) of the core 80 is 180/(180+9000)=1.29%, taking into account the data presented. Accordingly, the core 80 operates at the same frequency for a long time (because the desired step is 0), and the operating frequency is not modulated up or down. It can be assumed that if the calculation deviation ratio of the core 80 is greater than 1.29% (constant deviation ratio S), the operating frequency is modulated upwards, and if the calculation deviation ratio of the kernel 80 is less than 1.29% (constant deviation ratio S), the operating frequency is modulated downward.

In accordance with the complexity of the installations (complexity is related to the check reference value and affects the ratio of correctness of the calculation of the core 80, and the larger the complexity factor, the lower the correctness ratio; and vice versa, the smaller it is, the higher the correctness factor), a significant modulation period can be assumed at occurrence of a deviation. Assuming that the deviation ratio is e, the desired step of each nonce is calculated as follows: (1-e)χ180-eχ9000=180-9180e. If e=0.5%, for example, the desired step is 134.1, if e=1%, for example, the desired step is 88.2, and if e=2%, for example, the desired step is -3.6.

The calculation is performed using 650 MHz, and the expected value of one nonce provided by the core 80 is 1.3 per second (ie, 1.3 nonces provided per second). Explanations are given using the situation in which e is 0.5%, i.e. after providing 746 nonces, the expected value may be modulated upwards once. When e is 1.0%, 1134 noces are provided, and the expected value can be modulated upward once; if the deviation ratio is 2.0%, 27778 nonces are provided, the expected number can be modulated down once, and so on.

In FIG. 14 is a flowchart of the computing device chip frequency modulation method according to the fourth embodiment of the present invention, which can be implemented by the computing device chip frequency modulation apparatus 100. The computing device contains at least one working chip, and the working chip contains a plurality of cores. The computing device is preferably designed to work with data arrays, for example, to mine a virtual digital currency. The method includes the following steps: step S1401, setting a plurality of operating frequencies for a working chip of the computing device, and ensuring that the plurality of cores 80 in the working chip operate at the respective operating frequencies.

At this stage, a plurality of operating frequencies are set for each working chip, and the plurality of cores 80 in the working chip are operated at the respective operating frequencies according to the frequency modulation mechanism at the working chip level. For example, six operating frequencies are set: 500, 550, 600, 650, 700 and 750 MHz. The number of operating frequencies and the spacing between frequencies according to the present invention can be set according to actual requirements, and the more operating frequencies, the more likely the computing performance of the respective cores 80 will be fully achieved. When the frequency modulation switch is turned on (without frequency modulation of the cores 80) , cores 80 may be uniformly distributed, non-uniformly distributed, or randomly distributed to operate at operating frequencies depending on

- 37 041302 of the specified rule. At this stage, it is possible to set a plurality of operating frequencies for the working chip through the plurality of phase locked loop circuits 70 shown in FIG. 2. Of course, the method can also set a plurality of operating frequencies for the operating chip through other hardware or software.

It should be noted that the difference between operating frequencies according to the present invention can be controlled within an acceptable range, because when the core 80 improves by one operating frequency, the operating frequency of the core improves by one difference between frequencies, thereby improving certain computing performance due to the increase in speed. calculations. However, improving the operating frequency of the core may cause a loss of certain computational characteristics due to a decrease in the calculation correctness ratio. Thus, the frequency setting unit 10 must properly adjust the difference between adjacent operating frequencies so that when the core 80 is modulated up from the current operating frequency to a higher operating frequency, the computational benefit of the core 80 is greater than this loss. Preferably, the difference between adjacent operating frequencies is between 1 and 10%.

Step S1402, analyzing the performance indicator of each core 80 at its current operating frequency.

The computing performance indicator represents the actual computing performance of the core 80 at the current operating frequency, and includes, without limitation, calculation correctness ratio, number of correct calculations, calculation speed, and the like. If the performance indicator of core 80 is high, it means that the performance of core 80 can be improved, and if the performance indicator of core 80 is low, it means that the performance of core 80 may not be sufficient to operate at the frequency corresponding to the current operating frequency.

Step S1403, modulating the current operating frequency of the core 80 up or down according to the performance indicator of the core 80.

According to the core-level frequency modulation mechanism, at this stage, modulate the core 80 according to a suitable operating frequency according to the actual computing performance of the core 80, modulate the frequency of the high-performance core 80 upwards, and modulate the frequency of the low-computing core 80 downwards. , thereby fully achieving the computing performance of each core 80. At this stage, the frequency of the core 80 can be modulated by the phase locked loop circuits 70 shown in FIG. 2, or software. Preferably, if the calculation correctness ratio of the core 80 during the modulation period reaches the first correctness ratio threshold, this indicates that the core 80 is not achieving the best computing performance, thereby modulating the current operating frequency of the core 80 up to a higher operating frequency. If the calculation correctness ratio of the core 80 during the modulation period does not reach the second threshold value of the correctness ratio, this indicates that the computing performance of the core 80 is insufficient to operate at the current operating frequency, as a result of which the current operating frequency of the core 80 is modulated downward to a lower operating frequency. frequency.

Those skilled in the art will appreciate that the higher operating frequency is not limited to the higher adjacent operating frequency, one or more higher adjacent operating frequencies may also be the higher operating frequency; the lower operating frequency is not limited to the lower adjacent operating frequency, one or more lower adjacent operating frequencies may also be the lower operating frequency. Preferably, the difference between the current operating frequency and the higher operating frequency is 1 to 10%, and the difference between the current operating frequency and the lower operating frequency is 1 to 10%, whereby the core 80 is modulated from the current operating frequency to the higher operating frequency. frequency or lower operating frequency, and the computational benefit of the core 80 must be greater than the loss. Those. the current 600 MHz operating frequency of the core 80 is modulated up to a higher operating frequency of 700 MHz, the current 600 MHz operating frequency of the core 80 is modulated down to a lower operating frequency of 500 MHz, and so on. In this case, the interval between the higher operating frequency and the lower operating frequency is not limited.

Step S1404, determining the current allocation state of the cores 80 after frequency modulation at the respective operating frequencies.

After automatically modulating the operating frequency according to the computing characteristics themselves, the cores 80 are allocated to operate at the respective operating frequencies, and by counting the allocated number of cores 80 after frequency modulation at the respective operating frequencies, the current state of the distribution can be obtained. Preferably, the operating frequency may be subdivided into at least one high operating frequency, at least one medium operating frequency, and at least one low operating frequency, with the maximum frequency at the high operating frequency being the maximum operating frequency and the minimum frequency at the low operating frequency.

- 38 041302 operating frequency is the minimum operating frequency. For example, there are one thousand 80 cores in total, six working frequencies are set: 500, 550, 600, 650, 700 and 750 MHz, and the number of 80 cores sequentially distributed over six working frequencies represents 100, 200, 100, 100, 200 and 300 respectively. 500 and 550 MHz are low operating frequencies, 600 and 650 MHz are medium operating frequencies, and 700 and 750 MHz are high operating frequencies. 500MHz is the minimum operating frequency and 750MHz is the maximum operating frequency.

Step S1405, frequency modulation at the operating frequency according to the current distribution state and the predetermined frequency modulation mechanism, the frequency modulation mechanism is the correspondence between the distribution state and the frequency modulation of the cores 80.

The frequency modulation mechanism is a one-to-one correspondence between the allocation state and the frequency modulation. The state of the distribution of the cores refers to the state of the distribution of the cores 80 operating at the corresponding operating frequency. Frequency modulation at the operating frequency refers to direct frequency modulation at the operating frequency. Preferably, the frequency modulation at the operating frequency is performed by the phase locked loop circuits 70 shown in FIG. 2. The ideal state according to the present invention is to hope that more than a given ratio (eg 50%) or the maximum number of cores 80 are in the middle operating frequencies, whereby the frequencies of the cores 80 can be modulated upwards.

For example, if more than a given ratio (e.g. 30%) of the 80 cores are running at a high operating frequency (750 MHz), this may cause the 80 cores to not reach their maximum computing performance (which may be higher), so one operating frequency ( 600 MHz) is changed to at least one optimized high operating frequency (800 MHz), and the 80 cores initially running at the operating frequency (600 MHz) are all moved to the maximum operating frequency (750 MHz). The frequency at the optimized high operating frequency is higher than the frequency at the maximum operating frequency, thereby fully reaching the computing performance of the corresponding 80 cores.

Preferably, after step S1405, the method may further comprise: if the cores 80 exceeding the predetermined fourth ratio operate at least one middle operating frequency, stop frequency modulation at the operating frequency; or, if the number of cores 80 operating at at least one average operating frequency is the maximum, stopping the frequency modulation at the operating frequency. A relatively ideal state is that more than a given fourth ratio (e.g., 50%) or the maximum number of cores 80 are at one or more middle operating frequencies, such as a third operating frequency (600 MHz), so that frequency modulation of the cores 80 is not needed.

In FIG. 15 is a flow diagram of one preferred computing device chip frequency modulation method according to the fourth embodiment of the present invention, which can be implemented by the computing device chip frequency modulation tool 100. The computing device contains at least one working chip, and the working chip contains a plurality of cores. The computing device is preferably designed to work with data arrays, for example, to mine a virtual digital currency. The method includes the following steps:

step S1501, setting a plurality of operating frequencies for the working chip of the computing device, and causing the plurality of cores 80 in the working chip to operate at respective operating frequencies;

step S1502, analyzing the performance indicator of each core 80 at its current operating frequency;

step S1503, modulating the current operating frequency of the core 80 up or down according to the performance indicator of the core 80;

step S1504, determining the current allocation state of the cores 80 after frequency modulation at the respective operating frequencies. The operating frequency includes at least one high operating frequency, at least one medium operating frequency, and at least one low operating frequency, wherein the maximum frequency at the high operating frequency is the maximum operating frequency, and the minimum frequency at the low operating frequency is the minimum operating frequency.

Step S1505, if the cores 80, which exceed the predetermined second ratio, operate at least one high operating frequency, and this may cause the cores 80 to not achieve maximum computing performance (which may be higher), changing at least one operating frequency by at least one optimized high operating frequency, and the frequency at the optimized high operating frequency is higher than the frequency at the maximum operating frequency. The changed operating frequency may be a low operating frequency, a medium operating frequency, and/or a high operating frequency.

For example, six operating frequencies are set: 500, 550, 600, 650, 700, and 750 MHz, and if more than 30% (second ratio) of 80 cores operate at two high operating frequencies (700 and 750 MHz), two low

- 39 041302 operating frequencies (500 and 550 MHz) are changed to two optimized high operating frequencies (800 and 850 MHz), or one low operating frequency (500 MHz) and one medium operating frequency (600 MHz) are changed to two optimized high operating frequencies (800 and 850 MHz).

Preferably, if the cores 80 greater than the second ratio operate at the maximum operating frequency, at this stage change one operating frequency to one optimized high operating frequency, and the frequency at the optimized high operating frequency is higher than the frequency at the maximum operating frequency. The changed operating frequency may be a low operating frequency, a medium operating frequency, and/or a high operating frequency.

For example, if more than 30% (second ratio) of 80 cores are running at the maximum operating frequency (750 MHz), one low operating frequency (500 MHz) is changed to an optimized high operating frequency (800 MHz), or one medium operating frequency (600 MHz) is changed to the optimized high operating frequency (800 MHz) or the maximum operating frequency (750 MHz) is changed to the optimized high operating frequency (800 MHz).

Step S1506, if the cores 80 exceeding the predetermined third ratio operate at least one low operating frequency, which means that the computing capability of the cores 80 is too low and insufficient to operate at the low operating frequency, changing at least one operating frequency by at least one optimized low operating frequency, and the frequency at the optimized low operating frequency is lower than the frequency at the minimum operating frequency. It should be understood that this step may be omitted, ie. at least one operating frequency does not change to at least one optimized low operating frequency.

The changed operating frequency may be a low operating frequency, a medium operating frequency, and/or a high operating frequency. For example, six operating frequencies are set at 500, 550, 600, 650, 700, and 750 MHz, and if more than 30% (third ratio) of 80 cores operate at two low operating frequencies (500 and 550 MHz), two low operating frequencies (500 and 550 MHz) are changed to two optimized low operating frequencies (400 and 450 MHz) or one low operating frequency (500 MHz) and one medium operating frequency (600 MHz) are changed to two optimized low operating frequencies (400 and 450 MHz).

Preferably, if cores 80 larger than the third ratio are operating at the minimum operating frequency, one operating frequency is changed at this stage to one optimized low operating frequency. The changed operating frequency may be a low operating frequency, a medium operating frequency, and/or a high operating frequency. For example, if more than 30% (third ratio) of 80 cores are running at the minimum operating frequency (500 MHz), one low operating frequency (500 MHz) is changed to an optimized low operating frequency (450 MHz) or one medium operating frequency (600 MHz) is changed to an optimized low operating frequency (450 MHz), or the maximum operating frequency (750 MHz) is changed to an optimized low operating frequency (450 MHz)

Preferably, after step S1506, the method further comprises: if the cores 80 exceeding the predetermined fourth ratio operate at least one middle operating frequency, stop frequency modulation at the operating frequency, since the relatively ideal state is to be greater than the predetermined fourth ratio (e.g. , 50%) of the cores 80 were at one or more middle operating frequencies, such as a third operating frequency (600 MHz), which can fully provide the performance of the cores 80, so that the frequency modulation of the cores 80 is not needed.

If the number of cores 80 operating at least one average operating frequency is the maximum, stop modulating the frequency at the operating frequency, since the relatively ideal state is for the maximum number of cores 80 to be at one or more average operating frequencies, for example, the third operating frequency (600 MHz), which can fully provide the performance of the cores 80, so that the frequency modulation of the cores 80 is not needed.

According to one particular application embodiment of the present invention, six phase locked loops 70 are used and six operating frequencies are set at 500, 550, 600, 650, 700, and 750 MHz.

The number of cores distributed over the respective frequencies is counted by four hashplates as follows:

hash fee 0 hash fee 1 hash fee 2 hash fee 3

[294 26 96 224 1023 1665], [274 47 111 212 963 1721],

[350 25 153 369 1381 1050], [488 33 184 367 1342 950].

If four hash boards 0-3 are present, for example as shown in FIG. 7, the data is essentially normal distribution, and the minimum operating frequency (500 MHz) is the minimum frequency at which one core 80 operates, and it cannot be modulated down (if the deviation ratio is too high, one can consider closing the minimum frequency). If more than a given ratio (for example, 50%) of the 80 cores are at the maximum operating frequency (750 MHz), this means that the maximum efficiency has not been achieved (may be higher), and the entire operating chip can be improved. Relatively ideal

- 40 041302 standing is that more than a given ratio (eg 50%) or the maximum number of cores 80 were in one or more middle operating frequencies, for example the third operating frequency (600 MHz). In order to fully exploit the computational performance of the cores 80, one should consider the extended tail of the distribution on the high performance side rather than the extended tail of the distribution at the low frequency.

If 0-1 hash boards are present, for example, it can be seen that if the 600 MHz frequency is removed, and if a left shift was used in general, then one hundred 80 cores are at 550 MHz, and the current frequency is obviously in the left low frequency region, which does not contribute to the full achievement of the computational characteristics of cores 80. Thus, a shift to the right is generally more appropriate, i.e. full shift. If 550 MHz is set broadly to the right above 800 MHz by the phase locked loop circuits 70, several hundred cores 80 are expected to be improved above 800 MHz to improve overall computing performance.

In FIG. 16 is a flow diagram of a second preferred computing device chip frequency modulation method according to the fourth embodiment of the present invention, which can be implemented by the computing device chip frequency modulation tool 100. The computing device contains at least one working chip, and the working chip contains a plurality of cores. The computing device is preferably designed to work with data arrays, for example, to mine a virtual digital currency. The method includes the following steps:

step S1601, setting a plurality of operating frequencies for the working chip of the computing device, and causing the plurality of cores 80 in the working chip to operate at respective operating frequencies;

step S1602, analyzing the performance indicator of each core 80 at its current operating frequency;

step S1603, modulating the current operating frequency of the core 80 up or down according to the performance indicator of the core 80;

step S1604, determining the current allocation state of the cores 80 after frequency modulation at the respective operating frequencies. The operating frequency includes at least one high operating frequency, at least one medium operating frequency, and at least one low operating frequency, wherein the maximum frequency at the high operating frequency is the maximum operating frequency, and the minimum frequency at the low operating frequency is the minimum operating frequency.

Step S1605, if the number of cores 80 running at least one high operating frequency is the maximum, and this may cause the cores 80 to not achieve maximum computing performance (which may be higher), changing at least one operating frequency by at least one optimized high operating frequency, and the frequency at the optimized high operating frequency is higher than the frequency at the maximum operating frequency. The changed operating frequency may be a low operating frequency, a medium operating frequency, and/or a high operating frequency.

For example, six operating frequencies are set: 500, 550, 600, 650, 700 and 750 MHz, and a maximum of 80 cores operate at two high operating frequencies (700 and 750 MHz), resulting in two low operating frequencies (500 and 550 MHz) are changed to two optimized high operating frequencies (800 and 850 MHz), or one low operating frequency (500 MHz) and one medium operating frequency (600 MHz) are changed to two optimized high operating frequencies (800 and 850 MHz).

Preferably, if the number of cores 80 operating at the maximum operating frequency is the maximum, one operating frequency is changed at this stage to one optimized high operating frequency. The changed operating frequency may be a low operating frequency, a medium operating frequency, and/or a high operating frequency.

For example, when the maximum number of 80 cores is running at the maximum operating frequency (750 MHz), one low operating frequency (500 MHz) is changed to an optimized high operating frequency (800 MHz), or one medium operating frequency (600 MHz) is changed to an optimized high operating frequency. frequency (800 MHz) or maximum operating frequency (750 MHz) is changed to the optimized high operating frequency (800 MHz).

Step S1606, if the number of cores 80 running at least one low operating frequency is the maximum, which means that the computing capability of the cores 80 is too low and insufficient to operate at the low operating frequency, changing at least one operating frequency at least one optimized low operating frequency, and the frequency at the optimized low operating frequency is lower than the frequency at the minimum operating frequency, thereby preventing the poor processing cores 80 from affecting the overall processing performance of the operating chip. This step can be excluded, i.e. at least one operating frequency does not change to at least one optimized low operating frequency.

- 41 041302

The changed operating frequency may be a low operating frequency, a medium operating frequency, and/or a high operating frequency.

For example, six operating frequencies are set: 500, 550, 600, 650, 700 and 750 MHz, and a maximum of 80 cores operate at two low operating frequencies (500 and 550 MHz), resulting in two low operating frequencies (500 and 550 MHz) are changed to two optimized low operating frequencies (400 and 450 MHz) or one low operating frequency (500 MHz) and one medium operating frequency (600 MHz) are changed to two optimized low operating frequencies (400 and 450 MHz).

Preferably, if the number of cores 80 operating at the maximum operating frequency is minimal, at this stage one operating frequency is changed to one optimized low operating frequency. The changed operating frequency may be a low operating frequency, a medium operating frequency, and/or a high operating frequency. For example, when the maximum number of 80 cores is running at the minimum operating frequency (500 MHz), one low operating frequency (500 MHz) is changed to an optimized low operating frequency (450 MHz), or one medium operating frequency (600 MHz) is changed to an optimized low operating frequency. frequency (450 MHz) or maximum operating frequency (750 MHz) is changed to the optimized low operating frequency (450 MHz).

Preferably, after step S1606, the method further comprises the following:

if the cores 80 exceeding the predetermined fourth ratio operate at least one middle operating frequency, stopping the frequency modulation at the operating frequency; or if the number of cores 80 operating at at least one average operating frequency is the maximum, stop frequency modulation at the operating frequency.

According to one particular application embodiment of the present invention, six phase locked loops 70 are used and six operating frequencies are set at 500, 550, 600, 650, 700, and 750 MHz.

The number of cores distributed over the respective frequencies is counted by four hashplates as follows:

hash fee 0: [294 26 96 224 1023 1665], hash fee 1: [274 47 111 212 963 1721], hash fee 2: [350 25 153 369 1381 1050], hash fee 3: [488 33 184 367 1342 950].

If four hash boards 0-3 are present, for example as shown in FIG. 7, the data is essentially normal distribution, and the minimum operating frequency (500 MHz) is the minimum frequency at which one core 80 operates, and it cannot be modulated down (if the deviation ratio is too high, one can consider closing the minimum frequency). If the number of cores of 80 being at the maximum operating frequency (750 MHz) is the maximum, it means that the maximum efficiency has not been achieved (may be higher) and the entire operating chip can be improved. A relatively ideal state is that more than a given ratio (eg 50%) or the maximum number of cores 80 are in one or more middle operating frequencies, eg the third operating frequency (600 MHz). To take full advantage of the computational performance of the cores 80, one should consider the long tail of the distribution on the high performance side rather than the long tail of the distribution at the low frequency.

If 0-1 hash boards are present, for example, one can see that if the 600 MHz frequency is removed, then one hundred 80 cores are at 550 MHz, and the current frequency is obviously in the left low frequency region. Thus, a shift to the right in general is more appropriate, i.e. full shift. If 550 MHz is set broadly to the right above 800 MHz by the phase locked loop circuits 70, several hundred cores 80 are expected to be improved above 800 MHz to improve overall computing performance.

The present invention further provides a storage medium for storing a computer program executing the frequency modulation method of a computing device chip according to any of FIGS. 8-16. For example, when computer program instructions are executed by computers, the method and/or solution of the present invention may be invoked or provided through the operation of the computers. Moreover, program instructions for invoking the method of the present invention may be stored in a non-removable or removable storage medium, and/or transmitted and/or stored in a storage device of a computing device triggered by program instructions via a broadcast or data stream in other signal media. In this case, according to this, in one embodiment of the present invention, the computing device shown in FIG. 17, the computing device preferably includes a control board and at least one hash board connected to the control board. The control board contains a processor, the hash board contains a plurality of work chips to operate, and the work chips contain a plurality of cores. The device includes a storage medium for storing instructions of a computer program and a processor for executing the instructions of the program. When the instructions of a computer program are executed by the processor, the calculation starts.

Claims (18)

a casting device for executing the method and/or technical solution according to the aforementioned several embodiments. It should be noted that the present invention may be implemented in software and/or a combination of software and hardware. For example, the present invention may be implemented in application specific integrated circuits (ASICs), general purpose computers, or any other similar hardware. According to one embodiment, a software program according to the present invention may be executed by a processor to implement the following steps or functions. Likewise, a software program (including an associated data structure) according to the present invention may be stored in a computer-readable storage medium such as RAM, a magnetic or optical storage device, a floppy disk, or the like. In addition, certain steps or functions of the present invention may be implemented in hardware, such as circuitry, operating in conjunction with a processor to execute the corresponding steps or functions. The method of the present invention may be implemented as a computer-implemented method on computers, dedicated hardware, or a combination thereof. The executable code, or portions thereof, in the method of the present invention may be stored on computer program products. Examples of computer program products include storage devices, optical storage devices, integrated circuits, servers, online software, and the like. Preferably, the computer program products include persistent program code elements stored on a computer-readable medium for executing the method of the present invention when the software products are executed on computers. According to one preferred embodiment, the computer program comprises computer program code elements for executing all steps in the method of the present invention when the computer program is running on computers. Preferably, the computer program is implemented on a computer-readable medium. Summarizing, according to the present invention, the frequencies of the cores of the working chip of the computing device are automatically modulated, first setting a plurality of suitable operating frequencies and ensuring that the plurality of cores in the working chip operate at the corresponding operating frequencies, and then modulating the current operating frequency of the core in the direction of increasing or decreasing according to the indicator computing characteristics of each core at the current operating frequency, i.e. upward modulation of the high performance core and downward modulation of the low performance core. Thus, according to the present invention, the frequency corresponding to each core is automatically modulated according to the actual computing performance of each core in the working chip of the computing device, thereby maximizing the computing performance of the cores and improving the performance of the working chip and the working device as a whole. Of course, the present invention may also be characterized by various other embodiments, and those skilled in the art may make various appropriate modifications and variations in accordance with the present invention without departing from the spirit and scope of the present invention, but such appropriate modifications and variations shall be within the scope of the legal protection of the appended claims. Industrial Applicability The use of the frequency modulation method and apparatus of the computing device chip, the hash board, the computing device, and the storage medium of the present invention have the following advantageous effects: automatically modulating the frequency corresponding to each core according to the actual computing performance of each core in the working computing device chip, thereby maximizing the computing performance of the cores and improving the performance of the working chip and the working device as a whole. CLAIM 1. A method for frequency modulation of a microcircuit of a computing device, the computing device contains at least one working microcircuit, and the working microcircuit contains a plurality of cores, comprising the following steps: setting a plurality of operating frequencies for a working chip of the computing device and ensuring that the plurality of cores in the working chip operate at respective operating frequencies; analysis of the indicator of computing characteristics of each core at its current operating frequency; and modulating the current operating frequency of the core up or down according to the core computing performance indicator, wherein the step of setting a plurality of operating frequencies for the operating chip of the computing device and ensuring that the plurality of cores in the operating chip operate at respective operating frequencies further comprises: - 43 041302 setting a plurality of operating frequencies for a working chip by means of a plurality of phase-locked loops, operating frequencies and phase-locked loops are in one-to-one correspondence; wherein the step of modulating the current core operating frequency up or down according to the core performance indicator further comprises: modulating the current operating frequency of the core up or down by the phase-locked loops according to the core computing performance indicator. 2. The chip frequency modulation method according to claim 1, wherein the phase locked loop circuits are located inside or outside the working chip. 3. The chip frequency modulation method according to claim 1, wherein the step of analyzing the performance indicator of each core at its current operating frequency further comprises: analyzing whether an indicator of core computing performance reaches predetermined first, second, and/or third indicator thresholds during a predetermined modulation period, wherein the first indicator threshold is the same as or different from the second indicator threshold; wherein the step of modulating the current core operating frequency up or down according to the core performance indicator further comprises: if the core computing performance indicator reaches the first threshold of the indicator, modulating the current core operating frequency upward to a higher operating frequency; if the core performance indicator does not reach the second indicator threshold, modulating the current core operating frequency downward to a lower operating frequency; and/or if the core performance indicator reaches the indicator's third threshold, modulating the current core operating frequency down to a lower operating frequency. 4. The chip frequency modulation method according to claim 1, further comprising the following: if the cores operating at the predetermined at least one optimized operating frequency exceed the predetermined first ratio, stopping the core frequency modulation; or if the number of cores operating at at least one optimized operating frequency is the maximum, stop modulating the core frequencies. 5. The chip frequency modulation method of claim 1, wherein the step of analyzing the performance indicator of each core at its current operating frequency further comprises: analyzing whether the kernel calculation correctness ratio reaches the predetermined first and/or second correctness ratio thresholds during the predetermined modulation period, the first correctness ratio threshold is the same as or different from the second correctness ratio threshold; wherein the step of modulating the current core operating frequency up or down according to the core performance indicator further comprises: if the core calculation correctness ratio reaches the first correctness ratio threshold, modulating the current core operating frequency upward to a higher operating frequency; and/or if the core calculation correctness ratio does not reach the second correctness ratio threshold, modulating the current core operating frequency down to a lower operating frequency. 6. The chip frequency modulation method according to claim 5, wherein the step of analyzing whether the calculation correctness ratio of the kernel reaches predetermined first and/or second correctness ratio threshold values during a predetermined modulation period further comprises: analyzing whether the random numbers provided by the core are correct during the modulation period; counting the number of correct random numbers and the number of incorrect core random numbers during the modulation period; calculating a kernel random number calculation correctness ratio during the modulation period according to the number of correct random numbers and the number of incorrect random numbers, and determining whether the random number calculation correctness ratio reaches predetermined first and/or second correctness ratio thresholds; wherein the step of modulating the current core operating frequency up or down according to the core performance indicator further comprises: if the core random number calculation accuracy ratio reaches the first accuracy ratio threshold value, the modulation of the current core operating frequency upwards to - 44 041302 higher operating frequency; if the core random number calculation correctness ratio does not reach the second correctness ratio threshold, modulating the current core operating frequency down to a lower operating frequency. 7. The chip frequency modulation method according to claim 6, wherein the step of analyzing whether the random numbers provided by the core are correct during the modulation period further comprises: calculating, by the core, a first result based on the random numbers by a predetermined algorithm, each time the core provides one random number during the modulation period, the first result contains the first parameter; calculating, using the working chip tester, a second result based on random numbers using the same algorithm, the second result contains a second parameter; if the first parameter is the same as the second parameter, determining, by means of a tester, that the random numbers are correct random numbers or the random numbers are incorrect random numbers. 8. The chip frequency modulation method according to claim 5, wherein the step of analyzing whether the calculation correctness ratio of the kernel reaches predetermined threshold values of the correctness ratio during the predetermined modulation period further comprises: analyzing in real time whether the kernel calculation correctness ratio during the modulation period reaches the first correctness ratio threshold and the second correctness ratio threshold according to a preset real-time modulation instruction; evaluating whether the kernel calculation correctness ratio during the modulation period reaches the first correctness ratio threshold and the second correctness ratio threshold according to the pre-set advance modulation instruction within the modulation time period set by the advance modulation instruction; or analyzing whether the kernel calculation correctness ratio reaches, during the modulation period, the first correctness ratio threshold and the second correctness ratio threshold according to the received immediate modulation instruction; wherein the step of modulating the current core operating frequency up or down according to the core performance indicator further comprises: if the core calculation correctness ratio during the modulation period reaches the first correctness ratio threshold value, real-time modulation of the current core operating frequency upward to a higher operating frequency; if the core calculation correctness ratio during the modulation period does not reach the second correctness ratio threshold, real-time modulation of the current core operating frequency down to a lower operating frequency; if the core calculation correctness ratio during the modulation period reaches the first correctness ratio threshold during the modulation time period, modulating the current core operating frequency upward to a higher operating frequency; if the core calculation correctness ratio during the modulation period does not reach the second correctness ratio threshold during the modulation time period, modulating the current core operating frequency down to a lower operating frequency; or according to the received immediate modulation instruction, if the core calculation correctness ratio during the modulation period reaches the first correctness ratio threshold, modulating the current core operating frequency upward to a higher operating frequency; if the core calculation correctness ratio during the modulation period does not reach the second correctness ratio threshold, modulating the current core operating frequency down to a lower operating frequency; according to the received instruction to stop modulation, stop modulation of the current operating frequency of the core. 9. The chip frequency modulation method according to claim 1, wherein the step of analyzing the performance indicator of each core at its current operating frequency further comprises: presetting a node reference value, a correct calculation weight, an incorrect calculation weight, a correct calculation threshold, and a core calculation incorrect threshold; analysis of whether each kernel calculation is correct; adding one correct calculation weight value to the node reference value each time the core performs at least one correct calculation, and subtracting one incorrect calculation weight value from the node reference value each time the core performs at least one incorrect calculation; - 45 041302 determining whether the reference value of the core node reaches a correct calculation threshold or an incorrect calculation threshold; wherein the step of modulating the current core operating frequency up or down according to the core performance indicator further comprises: if the current core node reference value reaches a correct calculation threshold, modulating the current core operating frequency upward to a higher operating frequency; if the current core node reference value reaches the miscalculation threshold, modulating the current core operating frequency down to a lower operating frequency. 10. A device for frequency modulation of a microcircuit of a computing device, the computing device contains at least one working microcircuit, and the working microcircuit contains a plurality of cores, containing: a frequency setting module for setting a plurality of operating frequencies for a working chip of the computing device and allowing the plurality of cores in the working chip to operate at respective operating frequencies; a computing performance analysis module for analyzing a performance indicator of each core at its current operating frequency; and a frequency modulation unit for modulating the current operating frequency of the core up or down according to the core computing performance indicator, the frequency setting unit being configured to set a plurality of operating frequencies for the operating chip by a plurality of phase locked loops, and operating frequencies and phase locked loops are in one-to-one correspondence; and the frequency modulation module is configured to modulate the current operating frequency of the core up or down by the phase-locked loops according to the core computing performance indicator. 11. The device for frequency modulation of the microcircuit according to claim 10, in which the phase-locked loop circuits are located inside or outside the working microcircuit. 12. The chip frequency modulation apparatus of claim 10, wherein the computing performance analysis module analyzes whether the core computing performance indicator reaches predetermined first, second, and/or third indicator thresholds during a predetermined modulation period, wherein the first indicator threshold is the same , as the second threshold value of the indicator, or different from it; if the core computing performance indicator reaches the first indicator threshold, the frequency modulation module modulates the current core operating frequency up to a higher operating frequency; if the core performance indicator does not reach the second indicator threshold, the frequency modulation module modulates the current core operating frequency down to a lower operating frequency; and/or if the core performance indicator reaches the indicator's third threshold, the frequency modulation module modulates the current core operating frequency down to a lower operating frequency. 13. The device for frequency modulation of the microcircuit according to claim 10, in which the frequency modulation module further comprises: a frequency modulation submodule for modulating a current core operating frequency up or down according to a core performance indicator; a frequency modulation stop submodule for stopping the frequency modulation of the cores if the cores running at the predetermined at least one optimized operating frequency exceed the predetermined first ratio; or to stop modulating the frequencies of the cores if the number of cores running at least one optimized operating frequency is the maximum. 14. The chip frequency modulation apparatus according to claim 10, wherein the computational performance analysis module analyzes whether the kernel calculation correctness ratio reaches predetermined first and/or second correctness ratio threshold values during a predetermined modulation period, wherein the first correctness ratio threshold is the same , as the second threshold value of the correctness ratio, or different from it; the frequency modulation module modulates the current operating frequency of the core upward to a higher operating frequency if the core calculation correctness ratio reaches the first correctness ratio threshold; and/or modulates the current core operating frequency down to a lower operating frequency if the core calculation correctness ratio does not reach the second correctness ratio threshold. 15. The chip frequency modulation tool of claim 14, wherein the computational performance analysis module further comprises: a first analysis sub-module for analyzing whether the random numbers provided by the core are correct during the modulation period; - 46 041302 counting submodule for counting the number of correct random numbers and the number of incorrect core random numbers during the modulation period; and a first determination module for calculating a core random number calculation correctness ratio during the modulation period according to the number of correct random numbers and the number of incorrect random numbers, and determining whether the random number calculation correctness ratio reaches predetermined first and/or second correctness ratio threshold values; wherein the frequency modulation module is configured to modulate the current core operating frequency upward to a higher operating frequency if the core random number calculation correctness ratio reaches a first correctness ratio threshold; and/or modulating the current core operating frequency down to a lower operating frequency if the kernel random number calculation correctness ratio does not reach a second correctness ratio threshold. 16. The device for modulating the frequency of the microcircuit according to claim 15, in which the first analysis submodule further comprises: a first calculation unit for calculating a first result based on the random numbers by a predetermined algorithm, each time the core provides one random number during the modulation period, the first result contains the first parameter, the first calculation unit is provided in the core; and a first checker for calculating a second result based on the random numbers by the same algorithm, the second result contains the second parameter, and if the first parameter is the same as the second parameter, for determining that the random number is a valid random number or random number is a wrong random number, the first check block is provided in the working chip. 17. The chip frequency modulation apparatus according to claim 14, wherein the computational performance analysis module analyzes in real time whether the core calculation correctness ratio during the modulation period reaches the first correctness ratio threshold and the second correctness ratio threshold, according to a preset instruction. modulation in real time; the computational performance analysis unit analyzes whether the core calculation correctness ratio during the modulation period reaches the first correctness ratio threshold and the second correctness ratio threshold according to the pre-set advance modulation instruction within the modulation time period set by the advance modulation instruction; or the computational performance analysis module analyzes whether the core calculation correctness ratio during the modulation period reaches the first correctness ratio threshold and the second correctness ratio threshold according to the received immediate modulation instruction; the frequency modulation module modulates in real time the current operation frequency of the core upward to a higher operation frequency if the core calculation correctness ratio during the modulation period reaches the first correctness ratio threshold; and modulating in real time the current operating frequency of the core down to a lower operating frequency if the core calculation correctness ratio during the modulation period does not reach the second correctness ratio threshold; the frequency modulation module modulates the current operating frequency of the core up to a higher operating frequency if the core calculation correctness ratio during the modulation period reaches the first threshold value of the correctness ratio during the modulation time period; and modulates the current operating frequency of the core down to a lower operating frequency if the core calculation correctness ratio during the modulation period does not reach the second threshold value of the correctness ratio during the modulation time period; or the frequency modulation module, according to the received immediate modulation instruction, modulates the current operating frequency of the core up to a higher operating frequency if the core calculation correctness ratio during the modulation period reaches the first correctness ratio threshold; modulates the current operating frequency of the core down to a lower operating frequency if the ratio of correctness of the calculation of the core during the modulation period does not reach the second threshold value of the ratio of correctness; and stops modulating the current core operating frequency according to the received modulation stop instruction. 18. The device for modulating the frequency of the microcircuit according to claim 10, in which the computing performance analysis module further comprises: a setting sub-module for presetting a node reference value, a correct calculation weight, an incorrect calculation weight, a correct calculation threshold, and a core calculation incorrect threshold; -