DK161291B - DIGITAL TRANSMISSION SYSTEM FOR VIDEO-SHOWED PHONE PHONE SIGNALS - Google Patents

Abstract

1. System for the digital transmission of video and/or videotelephone signals at the bit rate of a PCM quaternary system of 139.264 Mbit/s pursuant to CCITT G 703.9, with the analog video or vidotelephone signal being digitally coded to a bit rate of 135 Mbit/s and a multiplexer (sync-mux) is provided at the transmitting end which bundles, in synchronism, the coded video or videotelephone signal whose bit rate has been brought, by means of the plugging technique, to a whole number multiple of 64 kbit/s, together with synchronizing signals (syn), signalling signals (sign) and additonal narrowband signals and possibly also with justification signals for said additional narrowband signals, each at the bit rate of 64 kbit/s or a whole number multiple thereof, into a multiplex signal at the bit rate of 139.264 Mbit/s and a demultiplexing device (sync-demux) is provided at the receiving end which breaks up the multiplex signal into the individual signals in a correspondingly reversed manner, characterized in that the multiplex signal formed by the multiplexer (sync-mux) and received by the demultiplexer (sync-demux) has a frame having 2176 time slots, with each time slot comprising 10 bits.

Description

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DK 161291 B

The invention relates to a system for digitally transmitting video and picture telephone signals as defined in the preamble of claim 1.

The invention according to German Patent Application No. P 32 5 27 780.6 (published 26-1-84) is intended to provide a system for digitally transmitting video and picture telephone signals, respectively, with the bit rate of a PCM quaternary system, which allows for simple and Inexpensive way of transmitting additional audio channels, a signaling channel or other signals to 64 kbit / sec rasters with a modular and controllable structure, in addition to the video and picture telephone signals 10, respectively. To solve this task, the German application proposed a synchro-multiplexer on the sending side and a corresponding demul-multiplexer on the receiving side.

In the present application, this synchronous multiplexer and demultiplexer, respectively, are intended to provide an optimal uncomplicated frame structure with a suitable time wear length.

This is achieved by the means of claim 1.

Due to the multiplex frame of the invention with 10-bit time slots, the advantages of a speed reduction with the factor 10 over a 1-bit time slit are obtained and that with the usual overall encoding of the video information no further synchronization information is required for digital-to-analog converter.

Further advantages arise from optimal embodiments of the invention as set forth in the subclaims. Due to the matrix-shaped structure of the 32-line and 68-slot multiplex frame 30, the advantage of each slot being a transparent 2-Mbit / sec channel is obtained.

Due to the fact that for the synchronization, 10-bit time slots, each containing a synchronization word, are distributed equidistantly in the frame, a more efficient synchronization is achieved than at 1-bit synchronization time slots.

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Due to the connection of a first slot for synchronization signaling purposes, stereo sound channels and other purposes and due to the connection of a second slot having an equidistant distance from the first 5 slot of 33 slots to a transparent PCM-30 channel results in the video information contained in the 33 intermediate columns, an optimal small storage.

Due to the favorable choice of bit sequence 111000100 for the frame synchronization word, a very fast synchronization is achieved, because this sequence including its inverted version has good autocorrelation properties, which is distinguished by the fact that by bit offsets only small conformity probabilities appear with the other information. Further, as a result of the inverted choice of the second synchronization word, a synchronization comparator with almost the same realization appears.

The invention is explained in greater detail below, for example with reference to the drawing, in which: FIG. 1 shows an exemplary embodiment of a multiplex frame according to the invention with time wear connection; FIG. 2 and 3 are each a block diagram of an optimal basic embodiment of a multiplexer and a demultiplexer, respectively; and FIG. 4 is a flowchart of one of several possible frame synchronization algorithms.

In FIG. 1 shows the matrix-shaped structure of the frame with 68 slots and 32 lines. The slots 2-34 and slots 36-68 are intended for transmitting video information, slot 1 for transmitting the frame synchronization, (stereo) audio channels, signaling purposes and other purposes, and slot 35 for a transparent 2048 kbit / s channel, f. eg. PCM-30 or 2 x stereo audio channels. In column 1, the frame recognition word is placed in every fourth line beginning with line 1, where the frame recognition word R = 1111000100 is placed in line 1 and the inverted inverted line

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Formation R is located in the other of said lines.

In even numbers, a 1024-kbit / sec stereo channel T is transmitted, where in the last line an audio fill time slot ST is placed in the case of positive fill. The audio fill signaling TS occurs in the third line. In the case of sound overflow, the first time slot is found in the eleventh line (TU).

With this designation, maximum deviations of -2 for audio bit rates of 6 10 .1 line 7 are allowed, signaling for the fill PS for a 2,048-Mbit / sec channel, for example PCM-30, as found in column 35 ( P).

In the event of an overflow, the overflow becomes PU

transferred in the nineteenth line in the first slot, and in the case of positive filling, the last time slot in line 35 (SP) serves. For monitoring A, there is a time slot in the fifteenth line of the first column, and in the twenty-third line of this first column there is a time slot for, for example, facsimile transmission FX.

In the twenty-seventh time slot in column 1, a 64-20 kbit / sec channel F is available for free, and in the thirty-one time slot in this first column, the signaling S is transmitted for the image telephone signaling.

As stated above, the video and image telephone information, respectively, are transmitted in the remaining columns, whereby the image fill signaling SKB to reduce the effect of burst errors is placed in two far apart slots in the frame. Along with the actual fill information located in the twenty-second line of the twenty-fourth column 30 (SB), the fill infringement time slots are distributed equidistantly in the frame.

Of course, if compatibility with the PCM frame chain word is desired, this can also be transmitted in the first time slot and in the first part of the second time slot.

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FIG. 2 shows a block diagram of an optimal basic embodiment of a multiplexer for transmitting image information and associated signaling. There is seen a 10-bit bus to which on the input side is connected a 5 resilient memory ES, a 10-bit shift register for recording signaling information, two registers for issuing a first synchronization word R and a second inverted synchronization word R over the tristate. registers. On the output side is connected a 10-bit-10 parallel serial converter over which the serial output multi-bit bit stream of 139.264 Mbit / s is decreased. A clock supply unit generates all necessary signals for controlling the bus and for sensing the video signal. Here, after a low-pass filtering with a 9-bit analogue digital converter A / D, the video signal is coded together and together with a parity bit generated by a parity bit generator PB, read (write) as 10-bit words in the elastic memory as the scanning frequency F ^, which advantageously amounts to 13.5 MHz. Of course, instead of the aggregate coding, a 135-Mbit / s bit stream, which is encoded separately, can also be recorded in the resilient memory ES over series parallel converters with a width of 10 bits.

The resilient memory is read out at the (read) clock frequency of 13.9264 MHz under the slots 2-34 and 36-68, respectively, activating over a read control.

By means of a phase comparator, the phases of the write rate and read rate of the elastic layer are compared, whereby the reading rate, when obtained or underestimated by a predetermined phase difference value, is stopped at the nearest possible filling apartment and signaled accordingly, the phase comparator activating a 10-bit register SKB, which then gives the message to the bus.

FIG. 3 shows it to the synchronous multiplexer in e.g.

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5 2 corresponding synchronous demultiplexes on the receiving side. Here, too, there is a 10-bit bus to which, on the input side over a 10-bit Latch, is connected a 10-bit switch register as a serial parallel converter. On the output side 5 there is again an elastic memory ES, a 10-bit shift register as parallel serial converter for the signaling as well as comparators for ascertaining the frame synchronization R and the inverted synchronization word R. Furthermore, a - * - 0 comparator is connected on the output side. for finding the fill signaling SKB. A clock supply unit controlled by the bit rate * "in" derived from the incoming multiplex stream generates all necessary acquisition signals to control the 10-bit bus connected input registers - * - 5, respectively, output registers. there is a control device which is activated by the two synchronization comparators and, for example, operates according to the synchronization algorithm shown in Figure 4. The arriving serial bit stream of 139.264 Mbit / s becomes un-20 <3 ^ column 2-34 and 36-68 respectively. reads son 10-bit words in the elastic memory ES with the (write) rate of 13,926 MHz, the readout from the elastic memory is done by a (read) rate corresponding to the average write rate produced by a phase control circuit PC, 25 VCO The 10-bit word read from the elastic memory is supplied with a digital-analog converter which is activated by a fault detection device constituted by an additional comparator and a parity bit generator PB, comparing the parity bit generated by the parity bit generator ^ 0 with the parity bit provided in the word read. In case of non-conformity, the digital-to-digital converter D / A with the read beat is stopped. A low-pass filter is connected to the output of the digital-analog converter from which the transmitted video signal can be detached.

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The FIG. 4 shows a possible diagram for a frame synchronization algorithm using a 1 "0-bit offset with every 1 bit as long as there is no match between the received word and one of the synchronization words. As soon as a match is found, it is checked In the case of three consecutive matches, a column synchronization is detected, then line synchronization occurs, 10 being queried after the first synchronization word that initiates the frame. If one of the sync words is not found, no synchronization is detected and a new synchronization process is initiated.

Claims (8)

1. System for digital transmission of video and / or picture telephone signals with a bit rate of PCM quaternary system of 139.264 Mbit / sec. according to CCITT G 703.9, 5 wherein the analog video and video telephone signal are digitally encoded at a bit rate of 135 Mbit / sec, where on the transmitter side there is a multiplexer (sync-mux) by means of which the coded video and video telephone signal, if bit rate by means of a fill-in technique is brought to a whole multiple of 64 kbit / sec, together with synchronization signals (syn), with signaling (sign) and with additional narrowband signals and possibly also with fill signals for these additional narrowband signals each at the bit rate of 64 15 kbit / sec. or whole multiples thereof are synchronously bundled into a multiplex signal at bit rate 139.264 Mbit / sec, and where on the receiving side there is a demultiplexer (sync demux) by which the multiplex signal is again divided into the individual 20 signals, characterized by , that the multiplex signal formed by the multiplexer (sync-mux) and received by the demultiplexer (sync-demux) has a frame with 2176 time slots, each time slot consisting of 10 bits. The system according to claim 1, characterized in that the frame is divided into 32 lines and 68 columns, each time slot being characterized firstly by its line number and secondly by its slot number (Z, S), where the transfer takes place in a serially linear manner. . System according to claim 2, characterized in that the time slots in a slot (35) are intended to transmit a 2,048 Mbit / sec bit stream and the time slots in a 34 slot offset slot (1) are intended to transmit a 1,024 Mbit / sec bit stream and of sync, signaling, signaling and possibly filling signals. System according to one or more of the preceding claims, characterized in that for slots there are time slots distributed equidistantly 5. the frame and each contains a synchronization word in which one time slot (R) carries the inverted information of the others (R ). System according to claim 3, characterized in that the bit sequence 1111000100 (R) and the bit sequence 0000111011 (R) are used as frame synchronization words. System according to one or more of claims 3-5, characterized in that the first time slot in every four lines starting with the first line contains the frame synchronization word, that the time slots in column 35 are intended to transmit a 2,048 Mbit / sec. bit stream (e.g., for PCM (P)), and in a plesio-crown case, the first time slot in the seventh line is designated for the fill signaling (PS) and the first time slot in the nineteen line as overflow (PU) that the first time slot in even number lines is intended to transmit a 1,024-Mbit / sec bit stream (e.g. to stereo sound (T)), and in a plesio-crown case, the first time slot in the a third line intended for fill signaling (ts) 25 and the first time slot in the eleventh line for overflow (TU), that the first time slot in the fifteenth line is intended for transmitting an alarm signal (A), a monitoring signal, or other signals; the one before the time slot in the twenty-third line is intended to transmit a facsimile signal (FX), the time slot in the twenty-seventh line is intended to transmit a synchronous 64-kbit / sec bit stream (F), or of an asynchronous over-keyed signal with low bit rate, that the first time slot in the thirty-one line is intended for transmitting a signaling signal to image telephone and video signaling (S), respectively, and that the time slots in the slots 2-34 and 36-68 are intended for transmitting the image telephone. the video signal, respectively, wherein the second time slot in the first line and time slot # 46 in the eleventh line 5 contain the fill message (SKB) and the twenty-fourth time slot in the twenty-second line contains the fill information (SB). System according to one or more of the preceding claims, characterized in that the synchronous multiplexer (sync-mux) contains a 10-bit bus to which, in each case, via tristate registers, a resilient memory is connected ( ES), which is supplied in parallel with the encoded video or video television signal as 10-bit words, partly additional registers which provide the synchronization words, the fill message and the signaling word and partly as the output register a 10-bit parallel series converter , as well as a clock supply, by which the tristate registers connected to the bus are activated in the time slot sequence corresponding to the frame structure. 2® System according to one or more of the preceding claims, characterized in that the synchronous multiplexer (sync-demux) contains a 10-bit bus to which is connected partly a serial parallel converter as input register and partly an elastic storage (ES), from which the encoded video or picture telephone signal is derived in parallel as 10-bit words, partly comparators for synchronization and filling finding, partly a register for signaling, as well as a clock supply and a control device for the synchronization.