DK0585475T3 - Method of loading and testing a holding buffer memory for activating a coupling step information memory in a - Google Patents
Method of loading and testing a holding buffer memory for activating a coupling step information memory in aInfo
- Publication number
- DK0585475T3 DK0585475T3 DK92113106T DK92113106T DK0585475T3 DK 0585475 T3 DK0585475 T3 DK 0585475T3 DK 92113106 T DK92113106 T DK 92113106T DK 92113106 T DK92113106 T DK 92113106T DK 0585475 T3 DK0585475 T3 DK 0585475T3
- Authority
- DK
- Denmark
- Prior art keywords
- loading
- activating
- testing
- coupling step
- step information
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
- H04Q11/08—Time only switching
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
During the loading and reading-out for checking newly loaded addresses, the control memory (CM) is selected not cyclically but optionally, specifically in each case alternating with the said cyclic selection, in deviation from normal operation. This saves time. <IMAGE>
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP92113106A EP0585475B1 (en) | 1992-07-31 | 1992-07-31 | Method for charging and testing the control memory of a time stage in a switching network of a digital TDM exchange |
Publications (1)
Publication Number | Publication Date |
---|---|
DK0585475T3 true DK0585475T3 (en) | 1999-06-14 |
Family
ID=8209861
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DK92113106T DK0585475T3 (en) | 1992-07-31 | 1992-07-31 | Method of loading and testing a holding buffer memory for activating a coupling step information memory in a |
Country Status (5)
Country | Link |
---|---|
EP (1) | EP0585475B1 (en) |
AT (1) | ATE171585T1 (en) |
DE (1) | DE59209508D1 (en) |
DK (1) | DK0585475T3 (en) |
ES (1) | ES2121805T3 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0828913B2 (en) * | 1993-01-13 | 1996-03-21 | 日本電気株式会社 | Time multiplex switch |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2222727B1 (en) * | 1973-03-21 | 1977-04-29 | Materiel Telephonique | |
DE3264638D1 (en) * | 1981-04-03 | 1985-08-14 | Cit Alcatel | Digital connection network |
CA1171946A (en) * | 1981-09-11 | 1984-07-31 | Mitel Corporation | Time division switching matrix |
JPS58137391A (en) * | 1982-02-10 | 1983-08-15 | Fujitsu Ltd | Time switch circuit |
US4485467A (en) * | 1982-02-18 | 1984-11-27 | Teknekron Infoswitch Corporation | Digital information switch matrix with on-line/off-line diagnostic features |
US4858227A (en) * | 1987-08-25 | 1989-08-15 | Solid State Systems, Inc. | Space and time having multiplexed memories |
JPH0785547B2 (en) * | 1988-07-08 | 1995-09-13 | 日本電気株式会社 | Frame converter |
-
1992
- 1992-07-31 DE DE59209508T patent/DE59209508D1/en not_active Expired - Fee Related
- 1992-07-31 EP EP92113106A patent/EP0585475B1/en not_active Expired - Lifetime
- 1992-07-31 DK DK92113106T patent/DK0585475T3/en active
- 1992-07-31 ES ES92113106T patent/ES2121805T3/en not_active Expired - Lifetime
- 1992-07-31 AT AT92113106T patent/ATE171585T1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
ATE171585T1 (en) | 1998-10-15 |
EP0585475A1 (en) | 1994-03-09 |
EP0585475B1 (en) | 1998-09-23 |
DE59209508D1 (en) | 1998-10-29 |
ES2121805T3 (en) | 1998-12-16 |
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