DE9421435U1 - Phase comparator - Google Patents

Description

Utility model registration

Werner Hachmann and Stefan Hachmann, In der Kuhle 9a
42555 Velbert-Lanqenberq

Phase comparator

The innovation concerns a phase comparator.

Such phase comparators are primarily used to test medium-voltage systems. Medium-voltage systems are systems that work with alternating voltages between 1 and 52 kilovolts (kV). The operating status of such medium-voltage systems must be determined. To do this, it must be determined whether a certain phase of the alternating voltage is present at all. Furthermore, the phase difference between two alternating voltages tapped at different points must be determined. Alternating voltages with a phase difference of up to 15° are still considered to be in phase.

Alternating voltages with phase differences of more than 60° clearly indicate phase imbalance. There is a transition area in between.

In order to be able to work with manageable voltages during measurements, partial voltages in the order of a few volts are taken from the voltages using a capacitive voltage divider. These are then further processed (DIN VDE 0681 Part 7). The phase comparator then provides "binary" displays in the form of "voltage present", "phases equal" or "phases unequal". The displays can be made using light-emitting diodes, for example.

It is essential that the phase comparator itself is functional. A false reading due to a malfunction of the phase comparator can have serious consequences.

The innovation is based on the task of creating an improved phase comparator for the present or similar purposes.

In particular, the innovation is based on the task of creating a phase comparator that is simple in design and works reliably.

The new phase comparator is characterized by

Means for generating a time clock, zero point switch for

Determining at least three zero crossings of the

AC voltages with respect to this timing, and means for

Determining the phase positions of the alternating voltage related to the

Timing from the respective zero crossings and means for determining the difference between the phase positions thus determined.

The basic principle of phase comparison according to the innovation is as follows: Three zero crossings are determined for each of the two alternating voltages. From the position of these zero crossings in relation to the time cycle, the phase of each of the alternating voltages in relation to the time cycle can be determined. The difference between the phases determined in this way is then determined in the form of a corresponding number of time cycles.

Each of the alternating voltages may be slightly offset from the zero line. The zero crossings then do not follow one another at exactly the same distance. The time interval between the first (rising) and the second (falling) zero crossing is smaller than the time interval between the second (falling) and the third (rising) zero crossing. This indicates that the zero line of the measurement is offset upwards relative to the alternating voltage. If it is larger, it indicates that the zero line of the measurement is offset downwards relative to the alternating voltage. The offset is greater the greater the difference between the time intervals.

The "means for determining the phase positions ^11" therefore contain, in a further development of the innovation, means for determining and mathematically taking into account a zero line offset of the alternating voltages from unequal time intervals of the zero crossings.

In this way, the measurement and correction of a zero line offset is reduced to a count of time cycles.

Before the phase comparison, it is preferably determined whether alternating voltages of sufficient amplitude are present at the measuring points. This can be done by using a threshold switch for each of the two alternating voltages, to which the alternating voltage is connected, means for

10 " ·

Determining the time interval during which the threshold value is exceeded by the respective alternating voltage, and means for indicating whether the time interval falls below a predetermined limit value as an indication of the presence or absence of the alternating voltage.

If the amplitude of the alternating voltage is greater than the threshold value of the threshold switch, but only slightly exceeds this threshold value, then the alternating voltage is only greater than the threshold value for a short time interval. This time interval is determined, for example, as the number of time cycles. If, on the other hand, the amplitude of the alternating voltage is large compared to the threshold value of the threshold switch, then the alternating voltage is above the threshold value for practically the full half period. A limit time interval can now be set: If the time interval during which the alternating voltage exceeds the threshold value of the threshold switch is shorter than this limit time interval, then this means: "No voltage". If the time interval during which the alternating voltage exceeds the threshold value of the threshold switch is longer than this limit time interval, then this means: "Voltage present". Here too, the voltage measurement is reduced to a count of time cycles.

Preferably, means are also provided for checking the frequency equality of the two alternating voltages before determining the difference in the phases. This ensures that the frequencies of the two alternating voltages match sufficiently precisely to enable a meaningful phase measurement. The frequencies can be determined from the number of time cycles in the interval between one zero crossing and the next but one. The frequency measurement is therefore also limited to a count of

11 *

The frequency comparison consists of a comparison of timing numbers.

The means for checking frequency equality, the means for determining the phase positions and the difference between the phase positions, the means for determining the zero line offset and the time interval determining and evaluating means can be formed by a microprocessor programmed for this purpose. Instead, however, an application-specific integrated circuit (ASIC) can also be provided for these functions.

The phase comparator can also contain self-testing means for testing the functionality of the phase comparator. These self-testing means can contain means for checking the battery voltage of a battery that supplies the phase comparator, means for testing display components by which results of the phase comparator can be displayed, e.g. light-emitting diodes, and means for self-testing the phase measurement.

An embodiment of the innovation is explained in more detail below with reference to the accompanying drawings:

Fig.l is a schematic representation of a voltage display system in which the phase comparator is applied.

Fig.2 is a block diagram of a phase comparator. 30

Fig.3 shows an implementation of the input impedance in the circuit of Fig.2.

Fig.4 shows the structure of the zero-voltage switch in the circuit of Fig.2.

12

Fig.5 shows the structure of the threshold switch in the circuit of Fig.2.

Fig.6 shows the waveform of the alternating voltage, which shows a zero line offset, and the corresponding output signal of the zero point switch with three zero crossings, which is fed to the microprocessor.
10

Fig. 7 illustrates the operation of the threshold switch of Fig. 2 and shows two alternating voltages of different amplitudes and their relationship to the threshold of the threshold switch.
15

Fig.8 shows a modification of the circuit for generating a "voltage present" signal using a threshold switch.

Fig.9 shows the power supply of the microprocessor using a button.

Fig.10 shows the circuit of light-emitting diodes for displaying the operating status of the medium-voltage system being tested.

Fig.11 shows a circuit for checking the function of the LEDs.

Fig.12 shows a circuit for internally generating AC voltages for self-testing purposes.

Fig.13 shows a circuit for performing a battery test.
35

Fig.14 is a flow chart for turning on the microprocessor.

Fig.15 shows a first section of a flow chart for the self-test of the phase comparator.

Fig.16 shows a second section of the flow chart for the self-test of the phase comparator.

Fig.17 shows a third section of the flow chart for the phase comparator self-test.

Fig.18 shows a flow chart for the internal signal generation according to the values stored in the value table.

Fig.19 shows a flow chart for a program interruption (interrupt routine) for reading stored values from a value table. 20

Fig.20 shows a table with the case distinctions of the measurement routine.

Fig.21 shows a flow chart of the phase comparison in the measurement routine.

Fig.l illustrates the use of the phase comparator for determining the operating state of a medium-voltage system, i.e. a system with voltages between 1 kV and 52 kV. The medium-voltage system contains an n-phase system, of which there are two lines 10 and 12, on which the high voltages to be tested are located. A processable partial voltage is capacitively tapped from each of the lines. A coupling electrode 14 with a dielectric 16 is used for this purpose. This coupling electrode 14 forms with the line, e.g. 12, and the

a first capacitor 18 in the dielectric between them. The first capacitor 18 forms a capacitive voltage divider between line 12 and earth with a second capacitor 20. A partial voltage proportional to the voltage on line 12 (or 10) and essentially in phase with it is tapped off from capacitor 20. This partial voltage is applied via an interface 22 to a phase comparator 24, which is yet to be described. Phase comparator 24 has input impedances, which are represented here by a resistor 26. An overvoltage protection device 28 is connected in parallel to capacitor 20. This is known per se and only serves to explain the use of the phase comparator.

Fig.2 is a block diagram of the phase comparator 24. Two alternating voltages, designated L and L _x , can be applied to the phase comparator 24 via two inputs 30 and 32.

The alternating voltage L is applied in parallel via an input impedance 34 to a zero point switch 36 and to a threshold switch 38. The output of the zero point switch 36 is applied to an input 40 of a computer 42. The computer 42 is formed here by a microcontroller which is commercially available under the name PIC 16C84. The signals received at the output of the threshold switch 38 are processed in a manner to be described by a signal conditioning circuit 44 and deliver a signal to an input 46 of the computer 42. The signals from the zero point switch 36 are square-wave voltages and deliver at least three consecutive zero crossings of the alternating voltage L. The signal from the signal conditioning circuit 44 is a binary signal and signals whether or not an alternating voltage L is present at all. In a corresponding manner, the alternating voltage L _x is applied via an input impedance 48 in parallel to a zero point switch 50 and to a threshold switch 52. The output of the zero point switch 50 is applied to an input 54

X3

of the computer 42. The signals received at the output of the threshold switch 52 are also processed by a signal conditioning circuit 56 similar to the signal conditioning circuit 44 and deliver a signal at an input 58 of the computer 42. The signals from the zero point switch 50 are again square-wave voltages and deliver at least three consecutive zero crossings of the alternating voltage L _x . The signal from the signal conditioning circuit 56 is a binary signal and signals whether an alternating voltage L _x is present.

The computer 42 receives a timing signal from a clock generator 60.

The computer 42 controls its operating voltage and the operating voltage of the phase comparator 24 from a power supply 62 via an ON/OFF circuit 64 and a control input 66. The voltage of the operating voltage is stabilized by a stabilization circuit 68.

Circuits 72 and 74 for port expansion are located at a port 70. This creates additional ports for the display device 76 and for a switch represented by block 78 for controlling the self-test. The self-test includes a circuit 80 represented by a block for battery testing and testing of the shields for the alternating voltages L and L _x , which is represented by blocks 82 and 84 respectively. A "window comparator" 86 is also provided for the self-test to test the burning voltages of the light-emitting diodes used for the display.

An external monitoring circuit ("watchdog") is connected to port 88 of the computer 42. Port 88 is also connected to a circuit 92. The circuit 92 generates and

16 " '

feeds two amplifiers 94 and 96 with the higher voltage required to generate the sine wave. Ports 98 and 100 supply pulse width signals, as will be described later. From these pulse width signals, sine signals are generated by circuits 102 and 104 for the self-test of the phase comparison. These sine signals are amplified by amplifiers 94 and 96 and are connected to terminals 106 and 108.

The circuit of the input impedances 34 and 48 is shown in Fig. 3.

A capacitive voltage divider consisting of capacitors 116 and 118 is connected to terminals 110 and 112 of interface 22 via a resistor 114. Resistor 114 protects capacitors 116 and 118 from critical voltage rise rates D _u /Dt and compensates for the phase-shifting component of the real part of the parallel circuit comprising capacitor 118, the Z-diodes 124 and 126 connected in opposition to one another, and measuring resistor 128.

The cable capacitance 120 of the connecting cable caused by the connection line is located between terminals 110 and 112. Parallel to capacitor 118 is an overvoltage protection device 122 consisting of two Zener diodes 124 and 126 connected in opposition. An alternating voltage drop across a resistor 128 is located between two terminals 130 and 132. If terminal 132 is not connected as a virtual zero point, but is connected to GND (device ground), terminal 130 must be biased via a resistor 134.

The voltage at terminal 130 is connected via a resistor 134 (Fig.4) to an input of an operational amplifier 136. The voltage at the input of the operational amplifier is limited by diodes 138 and 140. The resistor 134 and the diodes 138 and 140 protect the input of the

Operational amplifier 136 against overvoltages that are greater than its supply voltage. A reference voltage from a reference voltage generator 142 is present at the second input of operational amplifier 136.
5

The voltage at terminal 130 is also connected to an input of an operational amplifier 146 via a resistor 144 (Fig. 5). The voltage at the input of operational amplifier 146 is also limited by diodes 148 and 150. Resistor 144 and diodes 148 and 150 again protect the input of operational amplifier 146 against voltages that are greater than the supply voltage. A reference voltage from a reference voltage generator 152 is connected to the second input of operational amplifier 146.

The circuit of Fig.4 represents the zero voltage switch 36 or the zero voltage switch 50 of Fig.2. The circuit of Fig.5 represents the threshold switch 38 or the threshold switch 52 of Fig.2.

The operation of the zero-voltage switches 36 or 50 is explained in more detail in Fig.6.

In Fig.6, an alternating voltage to be tested is shown as a sinusoidal signal waveform 154. The time cycles 156 specified by the clock generator 60 are marked schematically on the time axis t. As can be seen, the alternating voltage is slightly offset from the zero line symbolized by the time axis (this offset can have a positive or negative sign and is due to the component tolerances). The operational amplifier 136 converts this into a square wave voltage 158, as shown in the lower part of Fig.6. The edges of the square wave voltage 158 define three zero crossings A, B and C of the alternating voltage 154. As a result of the zero line

18 "" ■

offset, the time intervals t^, t2 between the zero crossings A and B and between the zero crossings B and C are unequal. The zero crossings are fed to the computer. The number of time pulses 156 in the time intervals t^ and t£ are counted. From the differences in the number of time pulses 156, the computer 42 determines the zero line offset and the correct phase of the alternating voltage in relation to the time pulse.

The reference voltage from the reference voltage generator 142 serves here to carry out at least an approximate zero line adjustment.

Fig.7 illustrates how, using the threshold switch of Fig.5, a signal is obtained as to whether or not an alternating voltage is present at all. 160 designates the signal curve of an alternating voltage of relatively low amplitude applied to the operational amplifier 146. 162 designates the signal curve of an alternating voltage of relatively high amplitude applied to the operational amplifier 146. The threshold switch 38 with the operational amplifier 146 and the reference voltage generator 152 sets a threshold 164. The two alternating voltages exceed the threshold in a middle range around the maximum. In the case of the alternating voltage 160, the threshold 164 is exceeded by the signal curve in a time interval t3. In the case of the alternating voltage 162, the threshold 164 is exceeded by the signal curve in a time interval t.4. which is greater than the time interval t3. The operational amplifier 146 supplies square-wave signals such as the square-wave signal 166. These square-wave signals 166 are connected to the computer 42. The computer 42 determines the length of the square-wave signals 166 by counting the time pulses of the clock generator 60 that appear while the square-wave signals 166 are present. If the number

of the time cycles counted in this way is less than a certain limit, then the computer signals: "No voltage". If, on the other hand, the number of time cycles counted is greater than the limit, then "Voltage present" is signalled. 5

In order to relieve the computer 42 of the task of counting the time cycles, the arrangement of Fig. 8 can also be used. In this case, the exceedance or undershoot of the limit value is determined analogously and a single binary signal is generated accordingly, which is connected to the computer 42.

In the arrangement according to Fig.8, a threshold switch is also provided in the manner of Fig.5. Corresponding parts are provided in Fig.8 with the same reference numerals as in Fig.5. The output signal of the threshold switch is, as explained with reference to Fig.7, a sequence of pulses, the pulse width of which depends on the amplitude of the alternating voltage. These pulses are then filtered by a filter 168 and rectified by a rectifier 170. This produces a direct voltage, the level of which depends on the pulse width of the pulses. The direct voltage is connected to a Schmitt trigger 172. The Schmitt trigger 172 goes into a first switching state, signaling the presence of an alternating voltage, when the direct voltage exceeds a certain limit value. The Schmitt trigger 172 goes into a second switching state, signaling the absence of an alternating voltage, when the direct voltage falls below the limit value. The binary signal (1 or 0) thus obtained from the Schmitt trigger is also connected to the computer 42.

Fig.9 shows in detail the ON/OFF circuit 64 of Fig.2.

20 "

The phase comparator 24 is switched on and off by a button 174. If the phase comparator 24 is switched on, then it must be switched off by pressing a button. If the phase comparator 24 is switched off, pressing the button must switch it on.

When the button 174 is temporarily pressed, a partial voltage determined by a Zener diode 178 is passed from the supply voltage from the power supply (battery) 62 on the line 176 via a resistor 180 to a monostable flip-flop 182. The monostable flip-flop 182 controls a series transistor 188 via an OR gate 184 and a resistor 186, which lies with its emitter-collector path in the line 176 and connects the power supply 62 (Fig. 2) to the port 66 of the computer 42. The pulse from the monostable flip-flop 182 therefore passes through the OR gate 184. The computer 42 is connected to voltage. The computer 42, when it is connected to voltage, supplies a signal at an output 194, which is connected to the second input of the OR gate. After resetting the monostable flip-flop, the series transistor is kept conductive via the output 194 and the OR gate 184. The computer 42 remains connected to the power supply 62.

If the computer 42 is connected to the power supply 62, then a brief actuation of the button 174 via an input 190 causes the computer 42 to be switched off. A Zener diode 178 limits the height of the pulse connected to the input 190. If the computer 42 is switched off, then the output voltage at the output 194 of the computer 42 is eliminated. After the monostable flip-flop 182 has been triggered again, the transistor 188 is blocked.

Fig.10 shows the display device 76 of Fig.2 in detail. The states of the voltages to be tested are displayed "binary" as "voltage present" or "voltage not present", "voltages in phase" or "voltages out of phase" as well as "incorrect measurements" or "fault" by means of LEDs 196, 198, 200, 202, 204, 206 and 208. Each of the LEDs 196 to 208 is connected to the supply voltage via a resistor 210, as described using the LED 196. The supply voltage is supplied via a line 212. The emitter-collector path of a transistor 214 is connected in series with the LED 196. The emitter of the transistor 214 is connected to GND (device ground). The base of the transistor is connected via a resistor 216 to a wire of a bus 218, via which control signals from the computer 42 are switched to the display device 76. In addition, the base of the transistor 214 is connected via a capacitor 220 to GND (device ground). The voltages dropped across the LEDs 196 are tapped via the wires of a cable 222 for testing purposes.

Fig.11 shows a "window comparator" 86 (Fig.2) for testing the burning voltages of the LEDs 196 to 208 (Fig.10). The window comparator 86 is controlled by the computer 42. It checks whether the burning voltages of the LEDs are within predetermined "windows". The window comparator 86 contains electronic switches 224, 226, 228, 230, 232, 234 and 236, which are controlled one after the other by the computer via a bus 238 during the course of the test program. Each of the electronic switches 224 to 236 switches a wire of the cable 222 (Fig.10) to a comparator arrangement 240. The comparator arrangement 240 contains two comparators 242 and 244. The respective switched-through voltage is applied to the "lower" input of the comparator 242 and to the "upper" input of the comparator 244. A voltage divider with three resistors 246, 248 and 250, which is connected between the

supply voltage and GND (device ground), supplies an upper reference voltage at a tap 252 and a lower reference voltage at a tap 254. The upper reference voltage is at the "upper" input of the comparator 242. The lower reference voltage is at the "lower" input of the comparator 244. The comparator 242 switches and supplies an output signal if the burning voltage at the lower input, switched through via the respective switch 224 to 236, is less than the upper reference voltage at tap 252. The comparator 244 switches and supplies an output signal if the burning voltage switched through in each case is greater than the lower reference voltage at tap 254. The outputs of the comparators 242 and 244 are linked by an AND gate 256. The AND gate 256 supplies a "logic 1" signal to the computer 42 via its output 258 when the respective applied burning voltage is in a "window" specified by the upper and lower reference voltage. The burning voltages of the LEDs vary depending on the color of the LED. In the present case, the LEDs 196, 200 and 204 have different colors than the other LEDs and a lower burning voltage. To take this into account, the control signals of the computer 42 for the associated electronic switches 224, 228 and 232 are linked via an OR gate 260. The output of the OR gate 260 controls another electronic switch 262. The switch 262 then becomes conductive and places a resistor 264 in parallel with the resistor 250 of the voltage divider. This pulls the upper and lower reference voltages down and adjusts the window to the lower operating voltage of the LEDs 196, 200 and 204.

Fig. 12 shows in detail the formation of the sinusoidal test voltages for testing the phase comparison devices.

For testing purposes, the computer 42 supplies pulse sequences in which the pulse width changes sinusoidally via ports 98 and 100 (Fig. 2) and a cable 266. The pulse sequences are smoothed by filters. Each of the filters consists of a resistor 268 or 270 and a capacitor 272 or 274. The smoothed, sinusoidal voltages are amplified by the amplifiers 94 and 96 (see also Fig. 2). The amplifiers 94 and 96 supply sinusoidal test voltages with known phase relationships at the terminals 106 or 108.

Fig.13 shows the circuit 80 for battery testing. A partial voltage of the battery voltage applied to a terminal 276 is compared at a comparator 278 with a voltage of a reference voltage generator 280. The reference voltage generator 280 is fed by the supply voltage. The partial voltage of the battery voltage is tapped at a voltage divider with resistors 282 and 284. The supply voltage is switched off when the phase comparator is not in operation. However, current would constantly flow through the voltage divider 282, 284 and load the battery. For this reason, the emitter-collector path of a transistor 286 is connected in series with the voltage divider 282, 284. The base of this transistor 286 is connected to a voltage divider with a resistor 288 and 290 connected between the terminal 276 and GND (device ground). The emitter-collector path of a transistor 292 is also connected in series with the resistor 290. The base of the transistor 292 is connected to a voltage divider with resistors 294 and 296 connected between the supply voltage and GND (device ground).

As a result, when the supply voltage is switched off, the transistor 292 is blocked, and thus the transistor 286 is also blocked.

The operation of the computer 42 and the circuits interacting with it is described below using flow charts.

Fig.14 illustrates the switching on process. A rectangle 298 "ON/OFF" symbolizes the actuation of the button 174 in Fig.9. A rhombus 300 corresponds to the check whether switching on or switching off occurs. In the former case (yes), the signal at port 194 is set to "logical 1" according to rectangle 302.

This initiates a return to the main program, as shown by the oval 304. In the second case (No), the signal on port 194 is reset to "logical 0". This is shown by the rectangle 306. No further activity takes place, as indicated by the "Wait" rectangle 308.

The main program first controls a self-test of the

Phase comparator. The battery, the

Shielding, the LEDs of the display and voltage and

Phase measurement is checked. A flow chart of this part of the main program is shown in Figures 15, 16 and 17.

which represent consecutive sections of the flow chart.

In Fig.15, the ON/OFF circuit according to Fig.14 is initially shown as a rectangle 310, whereby it is assumed that a switch-on has taken place. A self-test flag is then set. This self-test flag signals to the device that a self-test program is running and, for example, no display should be made. The setting of the self-test flag is shown by a rectangle 312. The battery is then selected for the battery test according to Fig.13. In practice, the output of the comparator 278 in Fig.13 is queried. This is shown by a rectangle 314. Before the evaluation of the

2 B

A waiting time of 10 ms is switched on during the battery test to take into account transient processes. This is represented by a rectangle 316. After this time has elapsed, the battery test is evaluated. This is represented by a rectangle 318. During the evaluation, it is checked whether the battery is in good condition, i.e. whether the required battery voltage is present at terminal 276 in Fig.13. This is symbolized by the rhombus 320. If this is not the case (No), then a battery error flag is set. This is represented by a rectangle 322. From there, a loop 324 goes back to the normal program flow. If the battery is OK (Yes), then this finding is stored in an EEPROM. This is represented by a rectangle 326.

You will then be asked whether only a battery test should be carried out or whether the entire test program should be run. The battery is checked not only when it is switched on but also during the course of the measurements. This question is shown in Fig. 15 by a rhombus 328. If only a battery test should be carried out (yes), the self-test indicator is reset to "logic 0". This is shown by a rectangle 330. The flow chart then returns to the main program. This is shown by an oval 332 ("Return"). If the answer to the question is "no", then the test program continues.

The means for testing the shielding of the lines for the two alternating voltages L and L _x are then selected, which are designated 82 and 84 in Fig. 2. Such means for testing shielding are known per se and are therefore not described in detail here. This selection of the means for testing the shielding is represented by a rectangle 334.

Here too, a delay is switched on before the test is evaluated in order to take into account transient processes. This is represented by a rectangle 336. Then it is checked whether

the shielding is flawless. This is again represented by a rhombus 338. If the shielding is not flawless (No), then a shielding error flag is set. This is represented by a rectangle 340. The test result is stored in the EEPROM. This is represented by a rectangle 342. If the shielding is flawless (Yes), then this test result is also stored in the EEPROM. This is represented by the loop 344.

The test program continues with the flow chart of Fig.16 as indicated by the triangle "1".

Fig. 16 shows the testing of the LEDs 196 to 208 according to Fig. 10 and 11.

The LED test is "selected", i.e. the necessary configuration of inputs and outputs is created in the circuit of Fig. 10 and 11. This is represented by a rectangle 344. The LEDs 196 to 208 are identified by a consecutive number from "1" to "7" and are controlled one after the other by the computer 42 via the bus 238 and the switches 224 to 236 in this order.

The program works with two variables that are present in two counters of the computer 42. The first variable "LED" is the light-emitting diode that is switched on by the computer 42 during the light-emitting diode test. The second variable "LEDtest" specifies the light-emitting diode whose burning voltage is to be tested with the window comparator 86. If the display device 76 is intact, only the light-emitting diode that is switched on should burn, while no burning voltage drops on the other light-emitting diodes.

• *

For this purpose, the computer 42 is first set to an "LED" number = 1. This is represented by a rectangle 346. A previous display of the LEDs is deleted. This is represented by a rectangle 348. The computer 42 then switches on the LED 196 ("1") via the switch 226. This is represented by a rectangle 350. The counter for the LED to be tested is set to LEDtest ^{= 1.} The burning voltage of the LED 196 is then tested using the window comparator 86 of Fig. 11. This is represented by a rectangle 254. The result of the test is set as a bit of a bit pattern in the assigned memory location. This is represented by a rectangle 356. Then the computer 42 is advanced to the next "LED-(-est"~ ^Zani . This is represented by a rectangle 358. A check is made to see whether the total number of LEDs present has been exceeded. This is represented by the rhombus 360. If this is not yet the case (no), then the program flow is returned to the "input" of the rectangle 354 via loop 362. With the LED 196 still switched on, the operating voltage of the LED 198 ("2") is checked and the test result is stored as the second bit in the bit pattern. Then there is another advance to the next "LED-t _: est"~ ^Zan l ^This continues with repeated running through of the loop until the total number of LEDs is exceeded during this advance. Then the result of the query at the rhombus 360 is "yes". A bit pattern is then stored which, if the display device is intact, is 0000001: The switched on LED 196 lights up and supplies a voltage within the window specified by the window comparator 86, the other LEDs 198 to 208 do not light up. The bit pattern obtained from the tests of the window comparator 86 (eg 0000001) is now compared with a bit pattern in which one position corresponding to the switched on LED (here the LED 196) is replaced by a "1" and the remaining positions by a "0".

are subjected to an exclusive OR operation. If a "1" occurs on a LED that is not switched on, or if a switched on LED does not supply a voltage and generates a bit "0", then the exclusive OR operation provides an output of "logical 1". If only the switched on LED supplies a voltage, then the output of the exclusive OR operation is "0". Either two inputs are then "1" or both inputs are "0". This exclusive OR operation is represented by a rectangle 362. If the result of the exclusive OR operation is >0 (yes), then a LED is defective. This test is represented by a rhombus 364. In this case, the flow chart continues to rectangle 366. Rectangle 366 symbolizes the storage of the number of the defective LED. The variable LED, i.e. the number of the LED to be switched on, is then increased by 1. This is represented by a rectangle 368. If the exclusive OR link 362 is not >0 (No), then the flow chart goes directly to the rectangle 368 via a loop 370.

The next test, represented by a rhombus 372, is aimed at whether the variable LED is greater than the total number of LEDs after being increased by 1. If this is not the case (No), then a loop 374 leads back to the "Clear display" rectangle 348. The LED 196 is cleared. The next LED 198 is now switched on, which corresponds to the LED number increased by 1. The test process then runs again for all LEDs from the LED 196 (LED _test ^number " ^llf ) via the switched on LED 198 to the LED 208. This continues until finally the LED 208 (LED number = 7) is switched on and after the test process the increase in the LED number by 1 produces a number that exceeds the number of LEDs. The test result is then saved. This is represented by a rectangle 376.

The flow chart then goes to Fig.17. This is indicated by the triangles marked "2".

According to Fig. 17, a self-test of the phase measurement is carried out. For this purpose, two alternating voltages with a defined relative phase position are generated. The phase positions of these alternating voltages are determined in the manner described at the beginning with reference to Figures 4 and 6. It is checked whether the phase positions determined in this way match the phase positions of the alternating voltages generated for the test. To form the alternating voltages, the values of the alternating voltage are stored in a memory as a table. The values are called up one after the other by "pointers" at a fixed time interval and switched to two channels. The pointers can call up the values synchronously. In this case, two alternating voltages in phase are generated. The pointers can also call up the values with an offset, i.e., figuratively speaking, they can each be on different "rows" of the "table". In this case, two alternating voltages are generated that are out of phase with each other. The values of the value table, called up at a given time interval, are converted into pulses of the corresponding duration (pulse duration modulation). This creates pulse sequences with pulses of different widths, corresponding to the course of the alternating voltage to be generated. These pulse sequences are filtered and produce alternating voltages with the signal course corresponding to the table. This signal course is usually sinusoidal. However, sawtooth or triangular signal courses can also be generated in the same way.

In Fig.17, the pulse width modulation (PDM) is "selected". The supply voltage for the amplifiers 94 and 94 (Fig.12) is applied and the outputs 98 and 100 are activated. This is done by

a rectangle 378 is shown. The "pointers" for the two alternating voltages L^ and L _x to be generated are set to 0°.

This is shown in Fig.17 by the rectangles 380 and 382. Then the subroutine "PDM pre-run" shown in Fig.17 by rectangle 384 runs. This subroutine is shown in Fig.18. After the start shown by rectangle 386, the subroutine contains a query "PDM _L1 > 0 ?".

This is represented by a rhombus 388. PDM _L i is the value for L^ stored in the table. If this is not the case (No), then the signal "0" is output on line 98 (Fig.2). This is represented by a rectangle 390. If this is the case, then the signal "logic 1" is output on output 98. This is represented in Fig.18 by a rectangle 392. In both cases, the flow chart then continues with a query "PDMl _x ^> ° ^? " ^This is represented ⁱⁿ Fig ^. 18 by a rhombus 394. ^PDMl _x is the second alternating voltage L _x stored in the table. The two values PDMli and PDMl _x can be different from one another ^.

if the pointers are on different "rows" of the table. If the question is answered in the negative (No), the signal "0" is generated at output 100. This is represented by a rectangle 396. If the question is answered in the affirmative (Yes), the signal "logical 1" is generated at output 100. This is represented by a rectangle 398.
25

A time counter is then set to the maximum possible pulse duration "MaxPDM". This maximum possible pulse duration can be, for example, 255 time cycles of the clock generator 60 (Fig. 2). Setting the time counter to the maximum possible pulse duration is represented by a rectangle 400. This time counter is then counted down step by step. "Time" means the counter reading of the time counter. This counter reading is reduced by 1 at the next cycle. This is represented by a rectangle 402.

The "logic 1" signals at outputs 98 and 100 remain until they are changed during the subroutine.
5

Various queries then follow: Is the time counter empty, i.e. would the "time" counter reading be zero after the counter reading is reduced by one? This is represented by a rhombus 404. If this is not the case (no), then the next query follows, again symbolized by a rhombus 406: Is the "time" counter reading less than the value from the table just tapped by the "pointer" for the first alternating voltage, namely PDMli? If this is the case (yes), then the signal "0" is output at output 98. Output 98 thus switches from "logical 1" to "0".

This is represented by a rectangle 408. If "Yes" and "No" are selected, a further check is carried out on the rhombus 406 to see whether the counter reading "Time" is less than the value of the table just read by the corresponding pointer for the second alternating voltage. This is represented by a rhombus 410. If Time < PDMl _x ( ^Yes ) /, the output 100 is set to "0". This is represented in Fig. 18 by a rectangle 412. In this case, just as after setting the output 100 to zero, the counter reading of the time counter is reduced by 1 via a loop 414.

Then the loop described is continued until the answer to the query according to Rhombus 404 "Time = 0 ?" is "Yes".
30

This cycle generates a pulse of constant height at outputs 98 and 100, whereby the duration of the pulse is determined by the digitally stored and read-out value PDMli or PDMl _x . All values in the table are then converted into pulses one after the other in the manner described.

variable width. The leading edges of the pulses are spaced equally apart from one another. The duration of each pulse depends on the respective stored value PDMli or PDMl _x . In this way, several cycles are generated by the alternating voltages.

This is shown in Fig.19 as a flow chart.

The subroutine of Fig. 18 is interrupted at fixed time intervals, which are determined by a timer and are slightly longer than the maximum possible pulse duration. First, it is checked whether the interruption is actually caused by the timer. This is represented by a rhombus 416.

If this is not the case (No), then the interruption has other causes. This is represented by a rectangle 418. In this case, a loop 420 returns to the subroutine of Fig. 18. If the interruption is due to the timer (Yes), then the "pointers" switch to the next line of the table of stored signal values. This is represented by the rectangles 422 and 424 for the two sets of values PDMli ^and ^· P ⁰ ^Lx. A check is made to see whether the PDMLi value obtained is greater than the maximum possible pulse duration MaxPDM. This is represented by a rhombus 426. If this is the case (Yes), the value for PDMli is set ^to -f 0. A check is then made in the same way to see whether the PDML _X value is greater than the maximum possible pulse duration. This is represented by a rhombus 428. If this is the case (yes), the value for PDMl _x is set ^to °. This is represented by a rectangle 430. In both cases, the values for PDMli ^and ^ ^p ^ ^M Lx are then replaced in the subroutine of Fig. 18 by the current values formed according to Fig. 19. This is represented in Fig.19 by a rectangle 432. There is then a return to the subroutine of Fig.18. This interruption and

33

The hands are advanced at the fixed rate of the timer.

In the subroutine of Fig. 18, a query "often repeated" is then made, i.e. it asks whether the cycle described has been repeated several times in order to take into account transient processes, e.g. in amplifiers. This query is represented by a rhombus 434. If this is not the case (no), the flow chart jumps back to the start, namely to the rhombus 388, via a loop 436. The entire subroutine is then run through again. If the answer is affirmative (yes), the program goes on to the measurement during the self-test. This is represented in Fig. 18 by a rectangle 438.

The program described supplies pulse sequences with a fixed frequency, whereby the pulse widths change according to the digitally stored values in the table. The pulse-duration modulated signals thus obtained are smoothed by filters 268, 272 or 270, 274 and amplified by amplifiers. This produces alternating voltages with a predetermined phase relationship.

The phase relationships of the alternating voltages generated in this way for test purposes are measured in the manner of Fig.4 and 6 and compared with the specified phase relationship. The results obtained are evaluated. This is shown in Fig.17 by a rectangle 440. A rhombus 442 in Fig.17 symbolizes a query as to whether the self-test showed that the means for phase measurement are working properly. If this is not the case (No), an error flag is set. This is shown by a rectangle 444. The positive or negative result is stored. This is shown by a rectangle 446. Finally, it is checked whether the error flag is set to "0". This is shown by a rhombus 448. If an error was found, then the

If the error flag is not "O" (No), then the phase comparator is switched off. This is represented by a rectangle 450. If the error flag is "0" (Yes), then a self-test flag is set to "0". This is represented by a rectangle 452. Then the measurement can begin.

The measurement is carried out using the same means for the internally generated alternating voltages as for the voltages to be tested.

First, the three zero crossings A, B and C of the voltages are determined. At time A the signal goes from "logic 0" to "logic 1", at time B the signal goes from "logic 1" to "logic 0" and at time C the signal goes from "logic 0" to "logic 1" again. The times A, B and C are determined in relation to the clock of the clock generator 60. For the frequency test, the period durations T-^i and T^ _x for the two alternating voltages are

^T L1 = C _L1 - A _L1

- ^A Lx

The period lengths must not exceed
differ from each other. It must

If this is not the case, an error flag is set. If the period lengths and thus the frequencies of the two alternating voltages match within the specified tolerances, the zero line offset is corrected.

IpT -VT HP W ■» -^ -^ ~m ~r ~-v &mdash;

If, for example, the zero point switch 36 for the alternating voltage L^ switches at exactly 0 volts, i.e. switches when the voltage Li>0, but the zero point switch 52 for the alternating voltage L _x only switches when L _x >2 volts, then a phase shift would be displayed for alternating voltages that are exactly in phase. The shift in the zero line means that the time intervals between the zero crossings become unequal in the generated square wave voltage, as shown in Fig.6. A correction value for the zero crossings can be calculated from this non-uniformity:

K = C/4 - B/2 ..+ A/4.

If A-B = B-C, then this correction value becomes zero. This correction value K must be subtracted from the times A and C

Then you get corrected times A* and B* for the zero crossings. With these corrections there would no longer be any phase shift in the example given above.
20

With the times for the zero crossings corrected in this way, the phase angle ρ between the two alternating voltages can then be calculated. It is:

&rgr; = 2 ( A _L1 - A _Lx ) 360° / [( C _L1 - A _L1 ) + ( C _Lx - A _Lx )].

The phase angle is the difference between the times of the first zero crossings of the two voltages, divided by the average of the period lengths. This ratio is multiplied by 360°.

If the phase angle calculated in this way is less than 45°, "Phase equal" is displayed. Otherwise, "Phase unequal" is displayed. During the self-test, i.e. when the self-test flag (312 of Fig.15) is set,

the result of this test is not shown by the display 76 (Fig.2).

To measure the external alternating voltages to be tested, the relevant zero crossings for both alternating voltages are first determined based on a case distinction. This case distinction is shown in the table in Fig.20:

The first column of the table shows the different types of signals. Sp-Ll is a binary signal from which the presence or absence of the alternating voltage L^ is determined according to Fig.7. This is the output of a comparator which compares the time, e.g. t^, with a reference value. Sp-Lx is the corresponding signal for the alternating voltage L _x . Ph-Ll is the signal of the zero point switch 36 at the input 40 of the computer 42. Ph-Lx is the signal of the zero point switch 50 at the input 54 of the computer 42.

The second column of the table indicates changes in these different signals, eg from "logical 0" to "logical 1" (0-1). The third column indicates under which conditions the changes take place, eg whether the measurement is running at the time of the signal change or not. The fourth column indicates the action resulting from the signal change and the "condition", eg "start measurement L _x , save time Al _x ".

If the signals Sp-Ll and Sp-Lx change from 0 to 1 according to lines 1 and 4 of the table, this means that the voltages L^ and L _x are present. Then the measurement of L^ or L _x can take place. On the other hand, if the signals Sp-Ll and Sp-Lx change from 1 to 0 according to lines 2, 3 or 5, 6, then the actions to be derived from this depend on the "conditions". If the measurement is not yet running, the measurement of the relevant

37 *·

Alternating voltage is "forbidden", i.e. not initiated at all. Measuring an alternating voltage that is not present cannot produce any meaningful results. If the transition from 1 to 0 occurs while the measurement is running, the measurement must be aborted completely according to lines 3 and 6 of the table. Then, as stated in the last line of the table, an error has occurred.

A large number of cases have to be distinguished for the change of the signals for the phase measurement. 10

If the signal Ph-Ll changes from 0 to 1 and the measurement is not yet running, the measurement is permitted according to line 1 of the table and the measurements of both L^ and L _x are not yet finished, then we are at point A^ of the alternating voltage L^, i.e. at the first zero crossing. The resulting action is to start the measurement of the phase of the alternating voltage L^ and to store the time A^ in the corresponding memory location. The same applies analogously to the alternating voltage L _x according to line 10 of the table in Fig.20.

If the signal Ph-Ll changes from 1 to 0 while the measurement is running, this indicates a zero crossing of the alternating voltage from positive to negative. This is the time Bli . This time B ₃ ^ is stored in the corresponding memory location. The same applies analogously to the signal Ph-Lx according to line 11 of the table.

Finally, when the signal Ph-Ll changes from 0 to 1 (line 9) while the measurement is running, the third zero crossing Clj_ of the alternating voltage L^ has been reached. This time is then stored as C-^i in the corresponding memory location. The measurement of L^ is finished. This is signaled by a corresponding flag. The same applies

38 ···

analogously for the signal Ph-Lx. This is indicated in line 12. The situations dealt with in lines 9 and 12 differ from the situations dealt with in lines 7 and 10 in that in the former case the measurement is not yet running, but in the latter case the transition takes place while the measurement is running.

The last two lines deal with cases where the signals Ph-Ll and Ph-Lx change from 0 to 1 while the measurement of the other alternating voltage L _x or Li is finished and the measurement of the associated alternating voltage is not running. In these cases, an error is signaled.

The data thus stored are processed in the manner described above to produce a display. When measuring the external alternating voltages, the results of the measurement are displayed by the LEDs 196 to 208, in contrast to the results obtained during the self-test.

The processing of the data when measuring the external voltage is necessarily carried out using the same means and programs that are used to process the internally generated alternating voltages. The internally generated alternating voltages are still generated and processed according to the above relationships. If data for the external alternating voltages to be tested are available, the program is interrupted. The test program is interrupted and the calculations are carried out using data A, B and C of the external alternating voltages. The test program then continues at the same point. If the measurement of the external alternating voltages is finished and no measurement errors have been detected, the generation and measurement of the internal alternating voltages is aborted.

This is shown in Fig.21. Fig.21 essentially corresponds to Fig.18, which has already been discussed. Comparable elements of the flow chart are provided with the same reference symbols as there. However, following the "time=0" test (rhombus 404), a "measurement completed" test is carried out. This is shown by a rhombus 454 in Fig.21. If the answer is "no", the flow chart is returned to the start of the program by a loop 456 like loop 436 in Fig.18. If the answer is "yes", a check is carried out to see whether there are any measurement errors. This is shown by a rhombus 458. If there are any measurement errors (yes), an error is registered. This is shown by a rectangle 460. If no measurement error is found (no), the measurement is evaluated. This is shown in Fig.21 by a rectangle 462.

Claims (20)

Protection claims 1. Phase comparator for measuring phase angles between two alternating voltages, characterized by (a) means (60) for generating a timing clock, (b) zero point switch (36, 50) for determining at least three zero crossings (A, B, C) of the alternating voltages with respect to this timing cycle, and (c) means for determining the phase positions of the alternating voltage in relation to the timing from the respective zero crossings and (d) means for determining the difference between the phase positions thus determined. 2. Phase comparator according to claim 1, characterized by means for determining and mathematically taking into account a zero line offset of the alternating voltages from unequal time intervals of the zero crossings. 3. Phase comparator according to claim 2, characterized in that (a) the times of the two zero crossings A and C, which mark the beginning and the end of an alternating voltage period and each pass through the zero line in the same direction, are each adjusted by a correction value K = C/4 - B/2 +A/4 be corrected, where B is the time of the mean zero crossing between A and C and 5 (b) the phase difference ρ of the two alternating voltages according to the relationship &rgr; = 2 ( A _L1 - A _Lx ) 360° / [(Cli - A _L1 ) + (C _Lx - A _Lx )]. is determined. 4. Phase comparator according to one of claims 1 to 3, characterized by (a) one threshold switch (38,52) for each of the two alternating voltages, to which the alternating voltage is connected, (b) means for determining the time interval (t3, t4) during which the threshold value (164) is exceeded by the respective alternating voltage (160, 162), and (c) means for indicating whether the time interval is less than a predetermined limit as an indication of the presence or absence of the alternating voltage. 5. Phase comparator according to one of claims 1 to 4, characterized by means for checking the frequency equality of the two alternating voltages before determining the difference between the phases. 6. Phase comparator according to claims 1 to 5, characterized in that the means for checking the frequency equality, the means for determining the Phase positions and the difference between the phase positions, the means for determining the zero line offset and the time interval determining and evaluating means are formed by a microprocessor (42) programmed for this purpose. 7. Phase comparator according to one of claims 1 to 6, characterized in that the alternating voltages (L,L _X ) can be tapped at capacitive voltage dividers (18,20;116,118) which can be applied to the phases of medium-voltage systems. 8. Phase comparator according to claim 1, characterized in that binary display elements (196,198,200,202,204,206,208) are provided for displaying the phase comparison, which can be controlled to display the phase equality when the difference between the phases falls below a predetermined limit value and to display the phase inequality when the difference between the phases exceeds the limit value. 9. Phase comparator according to one of claims 1 to 8, characterized by self-testing means for testing the functionality of the phase comparator. 10. Phase comparator according to claim 9, characterized in that the self-testing means are microprocessor-controlled. 11. Phase comparator according to claim 9 or 10, characterized in that the self-testing means contain means (80) for checking the battery voltage of a battery feeding the phase comparator. 12. Phase comparator according to claim 11, characterized in that (a) the means for controlling the battery voltage include a comparator to which a stabilized reference voltage derived from the supply voltage is applied on the one hand and a partial voltage of the battery voltage tapped from a voltage divider on the other hand, and (b) the emitter-collector path of a transistor is connected in series with the voltage divider, the base of which is supplied with a voltage derived from the supply voltage, which turns the transistor on when the supply voltage is present. 13. Phase comparator according to claim 9 or 10, characterized in that the self-testing means comprises means (86) for testing display components (196,198,200,202,204,206,208) by means of which results of the phase comparator can be displayed. 14. Phase comparator according to claim 13, characterized in that the display components are light-emitting diodes (196» . 198,200,202,204, 206,208). 15. Phase comparator according to claim 14, characterized in that the means for testing the light-emitting diodes (196,198,200,202,204,206,208) are formed by a window comparator (86) to which the burning voltages of the individual light-emitting diodes (196,198,200,202,204,206,208) can be switched one after the other and which signals whether this burning voltage lies within predetermined voltage windows. 16. Phase comparator according to claim 15, characterized in that (a) the window comparator (86) has a first and a second comparator (242,244) each having an "upper" and a "lower" input, each of the comparators (242,244) providing a "logic 1" output when the voltage applied to the "upper" input is greater than the voltage applied to the lower input, (b) at the "upper" input of one comparator (242) one at a voltage divider (246,248,250) tapped upper reference voltage is applied and a lower reference voltage tapped at the voltage divider (246,248,250) is applied to the "lower" input of the other comparator (244),
15 (c) the burning voltage of one of the light-emitting diodes (196,198,200, 202,204,206,208) can be applied to the "lower" input of the first comparator (242) and to the "upper" input of the second comparator (244) via an electronic switch (226,228,230,232, 234,236) controlled by the computer (42) and (d) the outputs of the two comparators (242,244) are linked via an AND gate (256). 17. Phase comparator according to claim 16, characterized in that (a) some of the light-emitting diodes (196,200,204) have different colors from the other part and show lower burning voltages, (b) the control voltages of the associated electronic switches (224,228,232) are connected to the inputs of an OR gate, (c) the output of the OR gate controls another switch (262) and (d) a resistor (264) is connected in parallel to a part of the voltage divider (246,248,250) via the further switch. 18. Phase comparator according to claim 9 or 10, characterized in that the self-testing means contain means for self-testing the phase measurement. 19. Phase comparator according to claim 14, characterized in that the means for self-testing the phase measurement contain: Means (94,96;98,100;102,104) for internally generating a pair of alternating voltages phase-shifted by a predetermined phase angle, - means (106,108) for applying these alternating voltages to the phase comparator and - Means for comparing the measured phase angle with the said predetermined phase angle. 25 20. Phase comparator according to claim 19, characterized in that (a) the means for internally generating the alternating voltages comprise a program (Fig.18, Fig.19) stored in the computer (42), by means of which - a table of values of the signal curve of the alternating voltages to be generated internally, stored in a memory of the computer (42), is read out step by step by "pointers" in time with a timer, and - the values of the value table are converted into output pulses with a pulse width corresponding to the respective value and (b) the output pulses are smoothed by filters (268,272;270,274) to produce a continuous signal waveform.