DE8526950U1 - Gate array with single layer metal wiring - Google Patents

Description

Siemens Aktiengesellschaft Our reference Berlin and Munich VPA 85 P 1 6 6 O DE

Gate array with single-wire metal wiring 5

The invention relates to a gate array according to the preamble of claim 1.

Gate arrays for the implementation of customer-specific integrated circuits are well known. Such gate arrays are also manufactured using CMOS technology, and have transistor pairs each consisting of an η-channel and a p-channel MOS-FET.

It is known (see Electronics/July 3, 1980, pages 119-123) to combine four such transistor pairs in a so-called basic cell, whereby the basic cell has a p- and an n-diffusion region. Conductive bridges made of polysilicon are arranged between the basic cells. To supply power to the transistors, metal tracks are applied to the gate array, each of which extends over a row of basic cells. The drain electrode, source electrode and gate electrode of the MOS-FETs can be connected to one another, to the polysilicon bridges and to the metal pads, whereby each transistor pair is assigned a common gate electrode. When producing the customer-specific gate arrangement on the gate array, it often happens (see page 121 of the above-mentioned publication) that individual transistor pairs of the basic cells are not used.

Unused transistor pairs result in unused areas on the gate array and prevent high packing-35

Krö 1 Ktz / 18.09.1985

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density of the different functional blocks.
Function block is a gate arrangement through which, for example, a shift register,
a flip-flop or something similar is implemented.

The invention is based on the object of providing a gate array
with single-layer metal wiring, which has a
high packing density of the functional blocks.

This object is achieved according to the invention by the features specified in patent claim 1.

In the gate array according to the invention, the functional I

blocks, such as shift registers and delay I

sion Flip-Flo(_s, due to the larger number of Tran- )

sistor pairs and transistor pairs with separate gate 1

Electrodes in the base cells, densely packed. This means '.

the functional blocks are advantageously lower |

ohmic and low-capacitance. Another advantage 1

part is that due to the compact functional |

block the length of the signal paths is short, and thereby |

fast synchronous circuits can be realized. 1

With an increase in the number of transistor pairs in |

the basic cells is not necessarily an increase in the *

Packing density of the different functional blocks I

on the gate array. The individual gate |

Orders require to be implemented on the gate array |

different numbers of transistor pairs. The |

However, transistor pairs of a basic cell cannot be |

different gate arrangements, since

the transistor pairs of a basic cell influence each other

This would therefore cause disturbances between different _;

different gate arrangements. A split |

a basic cell into one or more transistor pair blocks 1

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is not possible because each transistor pair is assigned a common gate electrode, which means that the p-channel transistor and the η-channel transistor of a transistor pair cannot be blocked at the same time.

For this reason, the basic cell according to the invention has, in addition to the larger number of transistor pairs, also transistor pairs which each have their own gate electrode for the p-channel transistor and the η-channel transistor.

Particularly advantageous embodiments of the gate array according to the invention are specified in the subclaims.

The invention is explained in more detail below using an embodiment shown in the drawing.

Fig. 1 a basic cell according to the invention with six transistor pairs and

Fig. 2 shows another base cell according to the invention with eight transistor pairs.

Figures 1 and 2 show basic cells that contain six (see Figure 1) or eight (see Figure 2) transistor pairs TPl to TP6 or TPl to TP8. The p-channel transistors of the transistor pairs TPl to TP8 are arranged in a p-diffusion region PD, and the η-channel transistors in an n-diffusion region ND.

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The basic cells contain transistor pairs whose associated η-channel or p-channel transistors have separate gate electrodes. These are the third and fourth transistor pairs TP3, TPA in the divided basic cell shown in Fig. 1, as well as the third and sixth transistor pairs TP3, TP6 in the basic cell shown in Fig. 2.

The third and fourth transistor pairs TP3, TP4 in the basic cell shown in Fig. 1, as well as the third and sixth transistor pairs TF3, TPo in the basic cell shown in Fig. 2, can be used to form two (see Fig. 1) or three (see Fig. 2) transistor pair blocks in the basic cells. This is done in a known manner by connecting the gate of the p-channel transistor to a positive power supply line and the n-channel transistor to a power supply line having the reference potential.

It has been found that using six or eight transistor pairs in the basic cell allows particularly high packing densities of functional blocks on the gate array to be achieved.

3 claims
2 figures

Claims (3)

·· · · ■■ ■■ ·· ·· · ■ Il I ll &bull; · ··■ I III I I I _ 5 - VPA 85 P 1 6 6 O DE e Objections 1. Gate array with basic cells, each basic cell having up to four transistor pairs, characterized in that the basic cell has more than four transistor pairs (TP1 to TP8), and that the basic cell has transistor pairs (TP3, TP4 or TP3, TP6), whose associated p-channel and n-channel transistors each have their own gate electrode. 2. Gate array according to claim 1,
characterized in that the basic cell has six transistor pairs (TP1 to TP6), the middle two transistor pairs (TP3, TP4) each having separate gate electrodes. 3. Gate array ns. ;h claim 1, characterized in that the basic cell has eight transistor pairs (TP1 to TP8), wherein the third and sixth transistor pairs (TP3, TP6) each have separate gate electrodes.