DE69928445T2 - DIGITAL PERFORMANCE CONTROL - Google Patents

Abstract

A power controller for fluorescent lamp dimming is disclosed, using all digital internal and external programmable controls. A specific ASIC is described. A gate array and microcomputer share parallel functions with fast sub-functions carried out by the gate array and slower sub-functions carried out by a micro-processor. Circuits are provided for automatic shut down when a high frequency ground fault is detected; for connecting the filaments of gas discharge lamps in a series/parallel circuit; for driving the load as close to resonance as possible but in an inductive mode; and for developing a dead time between high side and low side switches which is related to transformer current, switch current, bridge voltage or bridge voltage dv/dt.

Description

AREA OF INVENTION

These The invention relates to power control units and more particularly to a power control unit, which is a digital implementation with such independent ones Features such as automatic shutdown, deadtime control, control near the inductive side and filament connections used.

Out the abstract of Japanese Patent Application JP 10-303674 A is known a circuit which blocks a leakage current and the capacity a filter for an AC power supply line improved. The circuit exists from a choke coil with three coils and a high pass filter for Extract noise. The power supply to the third coil the choke coil is controlled in response to the amplified noise output.

BACKGROUND THE INVENTION

Power Controllers are well known and usually use analog techniques. Digital techniques are used where continuous control is desired e.g. in controlling the darkening of gas discharge lamps such as about fluorescent lamps in an electronic ballast, usually avoided.

The The present invention provides a new digital implementation for power control circuits in particular for controlling the darkening of fluorescent lamps.

Some restrictions analog power control systems are:

I. inflexible control algorithm

The optimal control of circuit breakers (MOSFETs, a bipolar device, Transistors, thyristors, IGBTs and the like) requires complicated Algorithms based on nonlinear multistep functions and variables Functions are based, with a variety of predetermined parameters as the physical parameter range of the circuit arrangement can be selected.

• a) ein kompliziertes Arbeitsregime für Leuchtstofflampen benötigt wird, das die Vorheizstartoperation einschließt.
• b) nichtlineare oder spezielle Betriebsanforderungen für die Leuchtstofflampe entsprechend ihrer V/I-Arbeitskurve und in Abhängigkeit von der Abdunklungsentscheidungstabelle vorliegen, um bei allen Lichtstärken den besten Betrieb zu liefern.
• c) Flexibilität erforderlich ist, um die Verwendung verschiedener Lampenkonfigurationen (Typen und Anzahlen von Lampen) und verschiedener Hauptspannungen zu ermöglichen.

For example, in the case of a phosphor ballast power control unit, flexible algorithms are desired to deliver special loads when:

• a) a complicated operating regime for fluorescent lamps is needed that includes the preheat start operation.
• b) non-linear or special operating requirements for the fluorescent lamp according to its V / I working curve and depending on the dimming decision table, to provide the best operation at all luminous intensities.
• c) flexibility is required to allow the use of different lamp configurations (types and numbers of lamps) and different main voltages.

II. The number of electronic circuits increases as the number of control functions increases. If a silicon implementation possible is, it requires a high silicon addition cost.

III, No decision tables

A analogue solution does not provide "IF-THEN" decisions. It provides only by using analog comparators and only linearly given algorithms "YES NO" decisions ready. For example: Voltage Controlled Oscillator (VCO) for Frequency Modulation (FM) or for the pulse width modulation (PWM) zero to maximum, pulse control etc.

IV. No parameter setting tables

This has in the case of a fluorescent lamp ballast with different lamp configurations, but also with many other choices made by the control unit to be taken in any state of their operation, to do. A specific one Example is the time behavior of the lamp current loop, which at high strength or at low strength as well as during of the transitional operation or in stationary Operation is different.

SUMMARY THE PRESENT INVENTION

• I. Programmierbare vorgegebene feste interne Parameter können durch den Konstrukteur mittels einfacher MMI und adaptiver Regelschleifen auf das gewünschte Betriebsregime und auf die Leistungsschaltung programmiert werden, während die Leistungsschaltung vor Beschädigung geschützt wird, falls sie unter "unzulässigen" Einstellungen läuft. Diese Technik ermöglicht anstelle der in digitalen Signalverarbeitungsvorrichtungen (DSP-Vorrichtungen) üblichen ermüdenden und kostspieligen Prozedur, die die Programmierung dedizierter Software und die Anpassung der Steuerung an die Leistung in beiden Richtungen erfordert, eine sofortige Anpassung der Steuerung an die Leistungsschaltung.
• Die obigen vorgegebenen festen internen Parameter beziehen sich auf eine Menge von Zahlen und Tabellen, die bestimmt sind für:
• – Grenzwerte, Konstanten, Parameter und vorzeichenbehaftete Koeffizienten einschließlich in dem Regelschleifenalgorithmus; und
• – Adressierung/Identifizierung; usw.
• Beispiele des obigen sind:
• 1. die Normierung "realer" Signale;
• 2. die Erzeugung der Grenzwerte für den "FALLS-DANN"-Algorithmus.
• 3. die Anpassung an die Konstruktionskonfiguration und an das Arbeitsregime des Vorschaltgeräts.
• II. Es werden programmierbare vorgegebene Parametertabellen der internen Leistungskonfiguration bereitgestellt.
• III. Es wird eine extern programmierbare neue Parametertabelle bereitgestellt, die für eine spezifische Anwendung eingestellt werden kann, die die bereits vorhandenen Tabellen nicht verwenden kann (z.B.: eine EEPROM-Funktion).
• IV. Es können Software-Ersatzmittel für analoge Schaltungen verwendet werden.
• V. Eine anwendungsspezifische integrierte Schaltung (ASIC) behandelt prinzipiell eine unendliche Menge von Funktionen mit einer unbedeutenden Menge Silicium. Somit sind alle möglichen Komponenten/Schaltungen/Algorithmen auf demselben Silicium integriert. Dies schafft eine einfache, preiswerte und verbesserte Lösung mit der gesamten durch Software bereitgestellten Flexibilität. Die Integration sichert hohe Rauschfestigkeit, beseitigt Schnittstellenkomponenten zwischen Schaltungen, nutzt Schaltungselemente gemeinsam und ermöglicht eine drastische Platzverringerung.
• VI. Es wird ein Gate Array bereitgestellt, das die schnellen Algorithmen oder den schnellen Abschnitt von ihnen umfasst, wie:
• 1. Mittelabgriff;
• 2. Strom null, minimaler und maximaler Strom der Leistungsfaktorkorrektur (PFC);
• 3. Erzeugung von Ansteuerimpulsen.
• VII. Ein Mikrocomputer und das Gate Array nutzen Funktionen, die parallel ausgeführt werden, gemeinsam.
• VIII. Anstelle der Verwendung des in DSPs verwendeten Superskalarprozes sors verarbeitet ein sehr einfacher Mikroprozessor alle Aufträge durch Zeitscheibenbetrieb.
• IX. Ein Gate Array führt alle seine Zuweisungen parallel aus. Funktional arbeiten die Zuweisungen parallel, wobei sie für jede einzelne getrennte Gate-Array-Abschnitte oder -Blöcke benötigen.
• X. Der Mikroprozessor managt unter anderem den Gate-Array-Betrieb.
• XI. Das Gate Array empfängt eine Eingabe von Überwachungsnetzen und bearbeitet die Zwischenalgorithmusschutze. Im Fall der Leuchtstofflampenabdunklung wird der Auftrag unter Verwendung aller ASIC-Hauptelemente A/D, Mikroprozessor und Gate Array ausgeführt. In der beschriebenen Ausführungsform führt das Gate Array außerdem Überwachungsfunktionen aus.
• XII. Der Mikroprozessor überwacht Schutze, die betrieben werden, und sorgt für Langzeitaktionen.
• XIII. Im Allgemeinen werden die durch schnelle und langsame Unterfunktionen konstruierten Funktionen wie folgt behandelt: Der in dem Gate Array implementierte Algorithmus führt die schnellen Unterfunktionen aus, die schnelle Impulse oder Aktionen enthalten. Diejenigen Unterfunktionen, die eine Verarbeitung oder Aktionen erfordern, die während einer langsameren Betriebsart ausgeführt werden können, werden durch den Mikroprozessor ausgeführt. Die neue Struktur und der neue Prozess der Erfindung schaffen ein programmierbares integriertes digitales Steuermodul, das für ein Abdunklungs-Leuchtstoffeinrichtungs-Vorschaltgerät verwendet werden kann. Die Merkmale des Steuermoduls sind:
• a) Es kombiniert die ASIC des abdunkelbaren elektronischen Vorschaltgeräts (DEB) mit integrierter digitaler Steuerung auf einem programmierbaren Leiterplattenprodukt für neue Konstruktionen und für eine neue Bewertung des Beleuchtungsvorschaltgeräts, die für die Produktion mit niedrigem bis mittlerem Umfang geeignet sind.
• b) Eine große Anzahl "auf der Leiterplatte" programmierbarer Parameter, z.B. 14, definieren Vorheizen, absolute Lichtstärke und Abdunklungsbereich.
• c) Ein EEPROM ermöglicht, dass die oben beschriebenen Steuerparameter für mehrere Lampen, verschiedene Betriebsregimes und verschiedene Anwendungen eine einzige Hardware-Plattform verwenden.
• d) Integrierte vordefinierte Softwarestandardparameter für eine 2-Lampen-32 W/36 W-Lampenansteuerung für 120/230 V Wechselstromzuleitung/Netz.
• e) Enthält alle Abdunklungsvorschaltgerätsteuerungen einschließlich Leistungswandlung in einer einzigen digitalen ASIC mit Mehrbetriebsartregelung und impulsweisem Brückenschutz.
• f) Eine Boost-Steuerung, die Leistungsfaktoren korrigiert, mit modifizierter kritischer Betriebsart erreicht bei allen Lichtstärken den niedrigsten Gesamtoberschwingungsgehalt (THD).
• g) Eine Reihenresonanzlampen-Wechselrichtersteuerung erreicht weniger als 1% Stromstärkesteuerung, wie es für Architektur-Abdunklungs-Leuchtstoffeinrichtungs-Vorschaltgeräte erforderlich ist.
• h) Die Modulflexibilität beschleunigt die Produktneukonstruktion und Einsatzerprobung, was eine kundenangepasste ASIC-Softwarespezifikation, die für Vorschaltgerätprodukte in großen Mengen geeignet ist, vorwärts bringt.

The present invention provides a number of new improvements that can be integrated into a simple system or, in some cases, used individually in a stand-alone circuit. These improvements are:

• I. Programmable default fixed internal parameters may be programmed by the designer to the desired operating regime and power circuit using simple MMI and adaptive control loops, while protecting the power circuitry from damage if it is operating under "improper" settings. This technique allows instantaneous adaptation of the controller to the power circuit instead of the tedious and expensive procedure that is common in digital signal processing (DSP) devices, which requires the programming of dedicated software and the adjustment of control to power in both directions.
• The above given fixed internal parameters refer to a set of numbers and tables intended for:
• Limit values, constants, parameters and signed coefficients, including in the closed-loop algorithm; and
• - addressing / identification; etc.
• Examples of the above are:
• 1. the normalization of "real"signals;
• 2. the generation of the limit values for the "if-then" algorithm.
• 3. the adaptation to the design configuration and the working regime of the ballast.
• II. Programmable default parameter tables of the internal power configuration are provided.
• III. An externally programmable new parameter table is provided which can be set for a specific application that can not use the already existing tables (eg an EEPROM function).
• IV. Software substitutes for analog circuits may be used.
• V. An application specific integrated circuit (ASIC) basically handles an infinite set of functions with insignificant amounts of silicon. Thus, all possible components / circuits / algorithms are integrated on the same silicon. This provides a simple, inexpensive, and improved solution with all the flexibility provided by software. The integration ensures high noise immunity, eliminates interface components between circuits, sharing circuit elements and dramatically reducing space.
• VI. A gate array is provided that includes the fast algorithms or the fast section of them, such as:
• 1. center tap;
• 2. Current zero, minimum and maximum power factor correction (PFC) current;
• 3. Generation of drive pulses.
• VII. A microcomputer and the gate array share functions that are executed in parallel.
• VIII. Instead of using the superscalar process sors used in DSPs, a very simple microprocessor processes all jobs through time slice operation.
• IX. A gate array executes all its assignments in parallel. Functionally, the assignments work in parallel, requiring separate gate array sections or blocks for each one.
• X. The microprocessor manages, among other things, the gate array operation.
• XI. The gate array receives an input from supervisory networks and handles the inter-algorithm protections. In the case of the fluorescent lamp dimming, the job is performed using all of the main ASIC elements A / D, microprocessor and gate array. In the described embodiment, the gate array also performs monitoring functions.
• XII. The microprocessor monitors protections that are operated and ensures long-term action.
• XIII. In general, the functions constructed by fast and slow subfunctions are treated as follows: The algorithm implemented in the gate array executes the fast subfunctions containing fast pulses or actions. Those sub-functions that require processing or actions that can be performed during a slower mode of operation are executed by the microprocessor. The novel structure and process of the invention provide a programmable integrated digital control module that can be used with a dimming fluorescent lighting ballast. The features of the control module are:
• (a) It combines the dark electronic ballast (DEB) ASIC with integrated digital control on a programmable printed circuit board product for new designs and for a new evaluation of the lighting ballast required for low to medium size production are suitable.
• b) A large number of "on-board" programmable parameters, eg 14, define preheat, absolute light intensity and dimming range.
• c) An EEPROM allows the control parameters described above for multiple lamps, different operating regimes, and different applications to use a single hardware platform.
• d) Built-in pre-defined software standard parameters for a 2-lamp 32W / 36W lamp driver for 120/230V AC power supply / mains.
• e) Includes all dimming control gear controls including power conversion in a single digital ASIC with multi-mode control and pulse-wise bridge protection.
• f) A boost control that corrects power factors, with modified critical mode, achieves the lowest total harmonic content (THD) at all light intensities.
• g) A series resonant lamp inverter control achieves less than 1% amperage control, as required for architectural dimming fixture ballasts.
• h) Modules flexibility accelerates product redesign and field testing, resulting in a customized ASIC software specification suitable for ballast products in large quantities.

• 1. Eine neue Abschaltschaltung, die in Reaktion auf das Erfassen eines Gleichtakt-Hochfrequenzstroms, der einen gegebenen Wert übersteigt, die Leistung zum Vorschaltgerät abschaltet. Insbesondere ist auf die Gleichtaktdrossel eine zusätzliche Spule gewickelt, um einen Hochfrequenz-Erdschlussstrom zu erfassen und in Reaktion darauf die Leistung zu dem Vorschaltgerät abzuschalten.
• 2. Eine neue Schaltung, die zwei oder mehr Glühfäden von zwei oder mehr Gasentladungslampen, insbesondere Leuchtstofflampen, so parallel schaltet, dass die Entfernung irgendeiner Lampe diese Schaltung unterbricht, während sie zulässt, dass die an die Lampe angelegte Spannung zur Abdunklung verringert wird. Insbesondere ist eine Reihen-/Parallelschaltung vorgesehen, die das Erregen der Lampenglühfäden mit einem einweggleichgerichteten Gleichstrom (DC) ermöglicht.
• 3. Eine Steueranordnung für Gleichstrom-Wechselstrom-Wechselrichter zum Ansteuern nichtlinearer Lasten wie etwa elektronischer Vorschaltgeräte für Hochdruck- und Niederdruck-Gasentladungslampen, resonante Stromversorgungen und Laser-Stromversorgungen und dergleichen, in denen das Steuerschema sowohl eine Modulation mit veränderlicher Impulsbreite als auch eine Frequenzmodulation verwendet, wobei die Last so nahe wie möglich bei der Resonanz, jedoch auf der induktiven Seite der Resonanz, angesteuert wird. Sowohl der Schalter der oberen Seite als auch der Schalter der unteren Seite der (Einweg- oder Zweiweg-)Brücke werden in dieser Anordnung unabhängig gesteuert.
• 4. Eine neue Schutzschaltung für einen (Einweg- oder Zweiweg-) Wechselrichter in Brückenschaltung, der eine resonante Last liefert, wie etwa für ein resonantes elektronisches Vorschaltgerät für Gasentladungslampen, die eine Totzeit erzwingt, während der kein Schalter in Leitung angesteuert wird, ohne dass die Leistungsfähigkeit der Schaltung beschränkt wird. Der Punkt, an dem eine dynamische Totzeit beginnt, wird durch Erfassen des Punkts erfasst, an dem der Strom im Fall einer kapazitiv zeitgesteuerten Schaltung auf null zusammenbricht. Die Erfassungsschaltungen können den Induktorstrom unter Verwendung eines Stromtransformators oder eines Nebenschlusswiderstands, durch Erfassen des Stroms über die Schaltvorrichtungen, durch Erfassen der Brückenspannung oder durch Erfassen des dv/dt der Brückenspannung erfassen.

The new system of the invention can incorporate a large number of other features as integral components of the system or as standalone features that could be incorporated into any ballast control circuitry. These include:

• 1. A new shutdown circuit that shuts off power to the ballast in response to detecting a common mode high frequency current exceeding a given value. In particular, an additional coil is wound on the common mode choke to detect high frequency ground fault current and in response turn off the power to the ballast.
• 2. A new circuit which shunts two or more filaments of two or more gas discharge lamps, in particular fluorescent lamps, in such a way that the removal of any lamp interrupts this circuit while allowing the voltage applied to the lamp to be reduced for darkening. In particular, a series / parallel circuit is provided which allows the excitation of the Lampenglühfäden with a half-rectified direct current (DC).
• 3. A control arrangement for DC-AC inverters for driving non-linear loads such as electronic ballasts for high-pressure and low-pressure gas discharge lamps, resonant power supplies and laser power supplies and the like, in which the control scheme uses both a variable pulse width modulation and a frequency modulation with the load being driven as close as possible to the resonance, but on the inductive side of the resonance. Both the upper side switch and the lower side switch of the (one-way or two-way) bridge are independently controlled in this arrangement.
• 4. A new protection circuit for a bridge (one way or two way) inverter which provides a resonant load, such as for a resonant electronic ballast for gas discharge lamps, which enforces a dead time during which no switch in line is driven without the performance of the circuit is limited. The point at which a dynamic dead time begins is detected by detecting the point at which the current collapses to zero in the case of a capacitively timed circuit. The detection circuits may detect the inductor current using a current transformer or a shunt resistor, detecting the current through the switching devices, detecting the bridge voltage, or detecting the dv / dt of the bridge voltage.

According to the present Invention provides an electronic ballast for a gas discharge lamp, wherein the electronic ballast comprises an input AC circuit, a common mode inductor for connecting the input AC circuit with a rectifier in bridge circuit, a switch of the upper side and a switch of the lower one Side inverter circuit connected to the rectifier in bridge circuit is connected, and one the inverter circuit with the gas discharge lamp connecting and this driving resonant circuit has. With the common mode inductor is a monitoring circuit for detecting a high frequency ground fault current applied to a ground connection, which has a frequency higher as the frequency of the input AC circuit is connected. With the monitoring circuit is a control circuit for turning off the inverter circuit or the power supplied to the inverter circuit when the high frequency ground fault current exceeds a certain value, connected.

As a further aspect of the present invention, an electronic ballast for at least two parallel-connected gas discharge lamps, which are removably mounted in a holder ge in which there is an inverter circuit, a resonant circuit and at least two gas discharge lamps. The gas discharge lamps have a first and a second filament. The resonant coupling circuit includes an inductor and a capacitor connected in series with the first and second filaments. With the inductor, a first and a second coil are connected, and a first and a second diode are connected in series with the first and the second coil and with the first and the second diode, whereby the separation of the lamps and Filaments from their brackets opens the output circuit of the inverter circuit.

When Another aspect of the present invention will be an electronic one ballast for a gas discharge lamp created in which there is an input AC circuit. With the input AC circuit An AC filter is connected. With the input AC circuit is a rectifier bridge connected to from the AC circuit input an output DC to create. An inverter circuit comprising a switch of upper side and a lower side switch is included connected in series with a node and across the output of the inverter circuit connected, wherein a load circuit is connected to the node, which contains the gas discharge lamp.

Of the Include upper side switch and lower side switch each MOS gated devices and the like with input control terminals, which are excitable to turn them on and off, each one owns parallel diode. A master control circuit sets appropriate Timed control signals to the switch of the upper side and turn the switch of the lower side alternately on and off. In the master control circuit For example, a dynamic dead time control circuit is provided to intervene the end of the power line either through the MOStorgesteuerte device the upper side or through the MOS gated device of lower side and the like and the beginning of the line through the others by controlling the application of the control signals to theirs Control terminals only a short time interval to ensure. The dynamic dead time control circuit is connected to the current in the Resonance load and / or with the current in the first and in the second Switch and / or with the output voltage of the rectifier bridge and / or with the rate of change dv / dt of the bridge voltages connected and monitored she and puts the application of turn-on signals to the switch the upper side and the switch of the lower side both for capacitive as well as for inductive operations.

When Yet another aspect of the present invention will be Electronic control module for controlling the operation of an electronic ballast for at least created a lamp in which the control module is an integrated circuit owns that in accordance with control information using a combination of pulse width modulation and frequency modulation is operable to a first switch and to control a second switch so that they at least power a lamp. With the integrated circuit There is a first memory connected to a variety of parameter tables stores each parameter table the control information for the integrated Has circuit.

When Yet another aspect of the present invention will become a integrated circuit for controlling the operation of an electronic lamp ballast created in a central logic controller the overall operation of the electronic lamp ballast controls. With the central Logic supervisor is a DC / AC generator module verbun the, the drive signals for one Inverter circuit provides that a first switch and a second switch has. With the central logic supervisor is a powerline communication module connected via a Power line receives dimming control data. With the central logic supervisor is connected to a power factor correction module, the power factor determination and correction for controls the electronic lamp ballast.

When Another aspect of the present invention is a method to control the dimming operation of an electronic ballast, in which a current through a connected to the electronic ballast Load monitored and the current is controlled so as to maintain a darkening level is obtained.

SUMMARY THE DRAWINGS

1 is an electronic ballast circuit of the prior art, which represents a danger in the presence of a high frequency high voltage ground fault.

2 shows a new circuit to create a high-frequency hazard protection, which is an improvement of the circuit 1 is.

3 is a circuit diagram of a lamp ballast with a known series of Lampenglühfäden.

4 shows a circuit diagram of a lamp ballast with a known parallel circuit of Lampenglühfäden.

5 shows an improvement of the circuit of 1 and 4 , which is a new circuit arrangement for a lamp ballast, which uses a new series / parallel connection of filaments.

6 shows a known general half-bridge ballast circuit which is operated in an operation near the resonance.

7 shows the voltages and currents in the circuit 6 on a common time basis for a reactive phase condition.

8th shows the voltages and currents in the circuit 6 for a capacitive phase condition.

9 shows the circuit 6 , which is designed with a new current detection protection circuit.

10 shows the circuit 6 with a new voltage detection protection circuit.

11 shows the circuit 6 with a new dv / dt detection protection circuit.

12 shows the curves 8th using a new mode with continuous reactive load.

13 shows the curves 12 that have been changed by a new use of a predicted minimum dead time.

14 shows a new voltage detection protection circuit ( 10 ) for an electronic ballast.

15 is a block diagram of a preferred ASIC used to control the circuit 14 can be used.

16 is a block diagram of a complete control module incorporating the circuits of the 14 and 15 used.

17 and 17A show the curves for the new independent control of the upper side switch and the lower side switch of a DC / AC bridge inverter.

18 is a block diagram of the silicon topology of the ASIC of 14 and 15 ,

19 shows relevant voltage and current curves generated by the ASIC

18 were generated.

20 is a graph of luminous intensity versus current in which the curve is subdivided into fitted segments of the conventional nonlinear curve.

21 FIG. 13 is a wiring diagram of a remote-controlled dimmable ballast correcting power factors.

21A is a schematic diagram of the in 20 used ASIC.

22 shows the pin assignment of the ASIC for the 20 and 21 ,

23 is a wall control unit block diagram for the circuit diagram 21 ,

24 is another circuit diagram of the ballast control module of the invention.

25 is a circuit diagram of the ballast platform with control module.

DETAILED DESCRIPTION OF THE DRAWINGS

following the various new features are described that are related to each other combined and / or independent could be. These are described below in Sections I to V.

I. The high frequency hazard protection circuit

With reference to the drawings, in which like reference numerals refer to like elements, shows 1 schematically an electronic ballast circuit of the prior art, in which an AC input line via a common mode choke 31 with a rectifier circuit 30 is connected in two-way bridge circuit. As shown, both coils are the common mode choke or the inductor 31 Associated with stray capacitances. The exit of the bridge 30 can with a DC-DC converter circuit 33 which corrects for power factors whose one output is connected to the V _SS bus, while another output is connected to the V _CC bus.

Connected to the V _CC bus is an upper side switching MOSFET (or another MOS controlled device such as an IGBT) Q ₁ , while a lower side switching MOSFET Q _{2 is} connected to the V _SS bus. The MOSFETs Q ₁ and Q ₂ are suitably controlled to alternately turn on and turn off the MOSFETs Q ₁ and Q ₂ with controlled frequency, controlled duty and / or controlled phase delay.

Thereupon the output node is 35 connected with a resonant load, which in 1 from a blocking capacitor 40 , from an inductor 41 , from a parallel capacitor 42 and from a fluorescent lamp 45 with filaments 43 and 44 consists.

The feeder ladder in 1 are about the capacitors 47 and 48 with the earth 46 connected. If due to a ground fault or the like a person 50 is connected between the circuit and ground, there is a danger.

The the danger caused by the low frequency (50/60 Hz) becomes common treated with a residual current sensor (not shown). Indeed could the high-frequency voltage used in electronic ballasts (20-100 kHz voltage) be dangerous, since the voltages (especially during the ignition period) are high and there the gas in the tube like a big one Capacitor behaves.

2 shows the new circuit to avoid the above danger problem. In 2 have those parts that look similar to those 1 are the same reference numerals. To the common mode choke 31 is a new spare spool 60 added. The sink 60 is over a diode 61 with a control unit 62 connected, which is arranged so that it detects a fault condition. If the coil 60 detects a common-mode high-frequency current that is higher than a safe value, sets the control unit 62 to the converter 33 a "shutdown" signal, which turns off the DC / AC power bridge. Details of a typical converter and a typical DC / AC power bridge that could be used with this invention are described below.

II. DC filament supply circuit for safe parallel lamp operation.

A fluorescent lamp has two filaments on its two sides. Thus, the lamp owns 45 in 3 the filaments 43 and 44 , These filaments need to be heated before the lamp 45 can be ignited, and must remain heated if the lamp 45 in a "low light" condition or dimmed condition. There are two main circuits for lamp filaments used in electronic ballasts, a series circuit and a parallel circuit. 3 shows the series connection.

In this configuration, the heating current flows through the through the inductor 41 and the capacitor 42 formed resonant circuit. Before ignition and during a phase, the voltage at the lamp should be low (below the ignition voltage). Thus, the operating frequency should be significantly higher than the resonance. At this frequency, the current through the inductor 41 determined and could be too low to get a sufficient To produce filament heating. During and after ignition, the current through the filament is sufficient.

4 shows a parallel circuit of the prior art of the filaments 43 and 44 , In this configuration, the inductor has 41 auxiliary coils 70 and 71 that are used to the filaments 43 and 44 to supply a heating voltage (rather than a series current). This circuit provides sufficient current over the full lamp mode, but has a significant drawback. That is, when a lamp is removed from its housing, flows through the resonant circuit 41 and 42 a current that could damage the ballast especially if it is used to drive two parallel lamps.

In accordance with the invention, as well as in 5 is shown, created a new series / parallel circuit. Thus, the coils 70 and 71 out 4 reconnected as shown, passing over the diodes 75 and 76 with the filaments 44 respectively. 43 are connected.

This Access applies a parallel heater to the filaments and connects the lamp in such a way that pulling out of the housing opens the lamp circuit.

The result is a series-parallel combination where the parallel segment is the lamp 45 with a half-wave rectified DC waveform. The diodes 75 and 76 are connected in such a way that whenever the lamp 45 is pulled out, the current flow is blocked.

The connection of a second lamp 45 is in 5 shown in dashed lines. According to this arrangement, removing one of the lamps further enables the remaining lamp (or the remaining lamps when more than two lamps are driven) to operate. The removal of all lamps blocks the current flow.

III, protection circuits for the Bridge inverter.

6 shows a "generic" half-bridge circuit for driving any desired resonant load, such as an electronic ballast. The half-bridge consists of the MOS-gated devices and the like of the upper side and the lower side such as the MOSFETs Q ₁ and Q _2, respectively. The MOSFETs Q ₁ and Q ₂ are conventional with parallel body diodes 80 respectively. 81 shown, with the load 82 may be any desired resonance load, such as a gas discharge lamp. Basically, the circuit is off 6 a resonant topology, where the regime of operation is close to resonance, ie close to the resonant frequency of the inductor 41 and the capacitor 42 , lies. The invention to be described is suitable for any application in which a reactive current could flow across the bridge Q ₁ , Q ₂ . It should be noted that all that is described below is a full-bridge topology as well as the ones described in U.S. Patent Nos. 4,648,866 6 shown half-bridge concerns.

7 shows on a common time axis relevant voltages and currents in the circuit 6 when the excitation frequency of the MOSFETs Q ₁ and Q _{2 is} above the resonant frequency of the inductor 41 , the capacitor 42 and the load 82 lies. Under this condition, the load is reactive. In 7 is the line 100 the HO signal to Q ₁ and the line 101 the LO signal to Q ₂ . The bridge voltage at the node 35 is through the line 102 shown while the bridge current through the line 103 is shown.

At the end of each excitation cycle in 7 the stream rushes 103 over the inductor 41 the excitation voltage 102 to. When the upper switch Q _{1 is} closed, a current flows into the inductor 41 , When the upper switch Q _{1 is} opened or turned off, the current must go through the inductor 41 continue to flow, what he does in that he, as in 7 through the line 104 shown is via the integral diode 81 the lower switch flows. When the lower switch Q ₂ closes, the integral diode becomes 81 restored solely by a recombination effect of the charge carriers from the line at zero voltage.

The same method described above relates to the line through the line 105 the lower switch controlled half-cycle.

• 1. Wenn der obere Schalter Q₁ ausgeschaltet wird, wird der induktive Strom zu der integralen Diode 81 des unteren Schalters gelenkt, wobei die Spannung 102 an der Brücke sofort von Vdd auf Vss schwingt.
• 2. Während der untere Schalter Q₂ geschlossen wird, bricht der in die integrale Diode 81 des unteren Schalters gelenkte Strom auf Null zusammen.
• 3. Gleichzeitige Leitung sowohl des oberen als auch des unteren Zweigs Q₁ und Q₂und der Brücke ist nicht möglich.

The following can be observed:

• 1. When the upper switch Q _{1 is} turned off, the inductive current becomes the integral diode 81 the lower switch is controlled, the voltage 102 at the bridge swings immediately from Vdd to Vss.
• 2. While the lower switch Q _{2 is} closed, it breaks into the integral diode 81 the lower switch steered current to zero together.
• 3. Simultaneous conduction of both the upper and the lower branch Q ₁ and Q ₂ and the bridge is not possible.

The diagram 8th shows the behavior of the inverter bridge 6 when the excitation frequency is below resonance (and thus the load is called capacitive). The different lines 8th carry the same reference numerals as those 7 ,

The current through the inductor 41 precedes the excitation voltage in each excitation cycle and reverses its direction before the excitation cycle ends. Thus, at the end of the excitation cycle, the current flows across the integral diode of the circuit breaker Q ₁ or Q ₂ , which is on and ready to close. When the upper switch Q _{1 is} closed, the current continues to flow through its integral diode 80 , When the lower switch Q ₂ closes, the current continues to flow across the upper integral diode 80 ; thus it is restored to full bus DC voltage via a forced restoration process that is rugged. This forced recovery process causes a momentary short circuit condition with a high current spike (the one in the line 105 out 8th is designated) and may lead to device failure.

The same behavior applies to the lower switch 6 ,

• 1. Wenn der obere Schalter Q₁ "aus" angesteuert wird, fließt der Strom über den Induktor 41 wegen der Stromrichtungsumkehr, die auftritt, bevor die Erregung endet, in die integrale Diode 80 des oberen Schalters.
• 2. Die Brücke bleibt bis zum Zusammenbruch des von dem Induktor 41 zu der integralen Diode 81 fließenden Stroms oder bis der untere Schalter Q₂ in die Leitung angesteuert wird auf dem Pegel Vdd.
• 3. Falls der untere Schalter Q₂ in die Leitung angesteuert wird, während die interne Diode 80 des oberen Schalters noch Strom leitet, wird er in eine schroffe Wiederherstellung angesteuert, was die Vorrichtung beschädigen kann.
• 4. Dieselbe Erscheinung kann in der Leitungsperiode des unteren Schalters Q₂ beobachtet werden.

The following can be observed for a capacitive condition:

• 1. When the upper switch Q _{1 is driven} "off", the current flows through the inductor 41 because of the reversal of current direction, which occurs before the excitation ends, into the integral diode 80 of the upper switch.
• 2. The bridge remains until the collapse of the inductor 41 to the integral diode 81 flowing current or until the lower switch Q _{2 is driven} into the line at the level Vdd.
• 3. If the lower switch Q _{2 is driven} into the line while the internal diode 80 If the top switch still conducts current, it will be driven into a rugged recovery, which can damage the device.
• 4. The same phenomenon can be observed in the conduction period of the lower switch Q ₂ .

The problem of simultaneous caused by a rugged recovery Leading becomes common corrected by inserting a deliberate dead time, i.e. a period in the cycle in which none of the switches in the Line is controlled. The dead time should be long enough to a protection for the On the other hand, inserting a huge Dead time the efficiency the bridge deteriorates by limiting the duty cycle. Also limited it's the ability the bridge, near to work on the resonance. Thus, the usual solution is a compromise at the expense limited capacity provides insufficient protection.

• 1. Erfassung des Stroms über den Induktor 41 durch einen Stromtransformator oder durch einen Nebenschlusswiderstand in Reihe damit.
• 2. Erfassung des Stroms über die Schaltvorrichtungen Q₁ und Q₂.
• 3. Erfassung der Brückenspannung.
• 4. Erfassung der Anstiegsrate (dv/dt) der Brückenspannung.

In accordance with the invention, a variable dead time is provided that adapts to the circuit needs. This dead time is called a "dynamic dead time". The dynamic dead time is achieved by detecting the point at which the current collapses to zero in a capacitive case. There are four variants:

• 1. Detecting the current through the inductor 41 by a current transformer or by a shunt resistor in series with it.
• 2. Detecting the current through the switching devices Q ₁ and Q ₂ .
• 3. Detecting the bridge voltage.
• 4. Detection of the slew rate (dv / dt) of the bridge voltage.

9 shows the use of a current detection protection circuit, in which a current transformer 110 is provided for monitoring the bridge current. Also shows 9 the control module 111 which supplies the outputs LO and HO to the MOSFETs Q ₂ and Q ₁ . This current sensing function may also be provided by current transformers (not shown) in series with Q ₁ and Q ₂ or by the shunt resistor 112 in the Vss bus. These current measuring devices are then connected to the comparator 113 in the control module 111 connected. Each through the comparator 113 "Ringing" detected near the end of the power line period may be controlled by a feedback loop, such as a Schmidt trigger, a flip-flop, or a bus holder.

10 shows the circuits of the 6 and 9 that have been changed for a voltage detection protection mode. Thus, in 10 a connection from the node 35 about the resistance 115 to the comparator 111 been prepared.

• 1. Im Fall des "kapazitiven" Betriebs der Brücke (Linie 103 in 8) findet an dem Punkt, an dem der Strom auf null zusammenbricht, eine Inversion der Brückenspannung am Knoten 35 statt.
• 2. Diese Inversion wird mittels eines Spannungskomparators (Linie 102, 8) erfasst. Von der Periode, in der der Schalter geschlossen ist, bis zur Inversion der Brückenspannung wird eine Totzeit eingefügt (Linie 102, 8).
• 3. Irgendein durch den Komparator 113 in der Nähe des Endes der Stromleitungsperiode erfasstes "Läuten" kann durch eine Rückkopplungsvorrichtung wie etwa durch einen Schmidt-Trigger oder durch ein Flipflop oder durch einen Bushalter (nicht gezeigt) gesteuert werden.
• 4. Wenn die Brücke in einer induktiven Zone arbeitet (7), tritt die Inversion der Spannung sofort nach Schließen eines Schalters auf; somit wird keine Totzeit eingefügt.

The following is the operation of the circuit 10 described:

• 1. In the case of "capacitive" operation of the bridge (line 103 in 8th ) finds an inversion of the bridge voltage at the node at the point where the current collapses to zero 35 instead of.
• 2. This inversion is performed by means of a voltage comparator (line 102 . 8th ) detected. From the period in which the switch is closed to the inversion of the bridge voltage, a dead time is inserted (line 102 . 8th ).
• 3. Any by the comparator 113 "Ringing" detected near the end of the power line period may be controlled by a feedback device, such as a Schmidt trigger or a flip-flop, or by a bus holder (not shown).
• 4. If the bridge is operating in an inductive zone ( 7 ), the inversion of the voltage occurs immediately after closing a switch; thus no dead time is inserted.

11 shows a dv / dt detection protection scheme that includes a capacitor 117 that provides from the node 35 to a logic gate 118 in the control module 111 connected is. From the resistance 119 is a control module connection to a node between the diodes 120 and 121 intended.

The circuit off 11 is a change in the voltage detection control 10 , which is suitable for digitally controlled DC / AC bridges. This embodiment uses instead of the comparator 113 which is basically an analog device, a logic gate 118 ,

As the voltage increases, a current flows across the sense capacitor 117 which is clamped to VCC. At a falling voltage, the capacitor 117 clamped to the control circuit. If the voltage of the bridge does not rise or fall, the input signal of the logic gate could be 118 float and is thus kept at an appropriate value by the control logic.

It is possible to use a continuous reactive load protection arrangement in which the DC / AC bridge is off 6 operating in a continuous capacitive regime rather than just providing protection.

If the dead time by the current or voltage commutation automatically is determined, the operation of the bridge tends to be irregular, that is, the bridge could be driven in an asymmetric operation, the current waveform is irregular.

A simple case of such an irregularity is in the waveforms 12 shown the curves out 8th show, but contain the irregularity.

The irregular operation could be corrected using the previous (measured) dead time to predict a minimum dead time for the next cycles and, as in 13 is shown thereafter to detect the current or the voltage.

14 shows a specific circuit diagram of a voltage detection protection system for a fluorescent lamp ballast ( 3 and 10 ) in conjunction with a specific ASIC 130 to provide all control signals.

In 14 becomes the inversion of the bridge voltage at the node 35 through a comparator of internal voltage (in the ASIC 130 ) on the pin CT and used by the internal logic to extend the dead time.

It is noted that in 14 Voltage detection method shown overcomes the delays caused by the bus capacitance in the capacitive detection circuits.

15 Figure 13 is a block diagram of the ASIC, described in more detail later 130 ,

16 shows the complete control module including the circuits of the 14 and 15 ,

IV. The DC AC Inverter Bridge for Nonlinear Loads.

The following is a new process for the operation of the DC AC inverter bridge 6 described a non-linear, resonant and time-varying load, eg electroni control gear for low pressure and high pressure lamps, resonant power supplies, laser power supplies and the like.

Two common control methods are used: PWM control and FM control. Both methods provide only partial solutions to the problems that these power supplies pose. The problem arises when the control circuit attempts to achieve a low intensity target (eg, very low dimming) at a small current. Attempting to achieve a low current using a PWM circuit could drive the DC / AC bridge into the capacitive area and could lead to the destruction of the power switches Q ₁ and Q ₂ . In contrast, attempting to do so by changing the frequency usually results in irregular light output (rings or queues in fluorescent lamps) and instability.

Although this in 16 not shown are the different modules in the ASIC 130 in the ASIC (see 15 ) connected to a central logic supervisor. The central logic supervisor controls the overall operation of the ASIC 130 by enabling communication and passing data between the modules.

According to the control method of the invention, both pulse width modulation and frequency modulation are used and constantly changed to darken the lamp and / or maintain a high quality control regime. The aim is to work as close as possible to the resonance, transitions, lamp aging, noise, use of incompatible lamps, etc. but in the 7 to be shown inductive behavior. The new procedure is combined with a center tap protection solution that prevents "pulse by pulse" from accidentally being detected in the 12 and 13 shown capacitive load is reflected in the bridge of the inverter.

T

– volle Periode der Halbbrücke

T1

– Sperrstromzeit des Schalters der oberen Seite

T2

– Leitungszeit in der "zulässigen Richtung" des Schalters der oberen Seite

T3

– Leitungszeit des Schalters der unteren Seite.

When the new bridge control algorithm is used for dimmable electronic ballasts, it controls the preheat, ignition and dimming control functions. In a particular case, at high light levels, a constant width pulse is used for the lower switch Q _{2 of} the bridge, while a variable width pulse is used for the upper switch Q ₁ . This control scheme is in 17 shown the light intensity as a function of the pulse width tone for the switches Q ₁ and Q _{2 of} the upper side and the lower side in the 6 and 14 to 16 shows. At the present time, the constant pulse width becomes the curve 141 the lower side, but using any of the alternative curves 142 can be used. 17a further explains the in 17 shown behavior of the switch of the upper side. In 17a the names shown are defined as follows:

T

- full period of half bridge

T1

- reverse current time of the switch of the upper side

T2

- Line time in the "permissible direction" of the switch on the upper side

T3

- Line time of the switch on the lower side.

As explained above It is the goal of the half-bridge driving algorithm that Half-bridge load for all operating regimes Inductive, but close to keep the resonance.

The new procedure should the switches according to reverse line (parallel diode line) when the switch voltage is close to zero. For example must the rising edge of the control of the upper side during the Timeframe T1 come.

Of the Algorithm must keep the time period T1 short so that it is close to the Resonance, but never zero or negative, which is the expression of a capacitive load for the half bridge is.

Of the Algorithm secures during all operating regimes control the upper and lower side, the while stationary Conditions get a short solid T1. If the T1 against while transitions are shortened and close to zero, the center tap mechanism brings it to a close safe length or duration back.

In addition, the dead time between upper and lower switch operation is simultaneously controlled. For low light levels, this method is too coarse, with a variable width method also being applied to the operation of the lower switch Q ₂ .

As a general rule, the new method allows the independent control of each of the bridge switches Q ₁ and Q ₂ (or pairs of switches in the case of a full bridge) in a fully protected mode with zero voltage switching.

The stability The control is achieved by the fact that during the various operating regimes the Time constant of the DC / AC bridge control is changed. When the light intensity changed on request a small time constant (fast control) is used, while at inpatient (fixed) light control a larger time constant (slow control) is used. This procedure avoids overshoot or undershooting or light fluctuations.

The control scheme described above carries the ASIC 130 of the 14 . 15 and 16 out. In 18 Figure ₄ is another block diagram of the silicon topology that controls the switches Q ₁ and Q _{2 of} the bridge with center tap protection. 19 shows that through the circuit 18 generated control pulses in a common time base.

• 1. An den Mikroprozessor 160 wird über einen (ebenfalls in der ASIC 130 enthaltenen) A/D-Wandler 161 ein Lampenstrom-Abtastwert geliefert.
• 2. Der Mikroprozessor 160 verarbeitet alle Informationen und stellt einen DATENBUS 162 bereit, der alle verarbeiteten Informationen (PLC, LEIS-TUNGSFAKTORKORREKTUR, GLEICHSTROM/WECHSELSTROM) enthält.
• 3. Die Auswahleinrichtung 163 zwischenspeichert geeignete Daten in dem geeigneten ZWISCHENSPEICHER 164 und 165. Die Rate der erneuten Zwischenspeicherung ist eine Entscheidung oder ein Standard der Software.
• 4. Die Zähler "PWM-LOGIK der oberen Seite" und "PWM-LOGIK der unteren Seite" erzeugen zusammen die Signalform der OBEREN SEITE (19), die als ein Impulszug beschrieben werden kann. Die Impulsbreite ist durch "HS-DATEN" und "LS-DATEN" bestimmt, die die Zeitdauer zwischen Impulsen bestimmen.
• 5. Die HS-Signalform wird in das UND1-Gatter 168 eingespeist. Zu der Signalform wird eine feste Totzeit und außerdem eine (durch die Mittelabgriffseingabe bestimmte) veränderliche Totzeit addiert, woraufhin sie über den HSDV-Ausgang (Ausgang des Treibers der oberen Seite) 169 austritt.
• 6. Die Signalform wird außerdem durch das NICHT3-Gatter 170 invertiert und dem UND2-Gatter 171 zugeführt. Zu der Signalform wird eine feste und eine veränderliche Totzeit addiert, woraufhin sie über den LSD-Ausgang (Ausgang des Treibers der unteren Seite) austritt.
• 7. Die NICHT1- und NICHT2-Gatter 173 bzw. 174 vermeiden die Möglichkeit, dass die 2 Ausgänge HSD bzw. LSD beide gleichzeitig "hoch" sind.
• 8. Beschreibung der Mittelabgriffs-Schutzschaltung: Die Ausgänge des UND1 und des UND2 168 bzw. 171 werden überwacht. Falls es für 16 aufeinander folgende Impulse keine Überlappung mit der ursprünglichen Signalform (wie sie aus der HS-PWM-Logik herauskommt) gibt, erhöht sich der 16-Versuche-Zähler 176 um 1, was 4 aufeinander folgende Zyklen ohne Unterbrechung ermöglicht. Falls sich die gleiche Erscheinung wiederholt, wird der 16-Versuche-Zähler 176 weiter erhöht. Falls die Erscheinung verschwindet, wird der 16-Versuche-Zähler 176 zurückgesetzt.

The following is a description of the operation of the block diagram 18 and the curves 19 ,

• 1. To the microprocessor 160 is via a (also in the ASIC 130 contained) A / D converter 161 a lamp current sample is supplied.
• 2. The microprocessor 160 processes all information and provides a DATA BUS 162 ready, which contains all the processed information (PLC, POWER SCORE CORRECTION, DC / AC).
• 3. The selection device 163 Cache appropriate data in the appropriate INTERMEDIATE MEMORY 164 and 165 , The rate of re-caching is a decision or standard of the software.
• 4. The counters "PWM-LOGIK the upper side" and "PWM-LOGIK the lower side" together generate the signal form of the TOP PAGE ( 19 ), which can be described as a pulse train. The pulse width is determined by "HS DATA" and "LS DATA" which determine the duration between pulses.
• 5. The HS waveform is put into the AND1 gate 168 fed. To the waveform is added a fixed dead time and also a variable dead time (determined by the center tap input), whereupon it passes through the HSDV output (output of the driver of the upper side) 169 exit.
• 6. The waveform is also passed through the NOT3 gate 170 inverted and the AND2 gate 171 fed. To the waveform is added a fixed and a variable dead time, whereupon it exits via the LSD output (output of the driver of the lower side).
• 7. The NOT1 and NOT2 gates 173 respectively. 174 avoid the possibility that the 2 HSD or LSD outputs are both "high" at the same time.
• 8. Description of Center Tap Protection Circuit: The outputs of AND1 and AND2 168 respectively. 171 are monitored. If it is for 16 consecutive pulses do not overlap with the original waveform (as it comes out of the HS-PWM logic), the 16-count counter increases 176 by 1, allowing 4 consecutive cycles without interruption. If the same phenomenon repeats, the 16-trial counter becomes 176 further increased. If the phenomenon disappears, the 16-trial counter becomes 176 reset.

If the 16-trial counter 176 When it reaches 16, it sends an "abnormal" message to the microprocessor 160 and enters an anomalous protective regime.

It It is noted that the above technique applies to both a full bridge also applicable to a half-bridge is.

Around a constant change to achieve the light output becomes more variable in the mechanism Pulse width during the entire lamp dimming load curve a "dithering" technique with variable Depth applied.

Consequently causes the use of a digital controller for the pulse width the upper or lower switch through a simple PWM procedure, that the light flickers. To smooth the steps of lighting control, can a dithering method can be used. Thus, from a mixed Series of pulses made from these two time steps are composed, a PWM of an average level, the between the (defined by an integer) PWM steps.

Just by measuring the lamp current, an accurate light intensity control is achieved. This Ver Drive is implemented by adjusting the nonlinear current-light intensity curve to linear segments. Each segment allows a relationship between the percentage of luminous intensity and the lamp current, which, as in 20 is shown, allows a very accurate light intensity control. This technique avoids the need for a complicated lamp power or lamp current measurement algorithm for each lamp type to characterize the above non-linear behavior. The light control accuracy can be further increased by adding additional linear segments to the adjusted nonlinear current-light intensity curve.

This Method is done using a dedicated parameter table implemented, set or defined by the user can be. The above relationship is a relationship between the light intensity and the current at certain points (the extremes of each segment).

It is instructive now to summarize the principles that are in the in the control method of the DC / AC inverter bridge for outermost non-linear AC load algorithms used. It will, especially for a gas discharge lamp that covers most of its darkening area how a negative impedance behaves an extreme non-linear one Last viewed. These lamps have a transfer function whose reinforcement changes between wide limits, making it difficult is to achieve a fast and steady control. There are two common ways to such a load over an AC bridge to control: Pulse Width Modulation (PWM) and Frequency (FM). Both are effective only within a subset of the load that is controlled becomes.

The described control method uses a PWM whose frequency and dead times are variable. It will be in a half / full bridge topology applied: pulse width of the upper side, pulse width of the lower one Page, with the dead times between them programmed in a way and applied, which is constructed so that during the entire range from no load to full load a stable, steady Control loop is achieved.

The used method proposes before, at all loads nearby the resonance to work, the load but always something above the To keep resonance. This is done first by adding at each point the load regime the best control behavior (minimal gain change) is delivered. The pulse width and the frequency are in one Manipulated manner that achieves a constant control gain (occasionally the PWM is used to increase the load current while the Frequency is used to reduce it, and vice versa). These Manipulations are made according to the V / I characteristics of the load executed.

• 1. Von der Minimallast bis zu der ersten Bruchstelle wird die PWM-Steuerung verwendet: der Impuls der oberen Seite erhöht sich, während sich der Impuls der unteren Seite verringert. Die periodische Gesamtzeit wird bei einer festen Zahl gehalten.
• 2. Von der ersten Bruchstelle bis zur zweiten Bruchstelle wird die untere Seite festgesetzt und der Impuls der oberen Seite PWM-gesteuert. Der Tastgrad wird erhöht und gleichzeitig die Frequenz verringert.
• 3. Von der zweiten Bruchstelle bis zur Maximallast wird die Frequenzsteuerung verwendet, wobei sowohl der Impuls der oberen Seite als auch der Impuls der unteren Seite zunehmen.

The following is an example of an embodiment in a ballast application. The control of darkened discharge lamps over the full darkening area is based on a control area divided into three sections by two breakages:

• 1. From the minimum load to the first break, the PWM control is used: the upper side pulse increases, while the lower side pulse decreases. The periodic total time is kept at a fixed number.
• 2. From the first break to the second break, the lower side is set and the upper side pulse is PWM controlled. The duty cycle is increased while reducing the frequency.
• 3. From the second breaking point to the maximum load, frequency control is used, with both the upper side pulse and the lower side pulse increasing.

This Method generates a control load curve with minimum gain change and minimum predetermined dead time between pulses. This controls a predictable load (e.g., a normal-performance lamp) preferably. To caused by unpredictable behavior of the load losses to prevent the center tap voltage of the bridge is detected, to make sure the circuit is at zero voltage. To be destructive Stream to protect, the pulses are changed dynamically. The dead time is dynamically increased to the zero voltage point. This Feature of the invention allows that a lamp with normal operating behavior at high frequencies works with a very short dead time. It also allows the dead time in the case of transitions too increase, and change it the load behavior, e.g. while the discharge lamps age.

V. A digital implementation a power control circuit.

The following describes various techniques used in the new digital access to power management control units, particularly in a dimmable electronic ballast. 21 shows the powerline communication-controlled (PLC-controlled) dimmable preview switching device with a similar construction as that in 16 . shown The ballast control ASIC 200 is in 20 in the block 200 shown by solid lines. The PLC operation allows the ballast to receive the dimming control information via the same power supply line used to power the ballast. The ASIC 200 is again schematic in 21A shown. The ASIC pin assignments are in 22 shown. The block diagram of the wall control unit (WCU) is also in 23 shown. The in the 20 . 21 and 22 The techniques used are generally described as follows:

I. Adaptation of the dynamic Control behavior based on the energy consumption prediction.

The dynamic behavior of the control loop is "flexible". It uses a different "damping factor" and a different loop reaction time for a number of pre-determined conditions. For example, in the case of the electronic ballast, the following decision table is used:
if the bus DC voltage is within the limits of Vref ± 1%, "no reaction";
if the DC bus is within the limits of ± 3%>Vref> ± 1%, "slow"response;
if the DC bus is within the limits of ± 10%>Vref> ± 3%, "fast"response;
if light intensity is crossed + if it is below 90% of the desired, fast reaction;
if the input voltage step changed more than ± 2%, fast response, etc.

If a big change of the light desired is, will be first the desired luminous intensity while being given to the control unit e.g. from full light to light (transient mode), whereupon the power factor correction mode switched to fast response is to avoid Gleichspannungsbuseinsattlungen. At constant Light (stationary State), the power factor correction control switches to the operating mode slow reaction, which prevents a flickering / flickering of the light.

The Limit values, the damping factors and reaction times are parameters that are predefined in the designer programmable tables are listed.

The Control can be set to handle all types of applications including Engine control, temperature control and many others treated.

II. Programmable Parameter Tables

The tables of parameters are programmed for all possible regimes of the required application. For example, in the case of the electronic ballast, there are about 12 different regimes for the darkenable electronic ballast, including:
Direct-current soft start;
Additional increase;
Lampenvorheizen;
Lamp ignition;
increasing light intensity;
falling light intensity;
Upshifting the light intensity;
Downshift the light intensity;
steady state, "high"load;
steady state, "low"load;
Anomalies - output power shutdown; and
Input voltage switched off or "power failures".

each single regime has its own specific parameter table, which is chosen when entering a new regime.

each Contains parameter table all special parameters for the power factor correction control and for the DC / AC bridge control for each Regime. The designer can program these parameters.

Around in all regimes a stable DC bus and the best To maintain power factor correction, gives a digital Control using programmable lookup tables, for each different Regimes the best "treatment" (i.e., in the case of DC / AC bridge inverter control changes the reaction time according to the lamp regimen operation).

at This access is the digital solution the more efficient the application, the more efficient.

III, Adaptive loop parameters

The static and the dynamic loop response adapt to the Inputs by providing feedback information obtained from a number of digital and / or analog inputs, the according to the right ones Parameter tables, decision tables and treated equations chosen become.

IV. Idle period insertion for change to unsteady mode for Low power loads, with the frequency in desired Limits.

While the As the loads become smaller, the frequency becomes very high, with the "on" pulses being very short have to, to get the line of critical mode. Under one The critical operating mode becomes unusable for certain loads. At this Point, the controller goes to the "unsteady" mode, where they ceases to control the "ON" time and the "OFF" time of the pulse begins to control. The "ON time" is set to a desired "minimum usable Pulse "(programmable Parameter). The "off-time" can be between none and "maximum Change the dead time of the unsteady operating mode "(programmable parameter).

V. A method of controlling of the converter under load-free conditions by means of implementation a special "standby" PWM regime mode Use of a dedicated programmable parameter table.

Under Using a digital programmed controller can be special Operating modes are "tailored". All parameters including "pulse width", time between the Pulses, bundle parameters and other parameters for one assigned to a specific task.

One Example of this ability is this here for the electronic ballast used "standby" mode.

This mode is functional at all times when the ballast output stage is disabled and the power factor correction stage must continue to operate in standby mode. In this operating mode, the power factor correction stage has two tasks: first - the additional voltages 5 V and 12V for the control, and secondly - to keep the bus DC voltage within limits.

If the PF correction stage has a very small load is charging the DC bus capacitor quickly reaches a nominal limit, whereby it blocks power factor correction control pulses. To enable that the power factor correction stage supplies additional voltages, special parameters are used: the minimum pulse width and the fixed dead time between pulses. Another mode is the change from the control of the DC bus (with the exception of the maximum) to control the additional voltage to 12 V.

VI. Protection procedure by Combination of several parameter levels using programmable Tables.

Also included the parameter tables some limits to some of the protections provide. For example: The control pulses are in the case a DC bus overvoltage (pulse mode) disabled (the pulses are also disabled if the DC bus higher than 110%). In addition, will the pulses are disabled if the input voltage is above one certain predetermined limit. The input undervoltage is also monitored; below a certain limit, the power factor correction control goes to a power shutdown mode (in the present ASIC implementation, overvoltage protection (OVP)).

The Theory and PFC parameters will be like follows:

MinPFCParam

Maximum power factor correction maximum power pulse for maximum load with minimum input effective voltage. Tone = (255 - n) / 12 MHz 100 1.29 x 100 ^-05 s

MaxPFCParam

Minimum usable pulse for power factor correction control. 125 4.17 × 10 ^-07 s

LowDelPrs

Maximum dead time of unsteady operating mode. 0 2.13 x 10 ^-5 s

HighDelPrs

Just in critical mode.

Waiting on receipt of the ZC signal 83 another ns to activate the power factor correction switch. 254 8.33 x 10 ^-8 s

ShutHighDelPrs

Fixed dead time in shutdown mode. 150 8.75 x 10 ^-6 s

DampingFactor

1 / velocity control. Control step = {[(Vref-VDC) / n] + 1} * 83 ns 14

MaxVDC

Power factor correction software shutdown sound pulse will fail if VDC exceeds this reference. 245 439.5 volts

VDCRef

2.19 volts (A / D level) This is the normal VDC reference. 223 400 volts

VdcHys1

Range of steady state. At VDCRef +/- n the power factor correction tone pulse does not change. 2 3.6 volts

VdcHys1

Demand for fast response, fast PWM at VDC ± VdcHys1 or higher. If the error lies between VdcHys and VdcHys1, there is a slow response. PWM = fast 14 25.1 volts

PfcPWMPrs

Slow PWM response factor.
20

PfcPWMIPrs

Fast PWM response factor (0 if no PWM).
0

MinPFCStartUp

Soft start. Width of the power factor correction tone pulse as the bus DC voltage rises from zero to VDC. 253 1.67 · 10 ^-07 s

PFCTimerPRs

"Slow" loop response = 100 ms. Every 10 ms, the counter is incremented by 1.
10

PFCLoopCounterPRs

"Fast" loop response = 1 ms. Every 250 μs the counter is incremented by 1.
4
Acquisition rate of VDC
fixed at 500 μs
Correlation between power factor correction and DC / AC: for step new light, the power factor correction is up to 90% new light "FAST" and then becomes between 90% and 100% new light "SLOW". "90%" is not included as a parameter.

If the light is changed by "UP" or "DOWN", is the power factor correction control always slow".

DCAC parameters:

DcAcHys

Fast / Slow response area when Curr. Ref. Is higher than 75. If Curr. Ref. Is lower than 75, there is only a slow reaction. Under 2 There is no change in the tone pulse. 2 is not included as a parameter. 5 1.96%

SlowDcAcPrs

PWM with slow response of 20 possible combinations of last and next tone (HSD). The pulse can change every 250 μs.
20

FastDcAcPrs

PWM with fast response of 5 combinations. The pulse can change every 250 μs.
5

StartDcAcPrs

Response for increasing DcAc StartUp (PWM) to start the light after ignition.
15

HSD

Sound pulse changes always over all load curve points.

S.SOUND

HSD tone pulse for lamp ignition. 175 6.67 x 10 ^-6 s

StartTonTime

Duration of the HSD tone pulses for the lamp. Ignition = 2 · 250 μs = 500 μs 2 500 μs
very fast increase on StartTon at NOPWM.

AbDelayPrs

After switching off, wait for the switch-off period. 200 2 s

ShutTimerPrs

After switching off, wait for the switch-off period. 200 2 s

EBCurrentRef

Lower current reference for lower power loss in shunt resistance (EB). 51 1 volt

Light Level (6)

Table for IR light decoding = n / 2 "0, 2, 30, 80, 150, 200" "0, 1, 15, 40, 75, 100"%

LightBasePrs (4)

Fixed points on the lamp curve - 15, 40, 65, 100% lamp current must be supplied for each percentage point. "30, 80, 130, 200" "15, 40, 75, 100"%

CurrentBase (4)

Volt 100% light REFERENCE for ALL LIGHT SIGNS 227 2.23

Maximum Light Level

Vorschaltgerätfaktor. 200 100%

Accessories parameters:

MaxLightSensor

If n = 251 to 255, the occupancy switch is closed. 250 2.45 volts

MinStartDC

For the DC control. If the value is below 10 (5%), power cutoff 10 5%

PLC parameters:

NoiseHys1

Digital filter for PLC after the summation phase.
10

Global zone 0

TrxFreg (4)

PLC frequencies. F = 3ee06 / (64 - n) "33, 34, 35, 36" "96.77, 100, 103.44, 107.13" kHz

Das Folgende ist eine Betriebsbeschreibung, die die Einstellungen des Steuermoduls 111 und der ASIC 200 beschreibt:The following is a line assignment and a functional description for the ASICs of the 15 and 21 and for the control module 16 :

The following is a description of the operation of the control module settings 111 and the ASIC 200 describes:

Customer selectable parameters for D.E.B. applications

Of the Customer can control the behavior of the ballast by determining several Vorschaltgerätparameter influence. Software is used to determine the ballast parameters. The following customer parameters describe these parameters.

Customer parameter table

Parameters Table Selection

The control module 111 Contains in his PROM 13 Parameter tables and in its EEPROM a customer parameter table. The parameters of the tables 0-12 can only change the production. The customer can set his own parameters in the EEPROM table 13 programming using a Parameter Development Kit (PDK).

Tables 0-3: Versions for Two T8-32-W (Parallel Configuration) Lamps (120V Power Supply Application). tables 4-12 : Versions for two T8-36-W (Parallel Configuration) lamps (230V power supply application).

of course is Customization of the internal parameter table possible. A desired Parameter table is created by combining the (with the pins S0-S3 connected) micro jumpers (microjumper) S0, S1, S2, S3 for generating a hexadecimal number selected. For one logic "0" is to insert a jumper, while leaving open for a logical "1". The following parameter table selection table defines the selection of the desired Parameter table.

Parameters Table Selection Table

Selected Ballast Configuration Device Options: selected via A / D input CNFG

The control module 111 and the ASIC 200 allow ballast operation in 5 different configurations as follows: PLC DEB The ballast is remotely controlled by the wall control unit with a Powerline Communication (PLC) interface. In the PLC configuration, it can be determined that the ballast belongs to one of 7 different zones or belongs to all zones. The ballast zone determination is selected via the A / D input ZONE (see section PLC DEB below). DC DEB The ballast is controlled by the DC wall control unit via DC lines. (See the following section LOCAL DEB) LOCAL DEB The ballast is controlled by local infrared IR light and occupancy sensors. (See the following section LOCAL DEB) Occupancy DEB The ballast is controlled by the local occupancy sensor. (See the following section Occupancy DEB). EB Non-dimmable electronic ballast. (See section EB)

The Vorschaltgerätkonfigurationstabelle shows the ballast configuration selection via the CNFG pin. To get the required configuration is between the pin CNFG and GND to turn a resistor.

Vorschaltgerätkonfigurationstabelle

PLC D.E.B.

begin

The ballast starts the lamps with the "lowest Light intensity "(in the EEPROM is secured). The light intensity remains in the lowest light intensity, up to the wall control unit via PLC communication a dimming command is sent.

PLC function

The ballast receives a 17-bit string from the wall control unit (WCU) via PLC remote control communication. The bit allocation is as follows:
1 bit start
2-bit control modes
3 bits -7 selected zones
6 bits -64 light intensities
4 bits checksum
1 bit reserve

The Communication rate is 1 bit per line cycle. The PLC communication is synchronized with the supply phase.

Vorschaltgerätzonenidentifizierung

The determination of the ballast zone identity (0-7) is accomplished by providing a voltage in equal equidistant increments between 0 to 2.5 V are implemented at the zone pin. The zone selection table is shown below.

Zone selection table

EEPROM function

If (on the Supply pin) "supply line disappeared " is, the existing light is saved as the "last light" in the EEPROM. When the ballast is turned on will, it returns to this "last Light intensity "back, if" Table 15 "(S0, S1, S2, S3 = "1") is selected, can the EEPROM to a desired Parameter table are programmed. If table 13 is selected, the parameter table is obtained from the EEPROM.

DC D.E.B.

begin

The ballast starts the lamps at the last light level from the EEPROM parameter table and then increases or decreases to the DC controlled light level present in the ZONE pin. This DC voltage is applied by the DC control unit. The light intensity refers to the ZONE pin voltage according to the following formula:
Light intensity = (ZONE pin voltage / 2.23V) · maximum light level The maximum light level is obtained when the ZONE pin voltage 2 . 23V (converted to 227) is.

When the ZONE pin voltage falls below 110 mV, the lamp light goes to 0. The ballast starts when the ZONE pin voltage 140 exceeds mV.

LOCAL D.E.B.

begin

The ballast starts the lamps according to the last one in the EEPROM parameter table secured light intensity.

Local IR function

The IR receiver output is connected to the IR pin.

Of the IR transmitter sends 8 codes: 5 pre-set light commands, Up, down and down command.

Light sensor function

The Ballast light intensity is controlled by a light sensor that connects via the ZONE pin connected is. The ZONE pin is connected to the input via the feedback input Digital number converted and compared with the sensor reference value.

Of the Sensor reference value is during the reset initialization set to the light sensor value (ZONE pin terminal value). in the Case of a constant voltage at the ZONE pin (control (open loop)), the light intensity remains at the last light intensity (no error detected - sensor reference = ZONE pin voltage, with no dimming UP or DOWN command is produced).

The dimming command from the IR transmitter changes the sensor reference and changes the light level through a control mechanism to obtain:
Light sensor = new sensor reference.
Light sensor voltage range is 0.2V to 2.45V.

Assignment function (in the local configuration)

Two inputs serve the assignment function:
The "Occupy OFF" command uses the RCV pin. A logic "1" (open circuit) on pin RCV is detected as "no presence" and turns off the ballast. A logic "0" on the pin RCV is detected as "presence" and starts the ballast to the last light value.

Of the ZONE analog input pin is also referred to as "no presence, Locks "used. If the ZONE pin voltage is> 2.5 V, "no presence" is disabled. The ballast darkens turn off the light to the minimum light intensity.

After this the occupancy sensor has detected presence in the room the ballast too the last light intensity back. Between the detection of "no Presence "(by the control module) and the dimming operation, there is no delay time.

Occupancy D.E.B.

begin

The ballast starts the lamps according to the in the EEPROM parameter table saved last light intensity.

assignment function

The pin RCV serves as a "presence detection" input. When "no presence" is detected on the pin RCV (logical "high" open circuit), the ballast will darken the light to the "dimming light level" defined on the ZONE pin. The dimming light intensity is currently backed up by "no presence detected" according to the following formula:
Dimming intensity = [maximum intensity] · [ZONE voltage at initialization time] 2.23 V.

After this the occupancy sensor has detected a presence in the room (logic "0" on the ZONE pin), that will return ballast to the maximum light intensity back.

Annotation: Between the detection of "no Presence "(by the control module) and the dimming operation, there is no delay time.

EB

begin

The ballast starts the lamps on "maximum Light intensity ".

E. B. function

The ballast works only with the maximum light intensity. Darkening is not possible. As in all other configurations is regulated by the ILAMP feedback input pin of Lamp current stabilized. The voltage of the ILAMP pin in the situation of maximum light intensity is 0.5 V.

Organizational / protection circuits

The ballast protection features four control module pins 111 and the ASIC 200 used.

The CL input is used for the current limit protection of the power factor correction switch. When the CL input signal exceeds 2.5V, the PFCD output pin (power factor correction drive pulse signal) in pulses.

Of the VDC A / D input pin is used for closing the DC bus loop (Power factor correction output loop) and also as a hardware surge protection detection input used. (Input to the analog comparator). When the tension VDC pin exceeds 2.5V, the PFCD output is disabled in pulses. In addition, the VDC input for the Software Surge Protection used. Alternatively, the PFCD output (by software) is pulsed disabled when the VDC pin voltage exceeds 2.4V.

Of the CT input is used to bridge the half-bridge on a zero-volt switching operation (ZVS operation). If the load becomes capacitive, blocked the CT input partly the HSD or the LSD output (he increases the Dead times to obtain ZVS operation). If the restriction is 16 times a complete one Disappearance of the HSD pulses causes 4 cycles to be released without disturbing the CT input. This total cycle of 20 (16 + 4) repeats 16 times and activates the abnormal function if the disturbance does not disappear.

The SD input is used to detect total ballast failures. If the SD input voltage exceeds the rising threshold (2.2V-3.5V) of the Schmidt trigger corresponding to the occurrence of a total ballast failure, the hardware immediately disables (shuts off) the HSD and LSD outputs while the software is running the anomalous feature is activated. The control unit tries the ballast 2 Seconds after switching off again. If 2 Seconds after ignition of the lamps no abnormal indication is detected, the anomalous protection procedure automatically resets an internal failure counter. If the failure continues to be detected, the control unit attempts to start the ballast 10 times at 3-second intervals between attempts. To 10 The outputs HSD and LSD are permanently disabled. CT protection is also monitored as a total failure.

A Anomalous condition of CT protection starts the same abnormal protection procedure.

Claims (5)

Electronic ballast for a gas discharge lamp, wherein the electronic ballast comprises an input AC circuit ( 47 . 48 ), a common mode inductor ( 31 ) for connecting the input AC circuit to a rectifier in bridge circuit ( 30 ), an inverter circuit having a switch (Q1) of the upper side and a switch (Q2) of the lower side, which is connected to the rectifier in bridge circuit, and the inverter circuit with the gas discharge lamp (US Pat. 45 ) and these triggering resonant circuit ( 40 . 41 ), characterized by a monitoring circuit ( 60 . 61 ) connected to the common mode inductor for detecting a high frequency ground fault current applied to a ground connection having a frequency higher than the frequency of the input AC circuit, and a control circuit (15); 62 ) connected to the monitoring circuit for turning off at least one of the inverter circuit and the power supplied to the inverter circuit when the high frequency ground fault current exceeds a predetermined value. Electronic ballast according to claim 1, further characterized by a DC-DC converter ( 33 ) which corrects power factors and is connected between the bridge-type rectifier and the inverter, an output of the control circuit being connected to the DC-DC power factor correcting converter. Electronic ballast according to claim 1, characterized in that the monitoring circuit is an additional coil ( 60 ) on the common mode inductor and a diode device ( 61 ) connected between the auxiliary coil and the controller. Electronic ballast according to one of claims 1 to 3 for a plurality of gas discharge lamps ( 45 . 45 ), which are removably mounted in a holder, with corresponding filaments ( 43 . 44 ) thereof are connected in parallel to an output of the inverter circuit, characterized in that the resonant circuit ( 40 . 41 . 70 . 71 . 75 . 76 ) is constructed and configured to open a circuit path for a particular gas discharge lamp emanating from the output of the inverter when the lamp is removed from its support. Electronic ballast according to claim 4, wherein the gas discharge lamps first and second Include filaments, wherein first and second terminals of the first and second filaments are connected in parallel, the inverter circuit output a first and a second terminal ( 35 , VSS bus) and the connection resonant circuit has an inductor ( 40 ) and a capacitor ( 41 ) connected in series with a terminal of the output of the inverter, and further characterized in that: a first and a second coil ( 70 . 71 ) are connected to the inductor; a first and a second diode ( 75 . 76 ) are connected in series with the first and the second coil, respectively, the first coil and the first diode are connected in series with the first filaments; the second coil and the second diode are connected in series with the second filaments; the first terminals of the first filaments are connected to the first terminal of the inverter output via the serially connected inductor and capacitor of the connecting resonant circuit; and the first terminals of the second filaments are connected directly to the second terminal of the inverter output.