DE69908193D1 - Ausführung von speicher- und ladeoperationen mittels einer linkdatei - Google Patents
Ausführung von speicher- und ladeoperationen mittels einer linkdateiInfo
- Publication number
- DE69908193D1 DE69908193D1 DE69908193T DE69908193T DE69908193D1 DE 69908193 D1 DE69908193 D1 DE 69908193D1 DE 69908193 T DE69908193 T DE 69908193T DE 69908193 T DE69908193 T DE 69908193T DE 69908193 D1 DE69908193 D1 DE 69908193D1
- Authority
- DE
- Germany
- Prior art keywords
- load operations
- link file
- executing memory
- executing
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3824—Operand accessing
- G06F9/3834—Maintaining memory consistency
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3824—Operand accessing
- G06F9/3826—Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US313873 | 1999-05-18 | ||
US09/313,873 US6266744B1 (en) | 1999-05-18 | 1999-05-18 | Store to load forwarding using a dependency link file |
PCT/US1999/027105 WO2000070469A2 (en) | 1999-05-18 | 1999-11-15 | Store to load forwarding using a dependency link file |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69908193D1 true DE69908193D1 (de) | 2003-06-26 |
DE69908193T2 DE69908193T2 (de) | 2004-04-01 |
Family
ID=23217527
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69908193T Expired - Lifetime DE69908193T2 (de) | 1999-05-18 | 1999-11-15 | Ausführung von speicher- und ladeoperationen mittels einer linkdatei |
Country Status (4)
Country | Link |
---|---|
US (2) | US6266744B1 (de) |
EP (1) | EP1224557B1 (de) |
DE (1) | DE69908193T2 (de) |
WO (1) | WO2000070469A2 (de) |
Families Citing this family (78)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6473837B1 (en) | 1999-05-18 | 2002-10-29 | Advanced Micro Devices, Inc. | Snoop resynchronization mechanism to preserve read ordering |
US6393536B1 (en) | 1999-05-18 | 2002-05-21 | Advanced Micro Devices, Inc. | Load/store unit employing last-in-buffer indication for rapid load-hit-store |
US6473832B1 (en) | 1999-05-18 | 2002-10-29 | Advanced Micro Devices, Inc. | Load/store unit having pre-cache and post-cache queues for low latency load memory operations |
US6427193B1 (en) | 1999-05-18 | 2002-07-30 | Advanced Micro Devices, Inc. | Deadlock avoidance using exponential backoff |
US6266744B1 (en) | 1999-05-18 | 2001-07-24 | Advanced Micro Devices, Inc. | Store to load forwarding using a dependency link file |
AU5027200A (en) * | 1999-05-20 | 2000-12-12 | Intensifi, Inc. | Method and apparatus for access to, and delivery of, multimedia information |
US6405290B1 (en) * | 1999-06-24 | 2002-06-11 | International Business Machines Corporation | Multiprocessor system bus protocol for O state memory-consistent data |
US6662280B1 (en) * | 1999-11-10 | 2003-12-09 | Advanced Micro Devices, Inc. | Store buffer which forwards data based on index and optional way match |
US6487627B1 (en) * | 1999-12-22 | 2002-11-26 | Intel Corporation | Method and apparatus to manage digital bus traffic |
US6651161B1 (en) * | 2000-01-03 | 2003-11-18 | Advanced Micro Devices, Inc. | Store load forward predictor untraining |
US6622237B1 (en) * | 2000-01-03 | 2003-09-16 | Advanced Micro Devices, Inc. | Store to load forward predictor training using delta tag |
US6694424B1 (en) * | 2000-01-03 | 2004-02-17 | Advanced Micro Devices, Inc. | Store load forward predictor training |
US6678807B2 (en) * | 2000-12-21 | 2004-01-13 | Intel Corporation | System and method for multiple store buffer forwarding in a system with a restrictive memory model |
US20020152259A1 (en) * | 2001-04-14 | 2002-10-17 | International Business Machines Corporation | Pre-committing instruction sequences |
US6662277B2 (en) * | 2001-07-31 | 2003-12-09 | Hewlett-Packard Development Company, L.P. | Cache system with groups of lines and with coherency for both single lines and groups of lines |
US7620954B2 (en) * | 2001-08-08 | 2009-11-17 | Hewlett-Packard Development Company, L.P. | Mechanism for handling load lock/store conditional primitives in directory-based distributed shared memory multiprocessors |
WO2003017136A1 (en) * | 2001-08-16 | 2003-02-27 | Etagon Israel Ltd. | Using associative memory to perform database operations |
US6775748B2 (en) * | 2002-01-24 | 2004-08-10 | Intel Corporation | Methods and apparatus for transferring cache block ownership |
US6983348B2 (en) * | 2002-01-24 | 2006-01-03 | Intel Corporation | Methods and apparatus for cache intervention |
US7100001B2 (en) * | 2002-01-24 | 2006-08-29 | Intel Corporation | Methods and apparatus for cache intervention |
US7089371B2 (en) * | 2002-02-12 | 2006-08-08 | Ip-First, Llc | Microprocessor apparatus and method for prefetch, allocation, and initialization of a block of cache lines from memory |
US7089368B2 (en) * | 2002-02-12 | 2006-08-08 | Ip-First, Llc | Microprocessor apparatus and method for exclusively prefetching a block of cache lines from memory |
US7080210B2 (en) * | 2002-02-12 | 2006-07-18 | Ip-First, Llc | Microprocessor apparatus and method for exclusive prefetch of a cache line from memory |
US7080211B2 (en) * | 2002-02-12 | 2006-07-18 | Ip-First, Llc | Microprocessor apparatus and method for prefetch, allocation, and initialization of a cache line from memory |
US7111125B2 (en) * | 2002-04-02 | 2006-09-19 | Ip-First, Llc | Apparatus and method for renaming a data block within a cache |
US7028166B2 (en) * | 2002-04-30 | 2006-04-11 | Advanced Micro Devices, Inc. | System and method for linking speculative results of load operations to register values |
US7222226B1 (en) | 2002-04-30 | 2007-05-22 | Advanced Micro Devices, Inc. | System and method for modifying a load operation to include a register-to-register move operation in order to forward speculative load results to a dependent operation |
US7114043B2 (en) * | 2002-05-15 | 2006-09-26 | Broadcom Corporation | Ambiguous virtual channels |
JP3948615B2 (ja) * | 2002-07-05 | 2007-07-25 | 富士通株式会社 | プロセッサ及び命令制御方法 |
US7089400B1 (en) | 2002-08-29 | 2006-08-08 | Advanced Micro Devices, Inc. | Data speculation based on stack-relative addressing patterns |
US7627721B2 (en) * | 2002-10-08 | 2009-12-01 | Rmi Corporation | Advanced processor with cache coherency |
US7024537B2 (en) * | 2003-01-21 | 2006-04-04 | Advanced Micro Devices, Inc. | Data speculation based on addressing patterns identifying dual-purpose register |
US7657880B2 (en) * | 2003-01-31 | 2010-02-02 | Intel Corporation | Safe store for speculative helper threads |
US20040153611A1 (en) * | 2003-02-04 | 2004-08-05 | Sujat Jamil | Methods and apparatus for detecting an address conflict |
US7188215B2 (en) * | 2003-06-19 | 2007-03-06 | Ip-First, Llc | Apparatus and method for renaming a cache line |
US7321964B2 (en) * | 2003-07-08 | 2008-01-22 | Advanced Micro Devices, Inc. | Store-to-load forwarding buffer using indexed lookup |
US7287126B2 (en) * | 2003-07-30 | 2007-10-23 | Intel Corporation | Methods and apparatus for maintaining cache coherency |
US7676621B2 (en) * | 2003-09-12 | 2010-03-09 | Hewlett-Packard Development Company, L.P. | Communications bus transceiver |
US7237043B2 (en) * | 2003-11-21 | 2007-06-26 | Lsi Corporation | System for improving PCI write performance |
US7263600B2 (en) * | 2004-05-05 | 2007-08-28 | Advanced Micro Devices, Inc. | System and method for validating a memory file that links speculative results of load operations to register values |
US20050289050A1 (en) * | 2004-06-29 | 2005-12-29 | Narayanan Raja P | Automated marketplace presentation and purchasing service for a data computing device |
US7467204B2 (en) * | 2005-02-10 | 2008-12-16 | International Business Machines Corporation | Method for providing low-level hardware access to in-band and out-of-band firmware |
US7418541B2 (en) * | 2005-02-10 | 2008-08-26 | International Business Machines Corporation | Method for indirect access to a support interface for memory-mapped resources to reduce system connectivity from out-of-band support processor |
US7392350B2 (en) * | 2005-02-10 | 2008-06-24 | International Business Machines Corporation | Method to operate cache-inhibited memory mapped commands to access registers |
TWI283411B (en) * | 2005-03-16 | 2007-07-01 | Ind Tech Res Inst | Inter-cluster communication module using the memory access network |
US7376817B2 (en) * | 2005-08-10 | 2008-05-20 | P.A. Semi, Inc. | Partial load/store forward prediction |
US20080010440A1 (en) * | 2006-07-05 | 2008-01-10 | International Business Machines Corporation | Means for supporting and tracking a large number of in-flight stores in an out-of-order processor |
US20080010441A1 (en) * | 2006-07-05 | 2008-01-10 | International Business Machines Corporation | Means for supporting and tracking a large number of in-flight loads in an out-of-order processor |
US20100306509A1 (en) * | 2009-05-29 | 2010-12-02 | Via Technologies, Inc. | Out-of-order execution microprocessor with reduced store collision load replay reduction |
JP5283128B2 (ja) * | 2009-12-16 | 2013-09-04 | 学校法人早稲田大学 | プロセッサによって実行可能なコードの生成方法、記憶領域の管理方法及びコード生成プログラム |
JP5419761B2 (ja) * | 2010-03-12 | 2014-02-19 | アズビル株式会社 | デバイス制御装置およびcpu |
US8868828B2 (en) | 2011-05-24 | 2014-10-21 | International Business Machines Corporation | Implementing storage adapter performance optimization with cache data/directory mirroring |
US8793462B2 (en) * | 2011-05-24 | 2014-07-29 | International Business Machines Corporation | Implementing storage adapter performance optimization with enhanced resource pool allocation |
US8886881B2 (en) | 2011-05-24 | 2014-11-11 | International Business Machines Corporation | Implementing storage adapter performance optimization with parity update footprint mirroring |
US20120303934A1 (en) * | 2011-05-26 | 2012-11-29 | Advanced Micro Devices, Inc. | Method and apparatus for generating an enhanced processor resync indicator signal using hash functions and a load tracking unit |
WO2013101213A1 (en) * | 2011-12-30 | 2013-07-04 | Intel Corporation | Method and apparatus for cutting senior store latency using store prefetching |
US9128725B2 (en) | 2012-05-04 | 2015-09-08 | Apple Inc. | Load-store dependency predictor content management |
US9600289B2 (en) | 2012-05-30 | 2017-03-21 | Apple Inc. | Load-store dependency predictor PC hashing |
US9213641B2 (en) | 2012-06-14 | 2015-12-15 | International Business Machines Corporation | Cache line history tracking using an instruction address register file |
US9286233B2 (en) * | 2012-08-30 | 2016-03-15 | Advanced Micro Devices, Inc. | Oldest operation translation look-aside buffer |
US10198265B2 (en) | 2013-03-15 | 2019-02-05 | Intel Corporation | Microprocessor for gating a load operation based on entries of a prediction table |
US10467010B2 (en) * | 2013-03-15 | 2019-11-05 | Intel Corporation | Method and apparatus for nearest potential store tagging |
CN104346285B (zh) * | 2013-08-06 | 2018-05-11 | 华为技术有限公司 | 内存访问处理方法、装置及系统 |
US9524164B2 (en) | 2013-08-30 | 2016-12-20 | Advanced Micro Devices, Inc. | Specialized memory disambiguation mechanisms for different memory read access types |
US9569212B2 (en) * | 2014-03-28 | 2017-02-14 | Intel Corporation | Instruction and logic for a memory ordering buffer |
US9710268B2 (en) | 2014-04-29 | 2017-07-18 | Apple Inc. | Reducing latency for pointer chasing loads |
DE102015104776B4 (de) * | 2015-03-27 | 2023-08-31 | Infineon Technologies Ag | Verfahren und Vorrichtung zum Verarbeiten von Radarsignalen |
US9514083B1 (en) * | 2015-12-07 | 2016-12-06 | International Business Machines Corporation | Topology specific replicated bus unit addressing in a data processing system |
US10514925B1 (en) | 2016-01-28 | 2019-12-24 | Apple Inc. | Load speculation recovery |
US10437595B1 (en) | 2016-03-15 | 2019-10-08 | Apple Inc. | Load/store dependency predictor optimization for replayed loads |
JP6680978B2 (ja) * | 2016-04-15 | 2020-04-15 | 富士通株式会社 | 演算処理装置及び演算処理装置の制御方法 |
US10528353B2 (en) | 2016-05-24 | 2020-01-07 | International Business Machines Corporation | Generating a mask vector for determining a processor instruction address using an instruction tag in a multi-slice processor |
US10467008B2 (en) | 2016-05-31 | 2019-11-05 | International Business Machines Corporation | Identifying an effective address (EA) using an interrupt instruction tag (ITAG) in a multi-slice processor |
US10248555B2 (en) * | 2016-05-31 | 2019-04-02 | International Business Machines Corporation | Managing an effective address table in a multi-slice processor |
US10545887B2 (en) | 2017-02-24 | 2020-01-28 | Ati Technologies Ulc | Multiple linked list data structure |
US10789175B2 (en) * | 2017-06-01 | 2020-09-29 | Mellanox Technologies Ltd. | Caching policy in a multicore system on a chip (SOC) |
US10387162B2 (en) * | 2017-09-20 | 2019-08-20 | International Business Machines Corporation | Effective address table with multiple taken branch handling for out-of-order processors |
US10713057B2 (en) | 2018-08-23 | 2020-07-14 | International Business Machines Corporation | Mechanism to stop completions using stop codes in an instruction completion table |
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-
1999
- 1999-05-18 US US09/313,873 patent/US6266744B1/en not_active Expired - Lifetime
- 1999-11-15 DE DE69908193T patent/DE69908193T2/de not_active Expired - Lifetime
- 1999-11-15 WO PCT/US1999/027105 patent/WO2000070469A2/en active IP Right Grant
- 1999-11-15 EP EP99960376A patent/EP1224557B1/de not_active Expired - Lifetime
-
2001
- 2001-05-21 US US09/862,687 patent/US6549990B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
WO2000070469A3 (en) | 2002-04-25 |
US6549990B2 (en) | 2003-04-15 |
EP1224557B1 (de) | 2003-05-21 |
US6266744B1 (en) | 2001-07-24 |
DE69908193T2 (de) | 2004-04-01 |
EP1224557A2 (de) | 2002-07-24 |
US20010037434A1 (en) | 2001-11-01 |
WO2000070469A2 (en) | 2000-11-23 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: GLOBALFOUNDRIES INC. MAPLES CORPORATE SERVICES, KY |