DE69900127D1 - Verbessertes Verfahren zur Ausführung ganzzahliger Division - Google Patents

Verbessertes Verfahren zur Ausführung ganzzahliger Division

Info

Publication number
DE69900127D1
DE69900127D1 DE69900127T DE69900127T DE69900127D1 DE 69900127 D1 DE69900127 D1 DE 69900127D1 DE 69900127 T DE69900127 T DE 69900127T DE 69900127 T DE69900127 T DE 69900127T DE 69900127 D1 DE69900127 D1 DE 69900127D1
Authority
DE
Germany
Prior art keywords
integer division
improved procedure
performing integer
division
procedure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69900127T
Other languages
English (en)
Other versions
DE69900127T2 (de
Inventor
Guy Monier
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Application granted granted Critical
Publication of DE69900127D1 publication Critical patent/DE69900127D1/de
Publication of DE69900127T2 publication Critical patent/DE69900127T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/535—Dividing only
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
    • G06F7/728—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic using Montgomery reduction

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Error Detection And Correction (AREA)
  • Complex Calculations (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
DE69900127T 1998-04-02 1999-03-23 Verbessertes Verfahren zur Ausführung ganzzahliger Division Expired - Lifetime DE69900127T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9804273A FR2777098B1 (fr) 1998-04-02 1998-04-02 Procede de realisation ameliore d'une division entiere

Publications (2)

Publication Number Publication Date
DE69900127D1 true DE69900127D1 (de) 2001-07-05
DE69900127T2 DE69900127T2 (de) 2001-09-13

Family

ID=9524919

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69900127T Expired - Lifetime DE69900127T2 (de) 1998-04-02 1999-03-23 Verbessertes Verfahren zur Ausführung ganzzahliger Division

Country Status (4)

Country Link
US (1) US6470372B1 (de)
EP (1) EP0947913B1 (de)
DE (1) DE69900127T2 (de)
FR (1) FR2777098B1 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4712247B2 (ja) * 2001-08-31 2011-06-29 富士通セミコンダクター株式会社 整数除算または整数剰余算を含むアプリケーションプログラム向けのマイクロプロセッサの開発システム
DE10219164B4 (de) * 2002-04-29 2004-12-02 Infineon Technologies Ag Vorrichtung und Verfahren zum Berechnen eines ganzzahligen Quotienten
US20080250032A1 (en) * 2007-04-04 2008-10-09 International Business Machines Corporation Method and system for efficiently saving and retrieving values of a large number of resource variables using a small repository
RU2559771C2 (ru) * 2013-10-30 2015-08-10 Федеральное государственное автономное образовательное учреждение высшего профессионального образования "Северо-Кавказский федеральный университет" Устройство для основного деления модулярных чисел
RU2559772C2 (ru) * 2013-11-06 2015-08-10 Федеральное государственное автономное образовательное учреждение высшего профессионального образования "Северо-Кавказский федеральный университет" Устройство для основного деления модулярных чисел в формате системы остаточных классов
RU2661797C1 (ru) * 2017-06-13 2018-07-19 федеральное государственное автономное образовательное учреждение высшего образования "Северо-Кавказский федеральный университет" Вычислительное устройство

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IL97413A (en) * 1991-03-04 1995-06-29 Fortress U & T 2000 Ltd Microcircuit for the implementation of rsa algorithm and ordinary and modular arithmetic in particular exponentiation with large operands
FR2743646B1 (fr) * 1996-01-12 1998-03-06 Sgs Thomson Microelectronics Coprocesseur d'arithmetique modulaire comportant un circuit de division entiere
FR2745647B3 (fr) * 1996-03-01 1998-05-29 Sgs Thomson Microelectronics Coprocesseur d'arithmetique modulaire permettant de realiser des operations non modulaires rapidement

Also Published As

Publication number Publication date
FR2777098A1 (fr) 1999-10-08
EP0947913B1 (de) 2001-05-30
US6470372B1 (en) 2002-10-22
DE69900127T2 (de) 2001-09-13
EP0947913A1 (de) 1999-10-06
FR2777098B1 (fr) 2001-04-13

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition