DE69821883D1 - Steuerverfahren für elektronische Schaltung und Steuereinheit zu dessen Durchführung - Google Patents

Steuerverfahren für elektronische Schaltung und Steuereinheit zu dessen Durchführung

Info

Publication number
DE69821883D1
DE69821883D1 DE69821883T DE69821883T DE69821883D1 DE 69821883 D1 DE69821883 D1 DE 69821883D1 DE 69821883 T DE69821883 T DE 69821883T DE 69821883 T DE69821883 T DE 69821883T DE 69821883 D1 DE69821883 D1 DE 69821883D1
Authority
DE
Germany
Prior art keywords
circuit
implementation
control
control unit
electronic circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69821883T
Other languages
English (en)
Inventor
Jean-Marie Gaultier
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Application granted granted Critical
Publication of DE69821883D1 publication Critical patent/DE69821883D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/066—Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Communication Control (AREA)
  • Information Transfer Systems (AREA)
DE69821883T 1997-12-19 1998-12-16 Steuerverfahren für elektronische Schaltung und Steuereinheit zu dessen Durchführung Expired - Lifetime DE69821883D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9716193A FR2772944A1 (fr) 1997-12-19 1997-12-19 Procede de gestion d'un circuit electronique et unite de gestion pour sa mise en oeuvre

Publications (1)

Publication Number Publication Date
DE69821883D1 true DE69821883D1 (de) 2004-04-01

Family

ID=9514869

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69821883T Expired - Lifetime DE69821883D1 (de) 1997-12-19 1998-12-16 Steuerverfahren für elektronische Schaltung und Steuereinheit zu dessen Durchführung

Country Status (4)

Country Link
US (1) US6347392B1 (de)
EP (1) EP0924706B1 (de)
DE (1) DE69821883D1 (de)
FR (1) FR2772944A1 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6146224B2 (ja) * 2013-09-12 2017-06-14 株式会社ソシオネクスト 判定方法、判定プログラム、および判定装置

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4791602A (en) * 1983-04-14 1988-12-13 Control Data Corporation Soft programmable logic array
GB2149159B (en) * 1983-10-28 1987-07-08 Membrain Ltd Method and apparatus for generating sequence of multibit words
US4701920A (en) * 1985-11-08 1987-10-20 Eta Systems, Inc. Built-in self-test system for VLSI circuit chips
IL96764A (en) * 1990-12-23 1994-07-31 Zuta Marc Smart card integrated in a wristwatch and having logic unit controlling the automatic identification process and the data transfer
US6279116B1 (en) * 1992-10-02 2001-08-21 Samsung Electronics Co., Ltd. Synchronous dynamic random access memory devices that utilize clock masking signals to control internal clock signal generation
US5481471A (en) * 1992-12-18 1996-01-02 Hughes Aircraft Company Mixed signal integrated circuit architecture and test methodology
US5627842A (en) * 1993-01-21 1997-05-06 Digital Equipment Corporation Architecture for system-wide standardized intra-module and inter-module fault testing
US5682496A (en) * 1995-02-10 1997-10-28 Micron Quantum Devices, Inc. Filtered serial event controlled command port for memory
US5706473A (en) * 1995-03-31 1998-01-06 Synopsys, Inc. Computer model of a finite state machine having inputs, outputs, delayed inputs and delayed outputs
US5870585A (en) * 1995-10-10 1999-02-09 Advanced Micro Devices, Inc. Design for a simulation module using an object-oriented programming language
US6011546A (en) * 1995-11-01 2000-01-04 International Business Machines Corporation Programming structure for user interfaces
US5852726A (en) * 1995-12-19 1998-12-22 Intel Corporation Method and apparatus for executing two types of instructions that specify registers of a shared logical register file in a stack and a non-stack referenced manner
US5870586A (en) * 1996-01-31 1999-02-09 Xilinx, Inc. Configuration emulation of a programmable logic device
US5805931A (en) * 1996-02-09 1998-09-08 Micron Technology, Inc. Programmable bandwidth I/O port and a communication interface using the same port having a plurality of serial access memories capable of being configured for a variety of protocols
US5859993A (en) * 1996-08-30 1999-01-12 Cypress Semiconductor Corporation Dual ROM microprogrammable microprocessor and universal serial bus microcontroller development system
US6078736A (en) * 1997-08-28 2000-06-20 Xilinx, Inc. Method of designing FPGAs for dynamically reconfigurable computing

Also Published As

Publication number Publication date
EP0924706B1 (de) 2004-02-25
FR2772944A1 (fr) 1999-06-25
US6347392B1 (en) 2002-02-12
EP0924706A1 (de) 1999-06-23

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Legal Events

Date Code Title Description
8332 No legal effect for de