DE69734814T2 - LCD CONTROL UPDATING DATA STORED IN A RAM MEMORY - Google Patents

Description

Reference to similar inventions

These Registration is related to the pending applications with the titles "microcontroller with Internal Clock for Liquid Crystal Display "(U. S. Application Serial No. 08/671 933), "microcontroller with Dual Port RAM for LCD Display and Sharing of Slave Ports "(U.S.A. Application Serial No. 08 / 671,962), microcontroller with liquid crystal display Charge Pump "(U.S. Application Serial No. 08 / 671,575), and "Methodology for Testing a Microcontroller Chip Adapted to Control a Liquid Crystal Display "(U.S. Application Serial No. 08 / 671,011), filed on the same day and assigned to the applicant and their disclosures are incorporated by reference in this application are considered.

background the invention

The The present invention generally relates to microprocessors, which are particularly suited to control functions for external systems or subsystems available and therefore generally referred to as a microcontroller be, and in particular, on microcontrollers that are capable of doing so are, driving functions for a liquid crystal display (LCD, liquid crystal display) without the need for additional peripheral elements other than the display itself Available too put.

An LCD generally comprises a pair of glass panes sandwiched with liquid crystal material, the liquid crystal having the property of orienting its crystal-like structure in accordance with an electric field applied between the transparent electrically conductive material on the panes and thereby selectively masking the crystal the passage of light through the liquid crystal makes the darkened pixel visible to the eye. The typical LCD, such as the in 1 shown which is a panel 10 illustrated in the prior art sets a variety of commonly shaped, potentially alphanumeric letters 12 one. Each of the letters is in a figure formed as a block with the shape of an "8" consisting of a plurality of individual rectilinear pixels 15 - typically seven as shown in the figure - though more can be used where greater curvature or detailing of the representation of the individual alphanumeric character to be displayed is desired. For the seven pixel letter, there are three horizontal pixels, such as 17 . 18 , and 19 vertically aligned and equidistant from each other and two vertically aligned pixels 21 . 22 (and 23 . 24 ) are positioned at each end of the matrix limiting the spaces between them.

Conventionally, the pixels are driven by waveforms called a digitally coded matrix of electrical conductors in the form of a printed circuit (in FIG 1 not shown), with each of the conductors on the upper side of the LCD being connected to "segments" while the conductors on the lower side are connected to "common terminals." Therefore, if a particular code (for example, a binary based one) In the form of an electrical stimulus applied to the different conductors, a certain alphanumeric letter is displayed on the LCD, assuming, of course, that there is a light source radiating through the panes, the "segments" are electrically energized by drivers acting as part of a peripheral arrangement, typically in a circuit on a semiconductor chip (in 1 not shown). The "common terminals" are also driven by the circuit on the semiconductor chip in such a way that the RMS voltage dropping above each of the pixels is either above a threshold value (pixel dark) or below a threshold value (pixel transparent). For any LCD, the product of the number of "common ports" multiplied by the number of "segments" is equal to the number of pixels in that display.

LCDs are used in a wide variety of applications that Security systems for homes, operating devices for industrial Temperature controllers, home temperature controllers, sphygmomanometers, blood glucose meters, power meters for alternating current, Toys, recorders for conversations, microwave ovens and detectors for carbon monoxide lock in, to name just a few. The use of LCDs in such applications and in those where one or more microcontrollers are used to control the layout representing the application in The LCD used is in and of itself relatively conventional. The front was the display (which have a large number of pixels can) operated by its own power source and control devices and controlled while the arrangement in which or with which the display uses is controlled separately from the microcontroller. The requirement from separate control units had a detrimental effect on the costs, the complexity and the Size of the whole Control component of the system.

The nature of the problem can be better understood with reference to a relative simple example of a temperature controller used to control the temperature of the air in a housing by means of a controller applied to a heating, ventilation and air conditioning (HVAC) system to control for the housing. A thermo-dependent resistor provides an analog input signal that is a measure of the temperature of the air in the housing. An LCD display provides a visual indication of this temperature and also represents a set point or setpoint temperature that is determined by the user by appropriate selection using a keyboard. An interrupt is provided by an interface of the keyboard that allows the user to input certain information about the keyboard as references used by the microcontroller to change the display, such as writing another output to memory - a selected one Voltage for the thermostat output signal, where the microcontroller turns on a heat pump in the system.

It would be desirable all or at least a substantial part of the control functions within a single product, namely in the chip of the microcontroller But such a goal is by no means a simple task. An LCD display operates at a considerably slower speed as a microcontroller. Also the timing of the control functions of the Microcontroller is different from the timing of the LCD Control functions. Another issue arises in conjunction with the ability that a microcontroller can be put into a "sleep" or a sleep state, to save energy, whereas the LCD display is constantly working got to.

today Systems that control an LCD display, which in turn connect used with a microcontroller controlled arrangement will need among other things a source of time signals to the timing and to control the updating of the display, if not be provided by the microcontroller itself, like that the case is when the latter is in his sleep mode. Although the arrangement of the assembly of the microcontroller is typical a pin for an external input signal is available, it may be that the user of the assembly does not want to use this capability because he prefers this for to use other essential purposes. So that the LCD is in working condition remains, the module for the timing controller provide timing signals to the piece of logic that the LCD display activates. In a typical today's application currently available Microcontrollers are not capable of any time signal function to disposal when they are in the sleep state.

If The application of the user of the arrangement requires that the LCD Display must or should be ready for operation, it will be for the user necessary to use a separate arrangement, the external timing signals for the Control of the LCD available in which the external clock is connected to an external pin of the microcontroller is created. This means that the selected pin (of which only one finite number available is - in a typical arrangement of only one or perhaps two) for one other use purpose is available. And this other use can be much more necessary in an emergency situation.

Two Types of waveforms are alternately used to create an LCD To control the display, as in more detail will be described below. A type A waveform generates waveforms for the "common connection" and the "segment", all the data contained in a single frame and on one another complementary way are composed, such as high voltage and low Voltage to a DC value of zero for the frame to create. It is essential that the tension of the waveform over the glass pane away kept at an average DC value of zero because it is likely that the glass will be damaged, if for a longer time range a DC voltage is applied equal to zero. A type B waveform generates waveforms for the "common Connection "and the" segment "with all the data within two frames, with the actual data in one first frame and put this same data in inverse form in a second frame, so that over two full frames of data an average DC value is maintained by zero.

In general, the Type A waveform is used for simple LCD displays, and the Type B waveform is used for more complex LCDs and higher MUX (multiplex) rate displays, the latter because of a better resolution ratio for Type B, which creates an extended viewing angle. To turn on an LCD pixel, the RMS voltage of each of the two waveforms must exceed the threshold voltage of the glass (or more accurately, the capacitive element that forms the electrically conductive opposing pixel), and to turn off one pixel, the value of the RMS voltage must be be below this voltage threshold. The contrast of the display increases to a limited extent with increases in the RMS voltage above the threshold value of the display Tension of the glass. A significant problem arises in the way in which the waveforms of the voltages are created to efficiently drive the LCD from the microcontroller.

Because the type A waveform data in a single frame with a DC value of Zero returns read from a Random Access Memory (RAM) can be read from RAM at arbitrary times or be written in it. In contrast, in the Type B waveform two frames needed be over It is the zero DC value that needs to be achieved necessary, this data for to keep this entire time in RAM, that is over two Frames or cycles of the waveform. A change in the data in the RAM, for example, before the second frame is completed, it may result in that the second frame is not the inverse of the data in the associated frame contains and a resulting DC value that is not zero is.

The Frequencies of the frames for The LCD controls are relatively slow and in relative terms range from 60 to 100 hertz (Hz), whereas the microcontroller typically operates at frequencies of one megahertz (MHz) or higher. The fast-running microcontroller makes it difficult to get one DC value of zero in the type B waveform upright simply because the data can change so quickly. So Provides the reliability and physical instability of the LCD Glass itself is a problem when using an LCD display Control function is operated with a microcontroller is produced.

Yet another major problem is the way in which in the a control function for an LCD generating microcontroller can be tested. The very slow speed of the LCD display raises serious problems on designing a test methodology that allows it, because microcontrollers in a way to test the speed of its operation is appropriate and not wasteful with testing time or testing costs bypasses. About that In addition, the analog voltages to be reconciled with the LCD are inconsistent and features the desire to test the microcontroller with a digital test device or using digital simulations.

one another set of problems is encountered when the semiconductor substrate, from which the microcontroller is made, more of the P-type than the N type is. The conductivity of the P-type substrate makes it necessary with positive voltages to work, including the generation of positive voltages to the numerous functions of the LCD display and its controller.

One Cardinal The aim of the present invention is an arrangement of a microcontroller to disposal to provide the most efficient and economical LCD control functions merges with the system control functions of the microcontroller. Especially It is an object of the invention to provide an analog interface for reception and the transmission the inputs and outputs of analogue voltages (or other waveforms), an LCD interface for the updating of the LCD display, and the instructions and the Sequence control of the microcontroller for the execution of the control operations into a component - a Product - together respectively.

One associated The goal is to have at least a subset of the ability to make an LCD through to control a microcontroller controlled system, within of the chip of the microcontroller itself.

Yet Another important object of the present invention is to from a microcontroller controlled LCD available in which the user is notified when attempting to update the RAM is canceled.

Summary the invention

In Brevity is explained it the microcontroller according to a preferred embodiment and a preferred method of the invention only allowed in to write the RAM while a prescribed period of time, the integrity of the LCD does not adversely affect when Type B uses waveforms be used to control the display. In particular, it is for the RAM only allowed to be updated after two frames of the waveform have expired are and before a third frame is started. After a permissible update have to two more frames expire before a new update of the RAM can be done.

If an improper time is attempted to write to the RAM, an error bit is set to notify the user that an attempt has been made to update the RAM at an inadmissible time. This aims to guarantee that a voltage exceeding a DC voltage value of zero will not be applied across the glass, at least not for any continuous period of time, thereby avoiding damage to the glass and consequent loss of the LCD. The user does not need to take any special action in response to this flag, and if the flag bit is not set and written to the RAM, writing is allowed. But if the flag bit is set, it will be necessary to look at the write to make sure that all of the data has been entered into the memory or to correct the write if it has not. Because of the frequency with which data is handled in this array and the number of bytes that can be written, the complete data can be written in a single window, making it a valid solution to the problem.

Short description the drawings

The above and other objectives, features and advantages of The invention will be apparent from consideration of the following detailed description of a presently preferred embodiment and a method of use that is currently considered the best Mode of exercise of the invention, in conjunction with the accompanying drawings, in which:

1 shows a simplified functional diagram of a prior art LCD display that is useful for explaining the various components of the display described above;

2 FIG. 4 is a block diagram of an LCD module to be fabricated on a chip together with a microcontroller for an array to be used with the LCD display; FIG.

3A and 3B Examples of Type A and Type B waveforms for driving an LCD are;

4A . 4B a simplified block diagram of a microcontroller with the LCD module off 2 merged into the chip of the microcontroller;

5A and 5B are schematic diagrams of a preferred embodiment of a charge pump, which uses the arrangement of a switched capacitor, which is required to different voltage levels in multiples of a fixed, determined by the power supply (battery) base voltage V _DD , or by the arrangement of an alternative resistance ladder available set required for the LCD display;

6 FIG. 12 is a schematic diagram of a feedback and capacitor overcharge circuit for compensating for in the charge pump with the switched capacitor 5A resulting energy losses;

7 is a simplified block diagram of the coupling of an internal RC oscillator with an LCD module fabricated on-chip together with the microcontroller, the oscillator having the task of providing an internal clock for during periods in which the microcontroller is in a sleep state to provide the LCD display;

8th FIG. 12 is a schematic diagram of an exemplary internal RC oscillator for the circuit of FIG 7 ;

9 and 10A . 10B Figure 4 is a block diagram and a schematic diagram, respectively, of a technology implemented circuit that allows a simplified dual port RAM slave to be shared by a plurality of masters;

11 Figure 4 is a block diagram of a circuit used for the controlled update of the RAM using a Type B waveform to drive the LCD display; and

12 Figure 10 is a simplified block diagram illustrating a preferred methodology for testing the relatively slow speed LCD and LCD control module at high speed.

detailed Description of the Preferred Embodiment and Preferred process

HBezug picking up 2 , is an LCD module 30 included in the semiconductor (typically silicon) chip (not shown), in which a microcontroller (to be described in some detail below) is fabricated using conventional complementary metal-oxide-silicon (CMOS), polysilicon gate process technology. In the preferred embodiment of the invention, the microcontroller and therefore the LCD module are fabricated in a silicon substrate of P-type conductivity, a factor which is essential in some but not all of the aspects of the invention.

LCD module 30 includes a clock source 32 with the ability to select and share with a timer 35 interacts, which controls the operation of the LCD module. The timing 35 instructs the clock source to select one of three clock signal inputs - a signal input from an internal RC oscillator, a signal input T1CKl and a signal input Fosc / 4 - and whether this signal input is to be downshifted. The timer writes to a Random Access Memory (RAM) 37 Also, when to update the data to the control circuit of the I / O pads on the signal lines seg <31: 0>, and also provides the signals lcdclk, lcdph and COM3: COM0 to the control circuit of the connecting cables. The term pads refers to the output of the silicon chip, which then becomes the input of the LCD glass.

The segments of each alphanumeric character of the LCD are driven by digitally coded values that were written in and are now read from RAM 37 and transferred to the pads. The digital values are converted into analog waveforms by the control circuitry of the pads, the timing control signals 35 and analog voltage values provided by a charge pump or other source.

The generated waveforms are either of type A shown in the example 3A , or type B, shown in 3B , Referring to 3A , the common port and segment type A waveform generates waveforms, all data being contained in a single frame of complementary high and low voltage composition and maintaining an average zero DC voltage value over the full frame. In the figure, an LCD and its connection connections for the pixels are shown on the left side of the figure, with the darkening of the individual pixel due to the waveforms shown on the right side, which are generated in a 1/4 multiplexing control, corresponding to the corresponding ones Connections is applied. The pixels are the separate horizontal and vertical bars of an alphanumeric display, although sometimes referred to as segments, and the number of pixels that can be addressed is the arithmetic product of the number of segments multiplied by the number of common ports in the display.

Like in the 3A As shown, each of the common ports may be connected to many pixels. Similarly, each of the segments may be connected to many pixels. The upper display shows the common connection 3 For example, COM3 is connected to the horizontal pixel and the upper left vertical pixel, COM2 is connected to the upper right vertical and middle horizontal pixel, COM1 is connected to the lower left and right vertical pixel, and COM0 is connected to the dot (FIG. Decimal point) and bottom horizontal pixels. In the lower display (which is shown separately for purposes of simplicity and clarity of explanation, but in fact is the same display as that shown above), is Segment 0 (SEG0) is connected to the lower and middle horizontal pixels as well as to the upper and lower left vertical pixels, and SEG1 is connected to the dot, upper and lower right vertical and upper horizontal pixels.

Now if you look at the right side of the 3A Considering the waveforms occurring at the various pins and terminal connections in the first six (counted from top to bottom) parts of the figure are shown. Thus, for the uppermost waveform on pin COM0, the maximum of the waveform waveform (up to 3 V) occurs in the first 1/4 of the multiplex drive; In contrast, the maximum of the waveform for the waveform at COM3 is in the last 1/4. The waveform shown for SEG0 has a maximum of the course in each of the third and fourth 1/4 s of driving. When a common port is "active" (that is, a large RMS value), all pixels associated with that common port are active. Therefore, for example, in the case where COM3 is active, the upper left vertical pixel is active. And this pixel is at a crossroads of COM3 and SEG0. The combination of two waveforms, shown in the penultimate waveform as COM3-SEG0, has a maximum value at one point during the frame (in the last 1/4), so the pixel is "lit" at its point of intersection for the duration of the frame means darkened). On the other hand, the combination of the waveforms for COM0 and SEG0, shown on this side of the figure as the last (lowest) waveform, has never reached a maximum (gradient to 3V) during the frame, so that the bottom horizontal pixel, which is at the intersection of this common port and the segment remains unlit for the duration of the frame (ie, translucent). In the figure, the reference to waveform "selected" and "not selected" means correspondingly simply illuminated and unlit.

The same evaluation applies to the in 3B the display (s) and Type B waveforms except that a 1/4 duty cycle drive is used in which all of the data is generated in two frames or cycles. Again, the LCD and terminal connection are shown on the left side of the figure, with the obscuring of the pixels due to the waveforms shown on the right side and the terminal connections shown on the left side. For example, consider the top waveform on pin COM0 for the frame 1 is shown between the first two dashed vertical lines and frame 2 Immediately following between the second and third dashed vertical line, it will be recognized that the data from frame 2 Precisely the inverse are the current, in frame 1 put together data. As noted previously, this is ei ensure an average DC voltage value of zero over the two frames.

For the present invention, type A waveforms are used at all times (one or the other type would always be used to the exclusion of the other). As discussed hereinabove, an LCD pixel is turned on (i.e., dimmed) by the application of an RMS voltage that exceeds the threshold voltage of the glass. If the RMS voltage falls below this threshold voltage, the pixel is turned off. However, if a Type B waveform is used, the two consecutive frames in incremental changes would be written in and read from memory locations in the RAM. And, since there are two frames of data to achieve the DC average zero for a type B waveform, the data in RAM would be maintained for that entire time period of two frames. As in connection with the discussion below of 11 will be explained, where a Type B waveform is used, the timing of updating the data in the RAM is carefully controlled because a change in data in the RAM before the second frame ended could result in the second frame not the inverse of the data would be contained in the first frame and as a result a non-zero DC value. The high potential for resulting damage to the LCD glass can not be tolerated.

The LCD module 30 out 2 is capable of up to four common ports and 32 To support segments. Each pixel on the LCD glass has two ports, one of which is to a common port and the other to a segment. Each common port can therefore only be connected to as many individual pixels as there are segments.

For any given LCD driver, although the theoretically maximum number of pixels that can be driven is equal to the arithmetic product of the number of common terminals multiplied by the number of segments in the LCD, in reality the maximum number of pixels Pixels that are controllable may be lower than the theoretical maximum because of the load occurring at the analog voltage generator. The timing 35 generates digital signals that indicate which common port is active and in control at any one time, along with the clock source 32 when the data of the segment in RAM 37 be updated to the control circuit of the pad.

4 Figure 12 shows a simplified block diagram of a microcontroller explaining some of its more significant functions and including linking the LCD module and other components such as an internal RC oscillator. The microcontroller 50 is on a silicon chip 51 made in which the LCD module 30 according to 2 is integrated. The microcontroller has an analog interface for the convenience of the users of the device and an LCD interface for the purpose of periodically (or intermittently, as necessary) updating the display and providing analog applications. These functions, along with the microcontroller's instructions and sequencing, enable the device to perform control functions and control operations, all in a single or multi-chip arrangement within a single assembly for the device. All of these control functions are an integral part of the design of the microcontroller and its operation.

Driving an LCD with Type A or Type B waveforms is somewhat complex, using a structured method to control the RMS voltage across the capacitive circuit equivalent to the LCD glass while the DC level across the display is at an average value of zero Volt is to avoid damage to the glass. All of the waveforms are generated by the digital section, which is the LCD module 30 while the analog levels required for the control functions are provided by the voltage generating circuit, which may be internal to or external to the microcontroller.

The core of the microcontroller or the central processing unit (CPU) "speaks" with the logical part of the LCD module to control the timing of the LCD drive and the analogue functions. A voltage generator in the form of a charge pump or resistor ladder generates the voltages needed to drive the pins for the common LCD ports and segments. For LCD applications, discrete voltage levels must be made available, that is, for example, discrete steps of voltage x 1, voltage x 2, and voltage x 3. In the preferred embodiment, the charge pump range of operation is 1.0 volts to 2.3 volts for the base voltage and twice and three times that of the three required output voltages that must be provided. In fact, four voltages are needed, but one of the discrete levels is ground. It should be noted that this is different from the typical charge pump, where only one voltage level is needed, but where several stages are needed to get a fixed low (typically battery) voltage "pump up" to achieve this higher voltage.

Referring now to the schematic diagram 5A , a number of discrete voltage levels required by the LCD display are provided by the charge pump 75 in multiples of a fixed base voltage VLCD1 whose size and range are determined by the power supply (battery) V _DD . This excludes a fourth level VLCD0 which is set to the level of ground V _SS . The voltage of the base level VLCD1 is from a terminal of a power source 77 removed, on one side with the power supply V _DD and on the other side with an adjustable resistor (potentiometer) 78 connected is. The potentiometer is external to the chip 51 which is partially surrounded in the figure by the dashed line. The voltage at this output (VLCDADJ) is via an amplifier 100 with the unity gain applied to the base voltage VLCD1.

The desired voltage level of the charge pump 75 is achieved by using a switched-capacitor method comprising a switch matrix 80 and a control logic 81 used (the latter being a state machine), along with capacitors 83 . 1 . 102 , and 103 , At the first active clock signal, the switches become 80-C through the control logic 81 closed to cause the capacitor connected between pins C1 and C2 83 is charged to the voltage level VLCDI (nominal 2 volts). At the second clock signal, the switches 80-C opened and the switches 80-2 are closed, which causes capacitor 83 connected in series with VLCDI and in parallel with VLCD2. Therefore, the charge is in capacitor 83 on the capacitor 102 transfer. In this way, the effective voltage VLCD2 becomes capacitor 102 ultimately 2 × VLCDI (nominally 4 volts). At the third clock signal, the switches 80-2 opened and the switches 80-C are closed again to the capacitor 83 recharge to the voltage VLCD1. At the fourth clock signal, the switches 80-C opened and the switches 80-3 be closed so that capacitor 83 connected in series with VLCD2 and in parallel with VLCD3. Therefore, the charge in capacitor 83 now on the capacitor 101 and the voltage on VLCD3 will eventually become 3 x VLCD1 (nominal 6V).

The configuration and method of this charge pump takes into account the use of a P-type substrate for the microcontroller and the LCD module, taking into account that negative voltages can not be generated, and allows the generation of positive voltages with respect to ground level one or more Level are exceeded, exceed the operating voltage (V _DD ) of the component. As far as the use of the LCD display is concerned, the only point of interest for the LCD glass is that an RMS value is generated (which, in the course of a single frame in a Type A waveform, or two frames in a Type B waveform, one DC value of zero). It does not matter if this tension is positive or negative.

The user of the arrangement only needs the external potentiometer 78 and the external capacitors 83 . 101 . 102 , and 103 to allow control of the LCD by a voltage generator on the chip. There is no need to provide a separate power supply or voltage regulator. Three voltage levels are passed through the charge pump 75 generated by the multiplication of a voltage by charging the capacitance of a capacitor. The reference to ground provides a fourth level. All of the capacitances used are off-chip, requiring a separate pin for each of the capacitors. External capacitors are used because the current drive currents are of considerable magnitude, therefore, it would require large capacitance values if one were to realize the capacitors directly on the chip, and this would therefore increase the size of the chip substantially.

An alternative technique for obtaining the required discrete voltage levels utilizes a resistance ladder integrated into the silicon chip that suffers both from the need for a voltage supply having a level of output voltage that exceeds the highest voltage otherwise required in the array, as well as from significantly higher power consumption in comparison to the charge pump. Although less desirable for these reasons, a suitable embodiment of a resistor ladder will 90 in 5B shown. The circuit includes the resistors 91 . 92 and 93 , which are connected in this order and last connected to the supply voltage V _DD . A transistor 94 is connected between resistor 93 and VLCD0 to turn on and turn off the resistance ladder. The lowest or base voltage VLCD0 is connected to the potentiometer 95 and the highest voltage is VLCD3, which is connected to V _DD . The three resistors 91 . 92 , and 93 evenly divide the voltage difference between VLCD3 and VLCD0. Therefore, the voltage on VLCD1 is always one third of the voltage difference above VLCD0, and VLCD2 is always two thirds of the voltage difference above VLCD0. The voltages VLCD 0 . 1 , and 2 can be regulated in the voltage drop across the potentiometer 95 is changed.

With a resistor ladder requires a higher supply voltage, such as for example, a 6.5 volt supply. The glass of the LCD display needs be driven with an appropriate level of instantaneous current, which means the sizes of the for the Head elected Resistors sufficient must be low and therefore the current flow through the conductor relative is high compared to the one encountered in the process with the charge pump and switched capacitor. Another The advantage of the charge pump is that the current flow is proportional to the driven LCD glass - ever more segments are turned on, the higher the amperage. in the In contrast, the current flow for a resistance ladder is about the same, independently on the nature of the LCD display.

The Charge pump with switched capacitor is in the handling the drop in voltage that occurs over the life of the battery, also more effective than a resistance ladder. The power source in the Charge pump compensates for the decreasing battery voltage in the despite this decrease a constant current and in this way a relatively uniform reference voltage for the display be maintained. As a result, the LCD voltages on the display for a longer one Period kept constant. In contrast, it follows from the Resistor ladder with the decrease of the supply voltage a drop in the LCD voltages.

Yet some voltage loss occurs in the assembly with use the charge pump, the switching, the resistance of the switches and similar Factors can be assigned, just like any other Meet design with switched capacitors. To compensate, becomes the condition of the overcharging applied, in which the level of voltage at a pin of interest is determined, and the detected value by an analog Input of a comparator fed back becomes. If, due to this active feedback process, an inadequate Degree of charge is detected at the pin, the degree of Laden increased accordingly to compensate for the losses.

There Whenever any losses occur, the discrete ones are graduated Voltages are not a perfect two times and three times the base voltage be. The base voltage is likely to be at or near its original Level remains because it is readjusted, but the second and the third voltage will tend to fall off. As a consequence can out of it for different Data differences are observed in the display, showing a slight loss contrast, which makes it necessary to readjust the display constantly. Furthermore, a DC voltage may be present, which tends to over the Time a damage of the display, resulting in a serious problem with the reliability results. If a very large charge capacity exists is, as in the case where a big one LCD is controlled, the charge pump can fail, so that the Multiplication of the voltage is reduced. Therefore, there is one Limit in terms of the size of the capacity in the LCD display can be controlled.

In the method using the feedback and overcharging of the capacitor for the purpose of compensating for losses of the device, current is drawn from the supply voltage V _DD to charge the capacitors. An exemplary embodiment of such a compensation circuit is shown in FIG 6 shown. Two additional resistors - 105 and 106 - are connected in series with the output circuit of the power source 77 the circuit of the charge pump 5A , Voltages designated ΔV ₁ and ΔV ₂ fall above the resistors 106 respectively 105 and the series connection closes as before on an external potentiometer 78 , A small capacitor 108 is switched in parallel with the potentiometer to filter out noise during the clock signal cycle before the second discrete voltage level VLCD2 is charged. The build up of the charge in the switched capacitor 83 is monitored and sent to the positive input of a comparator 110 created. The negative input of the comparator consists of the base voltage plus ΔV ₂ , since the switch in the path of the circuit from the node between the resistors 105 and 106 during this part of the clock cycle is closed. Therefore, if the charge over the capacitor 83 is lower than the base voltage plus ΔV ₂ , the capacitor is overcharged to the latter voltage.

This is achieved as a result of the output of the comparator 110 that the transistor 112 turns on until the capacitor 83 is charged to the level of the base voltage plus ΔV ₂ and until the two inputs of the comparator have the same value and its output signal is zero. Then, in the clock cycle before VLCD3 is charged, even more losses will be incurred and the base voltage plus ΔV ₁ from the terminal to resistor 106 is applied as an input signal to the comparator. If then the charge current at the capacitor 83 is lower than this level (base level + .DELTA.V ₁ ), an overload is applied to the capacitor, which is terminated as soon as the two input signals at the comparator 110 the same Have value. Therefore, the compensation only takes place when it proves necessary as a result of the feedback circuit and the overcharge circuit is only turned on when it is determined by the feedback that this is necessary to make the capacitor 83 charge.

The main advantages of the arrangement for overcharging the capacitor according to 6 (i) the additional charge is sourced from the internal power supply V _DD ; (ii) active feedback (active charge monitoring) is used to keep the voltage level uniform; and (iii) by using a higher voltage (V _DD ) than that required to reach the overcharge condition (V _CAP ), the time required for the charge to reach this state is reduced. The compensation for losses within the circuit is achieved without the use of a special reference voltage, as might otherwise be expected here as a first consideration. Rather, delta voltage levels are chosen which are close to the likely losses for the process using a charge pump.

The Arrangement is still executed and adjusted to continue the operation of the LCD display even then respectively, while the microcontroller "sleeps", that is in one Operating state is offset with low power consumption, the is referred to as "sleep" or "sleep" state. Although essential functions and monitoring activities are active remain to allow the microcontroller to detect when it is necessary is a control function for the externally controlled arrangement perform, nonessential functions are reset to save energy. According to one important aspect of this embodiment of the invention is an internal cheaper RC oscillator used to control the timing of the LCD to decouple from the microcontroller and timing signals for the display to disposal to deliver. In this way, the sleep state of the microcontroller must be not disturbed to perform the timing functions and the user of the arrangement does not need any external components for the clock functions Make available or such functions over connect an external pin to the array with the microcontroller, but instead the LCD display is moving continue with the operation. And while the periods in which the microcontroller is in the awake state and Completely is ready, the LCD can either from the CPU of the microcontroller or the internal RC oscillator, it being preferred is operated by the microcontroller. Nevertheless, the input signal an external available to enable this input signal, the display during periods to control, in which the microcontroller in the state Sleep the user should be aware of the possibility of such an input signal of an external clock signal.

In the simplified block diagram according to FIG 7 is microcontroller 50 connected to the LCD module 30 to provide, among other things, clock signals from the internal clock of the microcontroller to maintain the timing of the display in operation. If the microcontroller is not prompted to provide functional control of its chip, or to be controlled by an external device intended to be controlled by it, or by peripheral devices, it will be shut down to the sleep state. This can be accomplished in a number of known manners, one of which is to schedule the interval of the last functional activity of the microcontroller, other than to provide timing signals (clock signals) to the LCD module / display. When a predetermined interval has elapsed without further functional activity, the microcontroller enters the sleep state, but may be revived or woken up the next time it is prompted to perform functional activity.

The timing signals from the microcontroller 50 become the LCD module 30 made available. The module selects between the clock sources supplied by the microcontroller 50 and the internal RC oscillator 117 to provide. The user must choose which clock source is desired. The selection of the internal RC oscillator or an external clock signal allows the LCD display to be driven during sleep, but not when the clock signal of the device (the microcontroller's internal clock signal) is selected. The internal on-chip clock signal provided by the RC oscillator is independent of the microcontroller's own internal clock signal.

The circuit of the RC oscillator 117 himself is in 8th shown in more detail, but may be carried out in a completely conventional manner, the essential aspect is the integration of the internal 1 RC oscillator on the chip of the microcontroller. The internal RC oscillator decouples the timing function for the LCD from the microcontroller during the periods when the microcontroller is in the sleep state and allows the timing signals to be provided by the LCD module directly from the oscillator to the LCD display. With reference to 8th switches the input signal CLKEN to the RC oscillator 117 the oscillation when the input signal has the logic level high and turns off the oscillation when the On has the logic low level. In the latter case, the output signal of a NAND gate 120 always in the high state and the output signal of an inverter 123 is always in the low state. Therefore, the output signal CLKOUT of the oscillator 117 in the low state and no oscillations take place.

When the input signal CLKEN at the oscillator changes to the high state, the output signal of the NAND gate changes 120 after low, which eventually causes the input signal of the inverter 125 in the state low changes. Although under these circumstances the output is trying to go high, the order to pull this up is very weak and one with nodes 128 connected capacitor 126 also speaks against it. The capacitor takes about 40 to 50 microseconds (μsec) to charge and, if so, the output signal CLKOUT (which had changed to high when the CLKEN input signal went high) becomes logic level pulled low. The output of the inverter 125 therefore changes to high and the output signal tries to switch to low, but the capacitor 126 is charged and the arrangement for pulling down the signal is weak, so that the capacitor discharges over a period of about 30 to 40 microseconds. Then the output signal CLKOUT changes to high and the process repeats itself. Accordingly, the signal CLKOUT oscillates approximately every 100 μsec.

In this way, the LCD display can over that through the internal RC oscillator 117 provided clock output signal are operated when the microcontroller 50 is in sleep state.

Referring to the block diagram in FIG 9 , which shows a dual port RAM with slave sharing, also shown in the form of a schematic diagram in 10 , prevents classic pre-charging, discharging and clocking of the RAM. For the purpose of controlling the LCD, the data, that is, the pixels, from the user of the device is represented as bits in the RAM 37 ( 2 ) saved. The LCD module 30 then updates the off-chip arrangements so that there will be cases in which the microcontroller 50 with the RAM 37 at the same time that the RAM communicates with the LCD. While the RAM communicates with the microcontroller, it may be updated, ie incremented, by the controller of the LCD, which typically requires large and relatively expensive dual port RAM. The arrangement according to 9 and 10 provides an alternative with smaller size and lower cost.

Here, the RAM comprises a plurality of flip-flops, wherein a master side is controlled by the central processing unit (CPU) of the microcontroller and a slave side is controlled by the LCD module. Four master registers 150 . 151 . 152 and 153 that communicate with the microcontroller as would be the case with any normal RAM register bit, will be for each of the slave registers 154 made available. The updating of the slave register is controlled by the LCD module and it is ensured that such updating does not occur at the same time as the data in a master register is changed. The purpose of this is to ensure that only stable data is presented at the outputs of the LCD segment. The associated, in the pictures of 10 shown master-slave structure is repeated 32 times for the 32 Segments that can be supported by an LCD module.

As an example of the operation of the RAM contains Master Register 150 the data for a particular segment with respect to the shared port 0 , Just before the joint connection 0 becomes active, the LCD module updates the slave register 154 with the data in the master register 150 , The data is then output to the interface of the control logic from where it will be taken when the shared port 0 becomes active. Because the data of the segment for the common connection 0 present on the pad, the LCD module is now capable of the slave register 154 with data from the master register 151 to update. The latter are the data of the segment in relation to the common port 1 just before the joint connection 1 becomes active. Similarly, the data of the segment is relative to the common port 2 in Master Register 152 included, and in terms of common connection 3 in Master Register 153 , This process continues for the specified number of shared ports.

On Reason that the control logic of the pad the Data of the segment locks, the LCD module, the next data of the segment in the slave register from the corresponding master register update before the next one common connection becomes active. Therefore, only one slave register needed for each Output signal of a segment.

On the side of the slave, the impact is on 4 to 1 Multiplexing, but a wired connection is used because the masters are mutually exclusive for the purpose of driving. Just 32 Slaves are needed and in place of 128 (ie 32 × 4) separate master-slave Kombina tions, become 128 Master with the 32 Slaves used. This method of sharing slaves by multiple masters substantially reduces the size and complexity of the RAM by allowing time division multiplexing of slaves by sampling the slave ports, since each slave is read out only in a particular associated time slot , In contrast, a classic dual port RAM requires one master for each slave, with an individual slave for each bit, so that the slave can be read from one side and written to the master from the other. In addition to simplifying the RAM, there is a significant saving in silicon area in this arrangement.

If Type A waveforms are used to drive and control the LCD display, the RAM can be updated at any time. However, at higher MUX rates, Type B waveforms would be preferred. In one embodiment, the Type B waveforms used are shown in FIG 11 , a controlled update of the RAM is performed. When Type B waveforms drive the LCD, according to another aspect of the invention, the microcontroller is allowed to write to RAM only during a predetermined time interval. In particular, updating the RAM is only allowed after two cycles - that is two full frames - of the waveform have expired and before the next cycle is started. After this update, two more cycles of the Type B waveform must expire before the next update of the RAM is allowed.

In 11 It will be the LCD controller 135 from a type B waveform allows the RAM 137 to provide a write permission. This write enable is provided only between the end of the second frame and the beginning of the next frame of data - not in the course of any portion of the current two consecutive cycles of the Type B waveform. In this scheme, if an attempt is made to write to RAM before a write access is allowed, the intended write is rejected and an error bit is asserted by a write error generator 140 to inform the user of the rejected attempt to update the RAM. This method aims to ensure that a voltage exceeding a DC voltage value of zero is not applied across the LCD glass, at least not for a longer period of time, which could otherwise result in damage to the display. The user must decide which action should be taken.

If written into the RAM and no error bit is set, this is always an indication that the writing process of the RAM was accepted and the user is neither notified he is still obliged to take any further steps. But setting an error bit during an intended write requires the need to store the data in the prescribed location to check in the store and, if it turns out to be necessary to carry out a appropriate correction. If desired, an interrupt can be made the LCD controller can be generated to inform the user when a data write operation to the RAM is started.

applies If you look at another point of view, you meet one significant problem in the search for the development of a methodology for the Testing the circuit at high speeds and in terms of comprehensive functional skills the LCD control, because of the relatively low speeds where the LCD and the LCD control module compared to the high speed of the microcontroller work. If for example an analog voltage is applied to a desired function of the microcontroller To test, the test device must be the 60 Hz period of the slow Wait for LCD displays to measure the effect of this voltage or check what a waste of very expensive testing time and effectiveness would. According to the invention an arrangement is used for testing that, exclusively on digital Circuits based, multiplexed values in short time slots used at high speed to check if the correct voltage or the correct pulse in the output signal can be achieved. This allows for low Cost of testing at very high speeds, without the Need to check analog voltages to make sure that the microcontroller and the LCD module work as intended.

Normally, the LCD pin is driven by a driver at low speeds to accommodate the operation of the LCD display and its control module. The invention provides a user mode in which such operation is maintained and, for general-purpose testing at high speed, a test mode in which the LCD pin is driven at high speed. Until then, in user mode, the normal LCD drivers are used for the display to apply the adequate voltages at speeds suitable for the display and the associated functions of the circuit. And, in a separate test mode, another driver capable of operating at very high speed is turned on solely for the sake of testing. If the Test of the arrangement is completed, the high-speed driver is turned off and the normal LCD driver is turned on again to operate the device in the user mode.

Referring to 12 , will an LCD pin 172 on the LCD display usually of small, low speed LCD drivers 173 energized in response to the application of a normal or user mode on signal 175 , As described hereinbefore, the drivers accept LCD data and LCD voltage levels as inputs 177 and 178 to provide adequately coded signals for driving the segments of the LCD display. If the device is to be tested, the signal that activates the normal mode will be removed, resulting in the small LCD driver 173 be turned off, and a signal that turns on the test mode 179 It is designed to enable high-speed large digital drivers 180 LCD pin 172 drive. Testing is done by determining the digital pulse levels and timing directly on the pin. For example, during normal operation of the display, four different analog voltages can be applied to pin 172 with each of these voltages in relation to the other distinct and different time phases. In the test methodology of the invention, test pulses for application to the driver in the different time slots are multiplexed together with the LCD data to provide the high speed digital speed, the low speed of the analog voltages and the timing of the input signals to pin 172 display. The test equipment - a digital tester 185 Then simply watch the digital levels and timing that occur at the pin.

If the pin pulses in a predetermined time slot, this is an indication that the associated analog voltage is being applied at the right time, and so on for each timeslot. This scheme allows the digital tester 185 used to test the port in an analog channel. Instead of looking for discrete voltages, the tester looks for a pulse in a time window at a high-speed port turned on specifically for the test. This method also allows simulations of all the analog LCD functions and voltage levels that can be found in the operation of the LCD module for different applications using a digital simulator limited to "ones" and "zeros".

In addition to its other advantages, is providing a capability that To drive the module in a test mode at high speed without additional Costs or disadvantages achievable from the standpoint of silicon consumption. This is the case because the same transistor is included for test mode purposes high speed can be used when needed is used by the transistor, which is generally in the circuit for protection before electrostatic discharges (ESD, electrostatic discharge) at the connection surface needed becomes.

Even though certain preferred embodiments and methods have been described herein, it will be that in those Technique to which the invention of the preceding description belongs, Trained be obvious that variations and modifications the described embodiments and procedures can be done without depart from the scope of the invention. Accordingly is it is intended that the invention be limited to that of the appended claims and the rules and policies required by applicable law Limited measure shall be.

Claims (4)

Method for controlling the updating of a the data for coding the control of pixels of one or several alphanumeric characters of a Liquid Crystal Display (LCD) storing Random Access Memory (RAM) to an average of one essentially the voltage value zero DC voltage across the transparent, conductive To obtain slices of the LCD comprising the steps: Apply a waveform for driving the LCD, in which the data for Encoding the pixel control over two frames which data is included in a first frame and the same data in inverted form in a second frame are included, so that an average DC value of Zero is achieved over the signal portion of the two frames; Allow the letter in the RAM for updating the data contained therein only after Completion of the second frame and before the start of a new one Signal portion of two frames of this waveform to one not Zeroing the average value of DC over the Avoid the area of the two frames; and Deny an attempt to write to RAM at other times than those between the end of the second frame of a signal component two frames and the beginning of a new signal component of two Frames the waveform sequence and set an error bit as a hint on the back proved attempt. The method of claim 1, further aufwei send the step of responding to said error bit flag by returning to the write attempt that triggered it to determine if all data intended for writing has been stored in RAM. Arrangement for controlling the updating of a Data for encoding the driving of pixels of one or more Alphanumeric characters of a Liquid Crystal Display (LCD) storing Random Access Memory (RAM) to average a substantially the zero voltage DC voltage across the transparent, conductive To achieve slices of the LCD, said arrangement comprising: medium for generating a waveform for driving the LCD, in which Data for transmit the encoding of driving pixels over two frames which data is included in a first frame and the same data in inverted form in a second frame are included, so that an average DC value is achieved by zero over the signal portion of the two frames; Means for allowing the Writing to the RAM to update the data contained therein only after completion of the second frame and before the beginning of a new signal portion of two frames of this waveform to one nonzero average value of DC over the Avoid the area of the two frames; Means to Deny an attempt to write to RAM at other times than those between the end of the second frame of a signal component two frames and the beginning of a new signal component of two Frames the waveform sequence and set an error bit as a hint on the back proved attempt. Arrangement according to claim 3, further comprising a Means of responding to said error Bit Flag by returning to the write attempt that triggered it to see if all data for writing was stored in the RAM.