DE69731917T2 - Data flow in a bus bridge - Google Patents

Description

The The invention relates to a data stream in a computer system.

computer systems generally include one or more peripheral computer interfaces (PCI) buses that have a special communication protocol between peripheral components, such as video control units and network interface cards, and the main memory of the computer system. When a System memory and peripheral components (PCI devices) different buses are available, a bridge is required, to the flow of data transactions between the two buses too manage. The PCI bus architecture is by PCI Local Bus Specification Revision 2.1 ("PCI Spec 2.1 "), published in June 1995, by the PCI Special Interest Group, Portland, Ore., which is incorporated herein by reference. A PCI-to-PCI bridge architecture is through the PCI-to-PCI bridge architecture Specification, Revision 1.0 ("PCI Bridge Spec 1.0 "), released in April 1994, defined by the PCI Special Interests Group.

Under The PCI Spec 2.1 and the PCI Bridge Spec 1.0 architectures support the PCI bridges two types of transactions: posted transactions (including all Memory write cycles) that complete on the initiating bus before finish them on the target bus, and delayed Transactions (including all memory read requests and all I / O and configuration read-write requests), complete on the target bus, before they complete on the initiating bus. A PCI device, the one delayed Transaction initiated must have control of the local PCI bus give up and wait for the target device to get the requested one Data (in the case of a delayed Read request) or a completion message (in the case of a delayed Write request). If Once the requested information has arrived, the requesting device until they turn the control or Control of the PCI bus in the normal course of operations gets before she can get the information from the PCI bridge.

The Document WO-A-95/32475 describes a computer system as described in US Pat the preamble of claim 1 is specified.

According to one Aspect The invention relates to a computer system as claimed 1 is indicated.

One Another aspect of the invention is a method as claimed in 12 is defined.

Further embodiments of the invention are defined in the respective dependent claims.

embodiments of the invention include one or more of the following features. The computer system may include a bus arbitrator, the requesting device a higher one Bus arbitration priority then, when the data storage device starts, allocates the requested data to the bridge provide. The requesting device can maintain the higher priority until the data storage device ceases to supply data to the bridge. If the data storage device begins to supply the requested data the bridge device supply, can the bridge device Stop a transaction that is initiated after the requesting one Device control over gives up the bus. After the transaction is completed, the requesting one Device a higher Bus arbitration priority be assigned. The delayed Request from the requesting device may be a memory read multiple request be. The second data bus may be a PCI bus.

advantages of the invention include one or more of the following items. A "stream" or a "sequence" of data may be between an initiating device and a target device. Such a sequence of data may increase the overall effectiveness of the computer system. A Forming data sequences can reduce the amount of time for which one requesting device to wait for the requested information must reduce, and can reduce the bus latency by eliminating the Reduce the requirement to issue more than one data request. The computer system may stream data by associating a higher Bus Arbitierungs priority to a requesting device, the completion information, the in the bridge enter, own, "support." The computer system can also stream by ending a current bus transaction, if completion dates for another, requesting device to begin to enter the bridge, support.

Other Advantages and features will become apparent from the description below and become apparent from the drawings, in which:

1 shows a block diagram of a computer system.

2 shows a block diagram of an expansion box of the computer system of 1 ,

3 shows a block diagram of the bridge chips in the computer system.

4 shows a block diagram of a queue block in each of the bridge chips.

5 shows a block diagram of the clock routing scheme in the bridge chips.

6 shows a block diagram of a clock generator in each of the bridge chips.

7 Figure 12 shows a block diagram of a master cable interface in each of the bridge chips for transferring data over a cable connecting the bridge chips.

8th shows a timing diagram of signals in the master cable interface.

9 Figure 12 shows a block diagram of a slave cable interface in each of the bridge chips for receiving data transmitted over the cable.

10 Figure 12 shows a block diagram of logic generation input and output pointers for the received logic in the slave cable interface.

11 shows a timing diagram of signals in the slave cable interface.

12 shows a timing diagram of the input and output pointers and their relationship to the recorded cable data.

13 Figure 12 shows a block diagram of the placement of flip-flops and input and output pads in each of the bridge chips.

14 shows a table of information, guided by the cable.

15A Figure 14 shows a table representing the type of information carried by the cable signals associated with single-address-cycle transactions.

15B Figure 14 shows a table representing the type of information carried by the cable signals associated with dual address cycle transactions.

16 shows a table of parameters associated with the cable.

17 shows a logic diagram of an error detection and correction circuit.

18 shows a parity check matrix for generating check bits in the error detection and correction circuit.

19 shows a syndrome table for generating fix bits in the error detection and correction circuit.

20A shows a state diagram illustrating a round-robin arbitration scheme.

20B shows a state diagram illustrating a two-level decision scheme.

21 shows a logic diagram of a decision device in each of the bridge chips.

22 Fig. 10 shows a state diagram of a grant state machine in a decision device.

23 shows a state diagram of a level one of a decision state machine in the decision means.

24 Fig. 12 shows a table illustrating a generation of new grant signals based on the current master.

25 Figure 12 shows a block diagram of logic for generating mask bits and master indication bits with multi-threading capability.

26A shows a logic diagram of circuits for generating the masked bits.

26B shows a block diagram of a computer system with multiple layers of buses.

27A shows a side view of an expansion card, inserted into a slot.

27B - C show schematic diagrams of a lever circuit.

28 - 31 show schematic diagrams of a circuit of the expansion box.

32A shows a state diagram of the circuit of the expansion box.

32B shows waveforms for the circuit of the expansion box.

33A shows a schematic diagram of a circuit of the expansion box.

33B shows waveforms for the circuit of the expansion box.

33C - H show a state diagram of the circuit of the expansion box.

34 shows a schematic diagram of a circuit of the expansion box.

35A shows a state diagram of the circuit of the expansion box.

35B shows waveforms from the circuit of the expansion box.

36 shows a schematic diagram of a circuit of the expansion box.

37 FIG. 12 shows a flow chart of a non-maskable interrupt handler called in response to detection of a bus hang state in the computer system.

38 Figure 12 shows a flowchart of a BIOS program being invoked by a computer system lookup event.

39 FIG. 12 shows a flow diagram of a BIOS isolation program invoked on a bus hang state or the computer lookup event. FIG.

40 shows a block diagram of a bus watcher in each of the bridge chips.

41 Figure 12 shows a state diagram of logic in the bus watcher for returning the bus to an idle state.

42 shows a logic diagram of status signals in the bus watcher.

43 shows a logic diagram of bus history FIFOs and bus state vector FIFOs in the error isolation circuit.

44 Fig. 10 shows a logic diagram of a circuit for generating ready signals for display when the bus history and state vector information is available.

45 Fig. 12 is a flow chart of a program for allocating a bus number to a powered-on or empty slot.

46 Fig. 10 shows a flow chart of a program for allocating memory space for the computer tersystem.

47 shows a flowchart of a program for allocating an I / O space for the computer system.

48 shows a flowchart of a program for handling a newly activated card.

49 shows a block diagram of a configuration space for a PCI bridge circuit.

50A shows a block diagram of a computer system.

50B shows a bus number assignment tree.

51 shows a block diagram illustrating type 0 and type 1 configuration transactions.

52 Figure 14 shows a table having a listing of an address from a primary bus to a secondary bus.

53A and 53B show a logic diagram of a circuit for handling type 0 and type 1 configuration cycles.

54A shows a block diagram of a circuit for storing information to allow calculation of bus function parameters.

54B shows a block diagram of prefetch counters.

55 shows a block diagram of a computer system.

56 shows a block diagram of a PCI decision scheme.

57 shows a schematic diagram of a buffer-emptying logic block.

58 shows a schematic diagram of a cable decoder.

59 - 62 12 show schematic diagrams of a posted memory write queue including control logic.

63 - 65 show schematic diagrams of a delayed request queue, comprising a control logic.

66 - 69b show schematic diagrams of a delayed completion queue, comprising a control logic.

70 - 74 show schematic diagrams and a table of a master cycle decision device.

75 - 87 show schematic and state transition diagrams of a queue block-to-PCI bus interface.

88 Figure 12 is a schematic block diagram illustrating bus devices connected to an expansion bus.

89 Figure 12 is a schematic block diagram illustrating a circuit to continue interrupt requests.

90 shows a schematic diagram of a device selection logic.

91 - 94 show schematic block diagrams of registers.

95 shows a graphical representation representing waveforms for the computer system.

96 shows a schematic diagram of the multiplex operating circuit.

97A - D show schematic diagrams of the interruption recording block.

98 shows a schematic diagram of the interrupt output block.

99 shows a diagram illustrating the time division processing of interrupt request signals.

100 shows a diagram illustrating an interrupt request listing.

101 Figure 12 shows a schematic block diagram illustrating bus devices connected to an expansion bus.

OVERVIEW

In The following description will give all signal mnemonics followed by a "#", "_" or "!", or preceding it, inverted, logical states at.

As in 1 includes a computer system 10 a primary PCI bus 24 that with a bridge chip 26a and a bridge chip 26b both of which are of a common design 26 are. The bridge chip 26a is with a bridge chip 48a over a cable 31 connected and the bridge chip 26b is with the bridge chip 48b over a cable 28 connected. The bridge chips 48a and 48b are of a common design 48 What's common to the design 26 is, with the exception of the design 26 an input-side fashion is and the design 48 is an output-side mode.

The PCI bus 24 is with a local bus 22 via a system controller / host bridge circuit 28 interfaced. The system controller / host bridge circuit 18 also controls access to system memory 20 also with the local bus 22 together with the CPU 14 and a level 2 (L2) cache 16 connected is.

A PCI Extended Industry Standard Architecture (EISA) bridge 15 interfaces the PCI bus 24 with an ISA bus 17 , Both a keypad control unit 21 as well as a read only memory (ROM) 23 are with the ISA bus 17 connected. A non-volatile random access memory (NVRAM) 70 , connected to the ISA bus 17 , stores information that the computer system should inherit when it is turned off. An automatic server recovery timer 72 monitors the computer system for inactivity. If the system locks, the ASR timer becomes 72 after about 10 minutes. A keypad 19 is through the keypad control unit 21 monitored for detection of depressed keys.

As 2 shows forms the bridge chip 48a an interface to a PCI bus 32a and the bridge chip 48b forms an interface to a PCI bus 32b , The PCI buses 32a and 32b are at two expansion boxes 30a and 30b , with a common design 30 , arranged, and each expansion box 30 has six hot-plug slots or slots 36 ( 36a - f ), which are suitable for conventional expansion cards 807 to record ( 27A ). A slot 34 at the expansion box takes a card 46 on that the bridge chip 26 has. Every hot-plug slot 36 own assigned a switching circuit 41 for connecting and disconnecting the slot 36 with and from the PCI bus 32 , Six mechanical levers 802 are used to selectively change the cards 807 at corresponding slots (when closed or locked) as further described in EP-A-0 811 903 entitled "Securing a Card in an Electronic Device" filed on the same date as this application and herewith reference it is described in. Each expansion box 30 includes registers 52 and 82 to monitor the levers 802 and status signals from the expansion box 30 and a register 80 for controlling a connection and a separation of slots 36 and from the PCI bus 32 ,

As 3 shows, the bridge chip is designed to be in pairs 26 and 48 to be used to connect a PCI-PCI bridge between the primary PCI bus 24 and the secondary PCI bus 32 to build. The programming model is that of two hierarchical bridges. The cable appears to the system software 28 as a PCI bus containing exactly one device, the output side bridge chip 48 , This greatly simplifies the configuration of the 2-chip PCI-PCI bridge connecting the primary and secondary buses. The bridge chip 26 that is closer to the CPU 14 lies down, connects the primary PCI bus 24 with the cable 28 , The second PCI-PCI bridge 48 is in the expansion box 30 present and connect the cable 28 with the secondary bus 32 , A mode pin upstream chip determines whether the bridge chip is operating in the output side mode or the input side mode. Some non-bridge features, such as a bus monitor 106 and a hot-plug logic in an SIO 50 , only in the expansion box 30 used and are not in the inlet side fashion chip 26 functional.

A clock generator 102 in the bridge chip 26 generates clocks based on the PCI CLK1 clock on the primary PCI bus 24 where one of the generated clocks is over the cable 28 to a clock generator 122 in the output side bridge chip 48 is provided. The clock generator 122 generates the PCI clocks in the expansion box 30 at the same frequency of the primary PCI bus 24 and controls it, resulting in both bridge chips 26 and 48 run at the same frequency. The output side bridge chip 48 runs the input side bridge chip 24 in phase with the delay of the cable 28 after. An asymmetric boundary in the input-side bridge chip 26 at the point where data from the cable 28 allows the phase delay to be at some value (and therefore the cable should be of any length), the only requirement being that the frequency of the two bridge chips be the same.

The core logic of each bridge chip is the bridge logic block ( 100 or 120 ), which has a PCI master ( 101 or 123 ) for working as a master on the respective PCI bus, a PCI target or a slave ( 103 or 121 ) to work as a slave device on the respective PCI bus, configuration register ( 105 or 125 ), which contain the configuration information of the corresponding bridge chip, and a queue block ( 107 or 127 ), which contains various queues in which data associated with transactions between the primary PCI bus and the secondary PCI bus 32 to be queued and managed. The data transmitted between the input side bridge chip 26 and the output side bridge chip 48 , are through cable interfaces 104 and 130 in the bridge chips 26 and 48 each buffered.

Interrupt program logic is also included in each bridge chip. There are 8 interrupts, 6 from the secondary bus slots, 1 from an SIO circuit 50 and 1 from the output side bridge chip 48 , available. In the output side chip 48 the interrupts are interrupted by an interruption recording block 132 picked up and along the cable 28 sent as a serial data sequence in sequential time pieces. In the output side bridge chip 26 the interrupts are interrupted by an interrupt output block 114 receive, which forwards the interruptions to an interrupt control unit.

The SIO circuit 50 provides control signals for illuminating LEDs, for controlling a reset and for selectively connecting the slots 36 by bus 32 , It also includes logic for reading the engagement status of the levers 802 and the status of the cards 807 in every slot 36 ,

The bridge circuit 26 includes support for interruptions in the expansion box 30 and, when installed in the host system with the user interface to a multi-channel interrupt controller, sends the status states of each interrupt in a serial data stream. The bridge circuit 26 can also be configured to drive standard PCI INTA, INTB, INTC, and INTD signals if installed in a standard slot in the host system.

Each bridge chip also includes a PCI arbitrator ( 116 or 124 ) for controlling access to up to seven bus masters. As the input side bridge 26 Installed in a slot becomes the PCI arbitrator 116 in the input side bridge chip 26 blocked. Each bridge chip also includes an I ² C control unit ( 108 or 126 ) for communication with devices such as EEPROMs, temperature sensors, etc., a JTAG master ( 110 or 128 ) for performing test cycles, a bus monitor ( 106 or 127 ) for measuring bus utilization and effectiveness and the effectiveness of the prefetch algorithm of the bridge chip, and a bus observer (Bus-Watcher) ( 119 or 129 ) for storing a bus history and status vector information and for informing the CPU 14 over a bus-hanging state. Certain blocks are locked in each bridge chip when not in use. In the input side bridge chip 26 become bus watchers 119 , the SIO 118 , the PCI arbitrator 116 and the bus monitor 106 blocked. In addition, the block receiving the break becomes 112 in the input side chip 126 and the interrupt output block 134 in the output side chip 48 blocked.

OVERVIEW THE QUEEN BLOCK

As 4 shows, manage the queue blocks 107 and 127 Transactions between the primary PCI bus 24 (in the input side chip) or the secondary PCI bus 32 (in the output side chip) and the cable interface 130 flow (From here, reference is made to the output side bridge chip assuming that the input side chip operates identically without otherwise indicating). The queue block 127 includes a cable decoder 146 that by the cable interface 130 Transactions on the secondary PCI bus 32 be completed. After decoding a transaction, the decoder places 146 the transactions, along with all the information, are in the transaction, in one of three queues 140 . 142 and 144 , Each queue contains various transaction buffers, each of which stores a single transaction, and is therefore able to handle various transactions simultaneously.

The first queue, a posted memory write queue (PMBQ) 140 , stores posted memory write cycles issued by the CPU on the primary bus along with all the information required to cycle on the secondary bus 32 perform. The PMWQ 140 has four transaction buffers, each of which holds a posted memory write transaction containing up to 8 cache lines (256 bytes) of data. In certain circumstances, a posted memory write transaction having more than eight cache lines of data may overflow into one or more subsequent buffers, as described below.

The second queue, a delayed request queue (delayed request queue). 142 ) stores delayed request transactions (ie, Delayed Read Requests - DRR), such as a memory read (MR), a memory read line (MRL), and memory Memory Read Multiple (MRM) requests, and in the output side chip, input / output (I / O) read write operations and configurations (config read / write operations) are output through the CPU on the primary bus, along with all the information required to do any transaction on the secondary bus 32 perform. The DRQ 142 has three transaction buffers, each of which is capable of holding a doubleword, or "dword", of data for delayed writes.

The third queue, a Delayed Completion Queue (DCQ) 144 , stores delayed completion information provided by the input side chip in response to delayed request transactions generated on the secondary bus 32 , For a delayed read request, the corresponding completion information includes the read data requested by the initiating device and the read status (ie, an indication of whether a parity error has occurred on the target abort). The delayed completion information returned for a delayed write transaction is the same as that returned for a delayed read request, with the exception that no data for delayed writes is returned. Since I / O and config read writes occur only on the output side bus, only the input side DCQ will contain delayed completion information corresponding to one of these transactions. The DCQ 144 has eight completion buffers, each of which can hold up to eight cache lines of completion information for a single, delayed request. In addition to the completion information, each completion buffer also contains a copy of the deferred request that generated the information. For delayed read transactions, there may be a data "sequence" between the primary bus 24 and the secondary bus 32 when the requesting device begins to look up the requested data before the target device stops it to the DCQ 144 to deliver. Under certain circumstances, the DCQ 144 retry additional data or "prefetch" if a requesting device retrieves all the requested data from the corresponding buffer in the DCQ 144 visits. Both streaming and automatic prefetching are discussed in more detail below.

Queue-to-PCI interface (Queue-to-PCI Interface - QPIF) 148 Manages transactions by the queues 140 . 142 and 144 to the PCI bus 32 and from the PCI bus 32 to the DCQ 144 and to the input side chip via the cable interface 130 flow. The QPIF 148 enters a "master" mode to posted memory write and delayed request transactions from the PMWQ 140 and the DRQ 142 to run on the secondary bus. For both posted memory write and delayed read transactions, the QPIF 148 "support" a transaction that employs less than one cache line of data (ie, a memory write (MW) or a memory read (MR) transaction) versus one that has one or more multiple cache lines len (ie a memory write and invalidate (MWI) transaction or memory read line (MRL) or memory read multiple (MRM) transaction, if certain conditions are met.) The QPIF 148 For example, a read transaction that employs a single cache line of data (ie, an MRL transaction) may also convert to one of multiple cache lines of data (ie, an MRM transaction). The QPIF 148 may also "correct" an MRL or MRM transaction starting in the middle of a cache line by reading the entire cache line and then discarding the unsolicited portion of the data. Correction, both of which are described in more detail below, improve system efficiency by reducing the time required to retrieve data from a storage device.

The QPIF 148 enters a "slave" code to get data from the DCQ 144 to a requesting PCI device or transactions from the PCI bus 32 to the DCQ 144 and send to the input side chip over the cable. If the QPIF 148 a posted write transaction from the bus 32 if it receives, it will pass the transaction on to the upstream chip, if any one of a group of transaction counters 159 indicates that the PMWQ in the other bridge chip is not full, as discussed below. If the QPIF 148 When a delayed request is received, it first makes the request to the DCQ 144 to determine if the transaction has already been placed in the DCQ and, if so, the corresponding delayed completion information to the DCQ 144 have been attributed. If the delayed completion information is present in the DCQ, the information is passed to the requesting device and the transaction is terminated. If the request has already been queued, but the delay shield information has not been returned, then the requesting device is retried and the transaction becomes on the PCI bus 32 completed. If the transaction is not yet queued, the DCQ reserves 144 a completion buffer for the transaction and the QPIF 148 performs the transaction to the input side chip via the cable interface 130 continue as long as the corresponding transaction counter 149 indicates that the other bridge chip is not full.

If the DCQ 144 determines that one of them contains buffer data intended for a requesting device, but different than the data requested in the current transaction, the buffer may be flushed to prevent the requesting master from receiving outdated data. The buffer is emptied if it contains prefetch data (ie, data remaining in the buffer after the requesting device has visited some of the data, or data not specifically requested by the device), but it does not deleted if it contains completion data (ie specifically requested by a device that has not yet returned to receive it). If the buffer contains completion data and the requesting device has issued a request that does not "hit" the buffer, the DCQ provides 144 the device with a character as a "multi-threaded" device (ie, one capable of maintaining more than one transaction at a time) and assigns another completion buffer to the new request and multiple buffer allocation schemes will be described in further detail below.

A Master Cycle Arbitrator (MCA) 150 in the queue block 127 maintains standard order constraints between posted memory write, delayed request, and delayed completion transactions, as specified in the PCI Bridge Architecture Specification, Version 2.1. These restrictions require that bus cycles maintain a strong write order and that deadlocks do not occur. That's why the MCA determines 150 the order in which posted memory write transactions in the PMWQ 140 and delayed request transactions in the DRQ 142 on the PCI bus 32 to run. The MCA 150 Also controls the availability of delayed completion information stored in the DCQ 144 , To ensure compliance with these rules, the output MCA gives 150 For each posted memory write cycle, there is an opportunity to bypass previously issued delayed request cycles while both the input and output MCA 150 Do not allow delayed request and delayed completion cycles to bypass previously issued posted memory write cycles. A transaction order by the MCA 150 will be described in more detail below.

The transaction counter 159 in the output-side queue block 127 keep a count of the number of transactions queued in the upstream bridge chip. A counter 160 for posted memory write (PMW) indicates the number of PMW transactions held in the input side posted memory write queue. The PMW counter 160 is incremented at any time when a PMW transaction to the cable interface 130 is sent. The counter 160 is lowered at any time, to which the QPIF 148 a signal from the cable decoder 146 recording, indicating that a PMW cycle on the input side PCI bus 24 has been completed. If the input side PMWQ has queued the maximum number (four) of PMW transactions, the PMW counter returns 160 a PMW full signal (tc_pmw_full) and shares the QPIF 148 with, additional PMW cycles from the PCI bus 32 to try again. Similarly counts a counter 161 for a Delayed Request (DR), the number of DR transactions held in the input side delayed request queue. If the DRQ holds the maximum number (three) of DR transactions, the DR counter represents 161 a DR full signal (tc_dr_full) indicating that the QPIF 148 all subsequent DR transactions from the PCI bus 32 have to try again. A counter 162 Delayed completion (DC) counts the number of delayed completions queued in the upstream Master Cycle Arbitrator. If the MCA holds the maximum number (four) of delayed completions, the DC counter will stop 162 a DC full signal (tc_dc_full), which prevents the output side QPIF 148 delayed request transactions on the secondary PCI bus 32 to run. Once the full state disappears, information about the delayed completion may be sent to the output DCQ.

A PCI interface block 152 is between the PCI bus 32 and the queue block 127 available. The PCI interface 152 includes a master block 123 and a slave (target) block 121 , The slave block 121 enables PCI devices on the bus 32 , on internal registers of bridge chips (eg target memory area registers 155 and configuration registers) to claim completion information contained in the DCQ 144 and also to initiate transactions made by the QPIF 148 and the cable interface 130 be led to the primary bus. The slave block 121 Controls the availability of the PCI bus 32 to the PCI devices on the bus 32 by detecting when each device accesses its REQ # line and the REQ # signals to the PCI arbitrators 124 continues. If the PCI arbitrator 124 selects a requesting device to receive control of the bus, issues the slave block 121 the bus to the device by setting up the GNT # line of the device. Once the bus 32 to the requesting device and the device sets up its FRAME # signal indicating the beginning of a transaction, the slave block locks 121 the transaction information (eg, address, command, data, byte enables, parity, etc.) in a slave lock register 156 , The queue block 127 then is able to get the transaction information from the locking register 156 to visit them and to the DCQ 144 and / or the cable interface 130 to deliver.

Transactions supported by the PCI slave block 121 , are shown in the following table.

PCI-Schnittstellen-Slave-Transaktionen

PCI interface slave transactions

The master block 123 the PCI interface 152 leaves only one cycle initiated by the queue block 127 (ie transactions held in the PMWQ 140 and the DRQ 142 ). The queue block 127 requests from the PCI bus by sending a request signal (q2p_req) to the PCI master 123 which then determines if a corresponding request signal (b1req_) to the PCI arbiter 124 is set up. The master block 123 sets b1req_ if the queue block 127 not a locked cycle is running and the PCI bus 32 not locked by a PCI device. If the PCI arbitrator 124 the queue block 127 selects, sends the master block 123 an acknowledgment signal (p2q_ack) to the queue block 127 to let him know that he has a control of the bus 32 holds. If the PCI arbitrator 124 no open requests from other devices on the bus 32 present, sends the master block 123 automatically the p2q_ack grant signal to the queue block 127 even if the queue block 127 did not set up the q2p_req signal. Once like the queue block 127 receives an arbitration (ie the arbitrator 124 sets the b1gnt_ signal) and sets up its q2p_frame signal to indicate the beginning of a transaction locks the PCI master 123 Outgoing transaction information (ie, address, command, data, byte enables, parity, etc.) into a master lock register 158 in the PCI interface 152 , The transaction information is then used to transact the transaction on the PCI bus 32 complete.

Transactions, supported by the master block 123 , are shown in the following table.

PCI-Schnittstellen-Master-Transaktionen

PCI interface master transactions

Generally, the master block works 123 as a standard PCI master. However, unlike standard PCI bridges, the master block will not terminate an MRL, MRM, or MWI transaction until a cache line limit is reached, just after the master latency timer. MLT) expires. Also, the master block represents 123 not "Initiator Ready" (IRDY) wait states on The master block 123 runs a locked cycle on the PCI bus 32 if the queue block 127 set its "lock" signal (q2p_lock) and its lock on the bus 32 releases when the queue block 127 set its "unlock" signal (q2p_unlock).

As well as 57 shows contains the PCI interface 152 a buffer evacuation logic 154 that determines when one or all of the DCQ completion buffers pass through the queue block 127 should be emptied. The PCI slave 121 generates two signals through the queue block 127 used to flush the completion buffers: a flush signal (p2q_flush) indicating when a buffer should be flushed and a slot selection signal (p2q_slot [2: 0]) indicating which PCI device (ie, which slot on the PCI bus) should be emptied of its data. The following table shows the relationship between p2q_slot [2: 0] and the PCI slot number.

Erzeugung von p2q_slot[2:0]

Generation of p2q_slot [2: 0]

When p2q_flush is set up, the queue block becomes 127 either all completion buffers in the DCQ 144 empty if p2q_slot [2: 0] is equal to "000", or the corresponding one of the eight completion buffers if p2q_slot [2: 0] has any other value The queue block 127 maintains a record of which termination buffers, if any, correspond to each PCI slot at any given time.

The p2q_flush signal is asserted on the rising edge of the first PCI clock (CLK) cycle after a config write (WR-CFG) cycle occurs or after an I / O write (iowr) cycle occurs , or a memory write (memwr) cycle an output-side target (hit_tmem) during an instruction check state (cmd_chk_st) encounters gates 2014 . 2016 . 2018 and 2020 and a flip-flop 2022 are arranged to generate p2q_flush in this way.

In the input side bridge chip (ie, when the upstream_chip_i signal is asserted), p2q_slot [2: 0] always has a value of "001" because the CPU is the only master on the primary PCI bus Value of p2q_slot on whether the cycle leading to a flush condition is one cycle from the secondary bus 32 to the queue block 127 is (ie if p2q_qcyc is set up). If the p2q_qcyc signal is asserted, p2q_slot [2: 0] takes the value of the reg_slot [2: 0] signal generated by the PCI slave 121 , The reg_slot [2: 0] signal indicates which of the seven devices on the secondary PCI bus 32 a control of the bus 32 has been granted. The PCI slave 121 generates the reg_slot [2: 0] signal by locking the value of the GNT # line for each of the seven slots on the bus 32 to form a latched grant signal of seven bits (latched_gnt_ [7: 1], the eighth grant line associated with the queue block is ignored) and by encoding latched_gnt [7: 1] according to one lookup table 2006 , which is indicated below.

Erzeugung von req_slot[2:0]

Generation of req_slot [2: 0]

If the cycle leading to the flush is not a secondary PCI-to-queue block cycle, it must do an I / O read or a config read to the target memory area of one of the plug-in slots on the secondary bus 32 be. If the cycle is an I / O read or a config read (ie! Iowr AND! Wr_cfg), p2q_slot [2: 0] assumes the value of the PCI slot whose memory area has been hit (mrange_slot [2: 0 ]). Otherwise, the cycle is an I / O write or a config write, and p2q_slot [2: 0] becomes equal to "000", so all completion buffers are flushed 2008 and 2010 and multiplexers 2002 and 2004 are arranged to generate p2q_flush [2: 0] in this way.

CABLE DECODER

As 58 shows, the cable decoder receives 146 Transactions from the cable interface and selects the appropriate queue to receive each transaction. If the cable decoder is in the data phase (ie, if data_phase or next_data_phase is present, an asynchronous signal setting the value of data_phase is asserted on the next CLK cycle), the cable decoder sees 146 to the command code (cd_cmd [3: 0]), sent over the cable, to determine which queue the transaction should receive. As shown in the table below, if cd_cmd [3: 0] has a value of "1001", the transaction is a delayed completion so that the cable decoder issues a cd_dcq_select signal telling the dcq to commit the transaction If the three LSBs of the command code signal (cd_cmd [2: 0]) are "111", the transaction is a posted memory write so that the cable decoder generates a cd_pmwq_select signal to send the pmwq over the to warn the incoming transaction. If the transaction is neither a posted memory write nor a delayed completion and the command code is not a streaming signal, the cable decoder asserts a cd_drq_select signal telling the DRQ to claim the transaction. Gates 2024 . 2026 . 2028 and 2030 are configured to generate the cd_dcq_select, cd_pmwq_select, and cd_drg_select signals in this way.

The The following table represents the command code with four bits, assigned to every type of transaction.

Transaktions-Befehl-Code

Transaction command code

When the output-side bridge chip has established a data sequence between the primary bus and a secondary bus master, the input-side cable decoder receives a command code of "1000." This code represents a streaming signal generated by the output-side chip When the cable decoder receives this command code, it sets up a cd_stream signal, which tells the QPIF in the upstream device to continue the transaction The cable decoder generates Also, a cd_stream_next data signal instructing the input side chip to supply a different piece of data to the secondary bus The cd_stream-next_data signal is asserted when a cd_stream signal is asserted, with the transaction in the data phase (ie, data_phase is asserted), and a next_data signal is from the input side chip via the Kab The next_data signal has been received (the next_data signal appears on one of the lines of the c2q_buff [3: 0] signal which, if no data sequence occurs, informs the queue block which output side DCQ buffer is allocated to the current transaction). The cd_stream_next_data signal is deasserted when either the cd_stream signal is deasserted or when a new request is received from the cable interface (ie c2q_new_req is asserted). Gates 2032 and 2034 are configured to generate the cd_stream and cd_stream_next_data signals in this way.

SAVED WRITE QUEUE

As 59 shows is the posted memory write queue (PMWQ) 140 a storage element containing all the command information needed to execute posted write transactions on the target bus. The PMWQ includes a tag storage area 2036 holding information identifying each transaction, a data RAM 2038 which holds the write data associated with each transaction in the PMWQ and various control blocks to manage the flow of transactions into and out of the PMWQ. For each transaction in the PMWQ, the character store retains 2036 Information such as the address to write to, the PCI command code (MW or MWI), an address parity bit, and "a locked cycle" and a "dual address cycle" indication -Bits, as shown in the following table. The character memory 2036 also stores a pointer to the data RAM location of the data corresponding to each of the transactions in the PMWQ.

Inhalte von PMWQ

Contents of PMWQ

Since the PCI Spec. 2.1 requires that posted memory write transactions be executed in the order in which they are received is the tag memory 2036 a circular FIFO device. The PMWQ, and therefore the character memory 2036 , can handle up to four posted memory write transactions simultaneously.

The data RAM 2038 , includes four data buffers 2042 . 2044 . 2046 and 2048 , one for each transaction in the PMWQ. Each buffer can store up to eight cache lines, or 256 bytes, of data (eight words per cache line). For each cache line in a buffer, the buffer stores eight data parity bits 2040 (one per dword) and thirty-two enable bits 2050 (one per byte).

A cable interface block 2060 receives each transaction and the corresponding data from the cable encoder and places the transaction in the character memory 2036 , A queue interface block 2053 receives the data from the cable interface block 2060 and place them in the appropriate location in the data RAM 2038 , The queue interface 2053 also receives data from the data RAM 2038 and deliver them to the QPIF when the QPIF runs the corresponding transaction on the PCI bus. An input pointer pointer logic block 2054 generates four input pointers, one for each buffer, of the queue interface 2053 tell where the next word of data is to be placed. A validity (exit) pointer block 2056 generates four output pointers, one for each buffer, indicating the position of the next word to be used.

As 60 shows holds a validity flag logic block 2052 an eight-bit validity line register 2062 for each of the four buffers in the data RAM 2038 upright. The validity line register 2062 indicates which of the eight cache lines in each buffer contains valid data. If the last word in a cache line has been filled with data (ie valid_pointer [2: 0] corresponds to "111" and cd_next-data is asserted, indicating that the word has been filled), the corresponding bit in a Eight-bit cable validity signal (ie, q0_cable_valid [7: 0], q1_cable_valid [7: 0], etc.) The bit to be set is indicated by the three most significant bits of the validity pointer (valid_pointer [5: 3]) indicating that the cache line is filled in. The corresponding bit in the cable validity signal is also set when a slot validate signal (validate_slot) is received from the cable decoder at the end of a cable valid signal The cable validity signal is placed in the validity line register 2062 latched according to the selected data buffer on the rising edge of the first PCI clock cycle (CLK) after the last word is filled or the valid_slot signal is received. Otherwise the validity line register will keep its current value. The bits in the validity line register 2062 are cleared when the appropriate bits of an eight-bit invalid signal (ie, q0_invalid [7: 0], q1_invalid [7: 0], etc.) are asserted.

The validity flag logic block 2052 generates a pmwq_valid [3: 0] signal indicating which, if any, contains the four data buffers at least one valid row of data. The valid keits block 2052 also generates a pmwq_valid_lines [7: 0] signal indicating which of the eight cache lines of a selected data buffer are valid. A queuing select signal from the QPIF (p2pif_queue_select [1: 0]) is used to select which valid line register 2062 a data buffer is used to generate the pmwq_valid_lines [7: 0] signal. When the queue block is given control of the bus to run a posted memory write cycle from a selected data buffer, the queue block transfers all the data in each row, its corresponding bit in the pewg_valid_lines [7: 0] signal is set. Gates 2064 . 2066 . 2068 . 2070 and 2072 and a flip-flop 2074 are arranged to hold the values in the validity line register 2062 for the first data buffer (q0_valid [7: 0]). A similar circuit determines the contents of the validity registers for the other three data buffers. A multiplexer 2076 selects the value of the pmwg_valid_lines [7: 0] signal.

Like now 61 shows holds a full-line logic block 2058 an eight-bit full-line register 2078 upright for each of the four data buffers. The contents of each full-line register 2078 indicate which of the eight cache lines in the corresponding data buffer are full. The bits in each full-line register 2078 are generated by an asynchronous next_full_line_bit signal, generated by the full-line state machine 2080 , which is described below, set. When a queue select signal from the QPIF (select_nex_queue [3: 1]) selects one of the data buffers and the next_full_line_bit signal asserted, the bit in the full line register becomes 2078 corresponding to the cache line indicated by the three most significant bits of the validity pointer (valid_pointer [5: 3]). A 3x8 decoder 2082 converts the three-bit validity pointer into an eight-bit signal that determines which bit to set. An eight-bit full-line signal (q0_full_line) is for each data buffer of the contents of the corresponding full-line register 2078 generated. The full-line signal indicates which lines in the corresponding data buffer are full. The full-line logic block 2058 also generates a pmwg_full_line [7: 0] signal indicating which cache lines of a selected data buffer are full. The multiplexer 2084 and the q2pif_queue_select [1: 0] signal are used to generate the pmwg_full_line [7: 0] signal.

As well as 62 shows, the full-line state machine 2080 in an IDLE state 2086 placed on a reset. In the IDLE state 2086 the next_full_line_bit is set to zero. When a transaction is placed in the PMWQ, the transaction occurs in two phases, an address phase and a data phase. When the data phase starts (ie, a clock_second_phase signal is asserted) and the valid flag pointer points to the first word in the cache line (valid_pointer [2: 0] = "000"), the state machine goes 2080 to a DATA state 2088 above. In the data state, the next_full_line_bit signal is asserted only if the validity pointer points to the last word in the cache line (valid_pointer [2: 0] = "111"), the cd_next_data signal is asserted by the cable decoder ( indicating that the last word has been filled with data) and the byte enable signal from the cable decoder (cd_byte_en [3: 0]) equals "0000." The state machine also goes back to the IDLE state 2086 when these conditions occur. If these conditions do not occur before the transaction ends (ie, cd_complete is asserted), the next_full_line_bit signal is not asserted and the state machine remains 2080 goes back to the IDLE state 2086 , The state machine 2080 also goes to the IDLE state 2086 without asserting the next_full_line_bit signal if the cd_byte_en [3: 0] signal assumes a value other than "0000".

Like again 59 and also 63 The PMWQ must normally complete a transaction from the cable decoder when the data buffer holding the corresponding data is full. However, if the cable decoder continues to send data after the buffer is full, it leaves an overflow logic block 2090 to make the data overflow into the next empty buffer. The overflow logic block 2090 carries an overflow register 2092 indicating which, if any, of the four data buffers are used as the overflow buffer. The contents of the overflow register 2092 are used to generate a four-bit overflow signal (pmwq_overflow [3: 0]). When the transaction is in the data phase (ie, data_phase is asserted), the valid flag pointer reaches the last word of a data buffer (ie, valid_pointer [5: 0] = "111111"), the cable decoder indicates that more data arrives (ie cd_next_data is set up) and the cable decoder has not indicated that the transaction is complete (ie cd_complete is not up), the select_next_queue [3: 0] signal that is on the most recently filled data Buffer is used to set the overflow register bit corresponding to the next data buffer, if the conditions are not met, the overflow bit is cleared 2094 and 2095 are used in conjunction with the select_next_queue [3: 0] signal to set and clear the appropriate overflow register bits when these conditions are met.

A single transaction may continue to overflow into additional buffers until the last one used buffer is full. If more than one buffer is used as an overflow buffer, multiple overflow register bits are set. Successive set bits in the overflow register indicate that a single transaction has overflowed into more than one buffer. The overflow bits are either set or cleared when the posted write transaction is placed in the PMWQ. Also, if the QPIF starts running the PMW transaction on the target bus and flushing the original buffer while the data is still entering the PMWQ, the original buffer can be reused to continue the overflow transaction. The overflow can continue until all available buffers are full.

QUEUE FOR DELAYED REQUIREMENT

As 64 shows, stores the DRQ 142 all the information needed to complete a Delayed Read Request (DRR) and a Delayed Write Request (DRW) transactions on the target bus. The DRQ includes a queue memory 2100 which holds information such as the address to be read from or written to, the PCI command code, byte enables, address and data parity bits, indication bits over a "locked cycle", and a "Dual address cycle", and the buffer number of the delayed completion buffer reserved in the initiating bridge chip for the completion information. The queue memory 2100 Also holds up to thirty-two bits (one word) of data to be written to the target bus in a delayed write cycle. Since delayed write cycles never use more than one word of data, no data RAM is needed in the DRQ. The DRQ, and therefore the queue memory 2100 , is able to hold up to three delayed request transactions at once. A cable interface block 2102 claims delayed request transactions from the cable decoder and places them in the queue memory 2100 , The following table shows the information that is retained in the DRQ queue store.

Inhalte von DRQ

Contents of DRQ

As well as 65 indicates, determines a validity flag logic block 2104 when the DRQ has received all the information necessary to do the transactions in the queue memory 2100 to run. If one of the DRQ slots is selected by a corresponding slot select signal (ie select_zero for the first slot, select_one for the second slot and select_two for the third slot) and the slot is validated by a validate_slot signal, indicating That the cable decoder has completed delivering the transaction to the DRQ, a validation signal corresponding to the slot (ie, q0_valid, q1_valid, or q2_valid) is asserted on the rising edge of the next PCI clock (CLK) cycle. If a slot is not selected and given a valid_slot signal for gül If the QPIF has selected the slot, the validity signal for the slot or the slot is canceled again, by setting up a DRQ select signal (q2pif_drq_select) and identifying the slot or slot (q2pif_queue_select = Slot number), but discarded the transaction by asserting a cyclic segregation signal (q2pif_abort_cycle). The validity signal is also deasserted if the DRQ completes the transaction by asserting a cycle completion signal (eg, q0_cycle_complete) while the QPIF is waiting for more data (ie, q2pif_next_data is asserted). However, the cycle completion signal is ignored if the QPIF is currently transferring data to the other bridge chip (ie, q2pif_streaming is established) as a data stream. Otherwise, if the slot validity signal is not specifically asserted or retired on a clock cycle, it will maintain its current value. The validity flag logic block 2104 also generates a DRQ validity signal (drq_valid [3: 0]) indicating which, if any, of the three DRQ slots contains a valid transaction by combining the validity signals for each individual slot (ie drq_valid = {0, q2_valid, q1_valid, q0_valid}). Gates 2106 . 2108 . 2110 . 2112 and 2114 , Multiplexer 2116 and 2118 and a flip-flop 2120 are arranged to generate the slot validity signals and the DRQ validity signals in this manner.

The DRQ also includes pointer logic blocks that maintain pointers to the memory locations from which to read data during delayed read request transactions. When the address at which the delayed read transactions begin will be in the queue memory 2100 loaded generates a validity pointer logic block 2122 a six-bit validity pointer indicating where the transaction will end. If the transaction includes a single word (eg, a memory read), the valid flag pointer logic represents 2122 the valid pointer equal to the address loaded in the queue memory 2100 into, up. For a memory read row transaction, the validation pointer pointer logic 2122 the valid pointer indicates a value of "000111", indicating that the last valid portion of the data is an eight dwords (ie, a cache line) beyond the starting point, for a memory read multiple transaction the valid pointer will be set to "111111", indicating that the last valid portion of data is sixty four dwords (ie, eight cache lines) above the starting point. The validity pointer logic 2122 retains a valid pointer for each slot in the DRQ (valid_pointer_0 [5: 0], valid_pointer_1 [5: 0], and valid_pointer_2 [5: 0]). The location of the valid pointer is ignored by the DRQ when it receives a streaming signal from the QPIF (q2pif_streaming), as described in more detail below.

An output pointer logic block 2124 keeps three output pointers (output_pointer_0 [5: 0], output_pointe_1 [5: 0] and output_pointer_2 [5: 0]), one for each slot in the DRQ, indicating the next word of data from memory should be read and fed to the other bridge chip. The pointer is incremented when the QPIF indicates that it is ready to read the next piece of data (ie, it sets the q2pif_next_data signal) once for each word read. Except in streaming situations, a transaction is terminated (completed) when the output pointer reaches the valid pointer. If a transaction ends before all data is read (ie, before the output pointer reaches the input pointer), the QPIF will pick up at the location indicated by the output pointer when the transaction starts again. When the output pointer is incremented, but the output pointer logic 2124 a stepback signal (q2pif_step_back), indicating that the transaction on the PCI bus has ended before the QPIF was able to read the last part of data, lowers the output pointer logic 2124 the counter once so that the last unread part of the data can be read when the transaction starts again. A queue interface block 2126 provides transaction information and the valid and output pointers to the QPIF.

QUEUE FOR DELAYED FINISH

As 66 shows, stores the DCQ 144 delayed completion messages containing the response of the target bus to each delayed request issued to the initiating bus. Delayed completion messages corresponding to delayed read requests include the requested data, while delayed completion messages corresponding to delayed write requests do not include data. A cable interface block 2130 claims delayed completion messages from the cable decoder and provides the delayed completion information to a tag memory 2132 , The DCQ, and therefore the tag store 2132 , is capable of storing up to eight delayed completion messages at once. The tag store 2132 stores information such as the PCI command and the address contained in the original request, leading to the delayed completion message, byte enable bits, address and data parity bits, and "locked cycle" bits and bits a "you al address cycle. "Tag memory is stored for delayed write transactions that use only a single word of data at a time 2132 a copy of the written data. Each of the eight slots in the tag store 2132 includes an implied pointer to one of eight corresponding data buffers in a DCQ data RAM 2134 , For delayed read transactions, the returned data will be in a corresponding data buffer 2135a - H in the data RAM 2134 saved. The following table represents the information stored in the tag store 2132 for every transaction held in the DCQ.

Inhalte von DCQ

Contents of DCQ

Each of the eight data buffers in the DCQ data RAM 2134 can store up to eight cache lines (256 bytes) of delayed completion data. Therefore, the buffers are large enough to store all of the completion data for even the largest delayed request transactions (memory read multiple transaction). However, the capacity of each data buffer can be reduced to four cache lines by setting a configuration bit (cfg2q_eight_line_) in the bridge chip's configuration registers. Each data buffer may be filled by data provided in a single, delayed completion transaction or, if not all requested data is returned in a single, delayed completion transaction, by multiple, delayed completion transactions. However, each data buffer may contain data corresponding to only one original, delayed request, regardless of how many delayed completion transactions it will take to deliver the requested data.

A queue interface block 2136 controls the flow of completion data from the DCQ cable interface 2130 in the data RAM 2134 in and out of the data RAM 2134 out to the QPIF. Three logic blocks generate pointers that direct the input and output of data stored in the eight data buffers. The first block, an input pointer logic block 2138 , maintains a six-bit input pointer for each of the eight data buffers (in_pointer_0 [5: 0], in_pointer_1 [5: 0], etc.). Each input pointer points to the location in the corresponding data buffer to place the next word of data. The second block, an output pointer logic block 2140 , maintains a six-bit output pointer for each of the eight buffers (out_pointer_0 [5: 0], out_pointer_1 [5: 0], etc.). Each output pointer points to the location of the word of data immediately adjacent to the word last removed from the QPIF. The output pointer for a selected data buffer is incremented when the QPIF indicates that it is ready for the next portion of data (ie, when q2pif_next_data is asserted). If the output pointer is incremented, but the last piece of data does not reach the requesting device, since the transaction was terminated by a device other than the QPIF, the QPIF sets a back-step signal (q2pif_step_back) which causes in that the output pointer logic block 2140 lowers the output pointer by one word.

The third pointer block, a valid pointer logic block 2142 For each of the eight-data buffers, a six-bit validity pointer (valid_pointer_0 [0: 5], valid_pointer_1 [5: 0], etc.) maintains the next word of data in the corresponding data buffer that is available to the QPIF is. Since the PCI Spec. 2.1 requires that read completion data not be returned prior to a previously initiated posted memory write transaction, delayed completion data placed into the DCQ while a posted memory write is pending in the PMWQ may not the requesting device until the posted memory write on the PCI bus is completed and removed from the PMWQ. Therefore, as long as any previously queued, posted memory write transactions remain in the PMWQ, the valid pointer must remain in its current location. Then, when all previously queued posted memory writes have been removed from the PMWQ, the valid pointer can be moved to the same location as that in the pointer. If the PMWQ is empty, all delayed completion data is valid (ie, available to the requesting device) as soon as they are stored in the DCQ.

Like the 67A and 67B must show the validity pointer logic block 2142 ask the Master Cycle Arbiter (MCA) to validate any delayed completion transactions that enter the delayed completion queue while a posted memory write is pending in the PMWQ. However, since the MCA can not queuce more than four delayed completion transactions at a time, as discussed below, the validity pointer logic block may 2142 Request a validity of no more than four delayed completion data buffers at once. The validity pointer logic block 2142 Also, logging must be maintained which four delayed completion transactions in the MCA are queued at any given time. To do so, the validity pointer logic block remains 2142 two four-slot registers at: a DCQ buffer number register 2144 and a validity request register 2146 , The buffer number register 2144 maintains the three-bit DCQ buffer number as determined by the DCQ buffer number signal (cd_dcq_buff_num [2: 0]) supplied by the cable decoder from each delayed completion transaction in which MCA queued. The validity request register 2146 retains a transaction valid request bit for each of the DCQ buffers, their numbers in the four slots 2148a - d of the buffer number register 2144 are stored. The request bit in each slot 2150a - d of the validity request register 2146 is established if a corresponding delayed completion transaction is queued in the MCA. The values of the bits in the four validity request slots 2150a - d are provided together with the MCA as a four-bit validity request signal (dcq_valid [3: 0]).

When a delayed completion transaction is to be queued in the MCA, its corresponding DCQ buffer number becomes one of the buffer number slots 2148a - d Invited by the cd_dcq_buff_num [2: 0] signal. The slot 2148a - d which is to be loaded is selected by a two-bit selection signal (next_valid_select [1: 0]). The value of the select signal depends on the value of the dcq_valid [3: 0] signal generated by the validity request register 2146 and the review table 2152 , the contents of which are shown in the table below. The slot is then loaded if it is selected by next_valid_select [1: 0], if the cable decoder has selected the DCQ and completed the transaction (ie cd_dcq_select and cd_complete are set up), and if at least one posted memory Write transaction in which PMWQ is pending (ie pmwq_no_pmw is not set up). Gates 2154 . 2156 . 2158 . 2160 and 2162 and a 2x4 decoder 2164 are arranged to the buffer number register 2144 to load in this way. Similarly, the corresponding bit in the validity request register 2146 through the exit of Gates 2154 . 2156 . 2158 . 2160 and 2162 and the 2 × 4 decoder 2164 set.

Puffer-Zahl-Register-Schlitz-Auswahl

Buffer number register slot selection

On the dcq_valid [3: 0] signal, the MCA outputs a four-bit DCQ run signal (mca_run_dcq [3: 0]) which indicates which of the DCQ buffers is to be pointed to by the buffer count. Register is indicated, its validity may have updated. The mca_run_dcq [3: 0] signal becomes a valid flag pointer updating logic block 2166 delivered, along with the pmwg_no_pmw signal and the pointers for each of the eight data buffers. If a posted memory write transaction remains in the PMWQ after the MCA sets up one of the mca_run_dcq [3: 0] bits (which will occur when a posted memory write transaction has been queued after the delayed completion Transaction has been queued, but before the MCA has set up the corresponding mca_run_dcq bit), the corresponding validity pointer is updated as long as no other delayed completion transactions corresponding to the same DCQ buffer are still queued in the MCA are placed. If a delayed completion transaction for the same DCQ buffer is still queued in the MCA, the validity pointer can only be updated if the mca_run_dcq bit is asserted according to that transaction. On the other hand, once the pmwq_no_pmw signal is deasserted, all validity pointers are updated to match the corresponding in pointers, regardless of whether delayed terminations are still queued in the MCA. If a mca_run_dcq bit is asserted, the corresponding bit in the validity request register becomes 2146 deleted. Gates 2168 . 2170 . 2172 . 2174 and 2176 are arranged to clear the validity request register bits in this manner. Like again 66 indicates, determines a hit logic block 2180 When a delayed request transaction from a requesting device on the PCI bus has "hit" one of the delayed completion messages in the DCQ According to PCI Spec 2.1, the following attributes must be identical for a delayed completion to one Requirement to be adapted: address, PCI command, byte enables, address and data parity (if there is a write request), REQ64 # (if there is a 64-bit data transaction), and LOCK # (if supported) If a request is latched by the PCI slave, the QPIF looks up the request information, sends it to the DCQ, and sets up a check cycle signal (q2pif_check_cyc) containing the DCQ hit logic 2180 instructs the request information about the delayed completion messages stored in the DCQ tag store 2132 , to compare. The hit logic 2180 receives the 64-bit address signal (q2pif_addr [63: 2]), the four-bit PCI command signal (q2pif_cmd [3: 0]), the four enable bits (q2pif_byte_en [3: 0]), the dual address cycle bit (q2pif_dac) (corresponding to the PCI REQ64 # signal), the lock bit (q2pif_lock) from the QPIF, and if the request is a write request, the data being written should (q2pif_data [31: 0]). Although not required by the PCI Spec 2.1, the QPIF also provides the slot number (q2pif_slot [2: 0]) of the requesting device to continue the buffer block deflator program, as described below , The hit logic 2180 then compares each of these signals with delayed completion information stored in the eight DCQ buffers. If all the signals match the information of any of the delayed completion messages, the hit logic identifies 2180 the buffer containing the customization completion message by placing a corresponding bit in an eight-bit hit signal (dcq_hit [7: 0]). When a hit occurs, the QPIF looks up the completion message and delivers it to the requesting device. and, if the request is a read request, it starts removing the returned data from the corresponding data buffer in the data RAM 2134 , If the requested information does not match the completion information of any of the delayed completion messages in the DCQ, the request is "missed" with respect to the DCQ, and is stored in the next available DCQ buffer and transferred over the cable continues to the other bridge chip through the QPIF. A PCI device that initiates a request that missed the DCQ may have its REQ # line masked until its completion message is returned, as described in further detail below.

The hit logic 2180 also interfaces with a multi-threaded master capture block 2182 to capture which PCI slots, if any, contain multi-threaded devices. Multi-threaded devices are capable of maintaining more than one delayed transaction at a time, and must therefore be handled specifically. When a multi-threaded master is detected, a corresponding bit is set in the configuration registers to indicate that the device is capable of supporting multiple, outstanding, delayed transactions, and therefore its REQ # line should not be masked become. A multi-threaded master acquisition will be discussed in more detail below.

Another function of the DCQ is to determine if there is an opportunity to generate a data string of read data between the primary and secondary PCI buses. A streaming opportunity exists when delayed completion data is placed in the DCQ by the cable decoder while still placed on the target bus by the target device. If the PCI device that initiated the transaction returns its request while the target device is still placing data on the PCI bus, a read data string is established. As a reading streaming is an efficient way to transfer data between the primary and the secondary PCI bus, the PCI bridge chip not only gives higher priority in the bus arbitration process to a device whose termination data arrives, but will also try to terminate a non-streaming transaction to improve the possibility that a sequence of data will be established. However, while in theory streaming may occur during any read cycle, in practice it is likely that this only occurs during transactions involving a large amount of data (ie, memory read multiple transactions). Therefore, the queue block will attempt to terminate transactions in favor of potential streaming opportunities only if a potential streaming transaction is a memory read multiple transaction.

As well as 68 indicates, determines a stream logic block 2184 in the DCQ, if there is a streaming opportunity and, if so, it generates the signals needed to support the data sequence. The data sequence logic block 2184 generates the signals required to interrupt a current transaction in favor of a potential data sequence. When the cable decoder places a delayed completion transaction in the DCQ, the data string logic uses 2184 the DCQ buffer number signal supplied by the cable decoder (cd_dcq_buff_num) to the PCI command code stored in the corresponding DCQ buffer (q0_cmd [3: 0], q1_cmd [3: 1], etc.). ). If the instruction code represents a memory read multiple request (ie, "1100"), the data string logic sets 2184 an interrupt-for-data-sequence signal (dcq_disconnect_for_stream) instructing the QPIF and the PCI interface to terminate the current transaction due to a potential streaming opportunity. A multiplexer 2186 and a comparator 2188 are arranged to generate the dcq_disconnect_for_stream signal. Then, as long as the cable decoder continues to provide the completion data to the DCQ (ie the cd_dcq_select signal remains set up) and no posted memory writes appear in the PMWQ (ie, pmwq_no_pmw remains stalled), provides the data sequence logic 2184 a streaming request signal (q2a_stream) directly to the PCI arbiter. The data sequence logic 2184 also supplies the slot number of the potential streaming device (q2a_stream_master [2: 0]) to the PCI arbiter using the cd_dcq_buff_num [2: 0] signal to obtain the PCI slot number stored in the selected DCQ buffer (q0_master [2: 0] for DCQ buffer zero 2135a , q1_master [2: 0] for DCQ buffer one 2135b , etc.). The PCI arbiter then raises the bus arbitration priority of the potential streaming device, as discussed in further detail below. If the potential streaming master is not granted the bus before the streaming opportunity disappears, its priority is returned to normal. Since the input side bus has only one master device (the CPU), this feature is disabled in the input side chip. The gate 2190 and the multiplexer 2192 are arranged to generate the q2a_stream and q2a_stream_master signals.

When a requesting device encounters a delayed completion message stored in the DCQ, the corresponding bit of an eight-bit hit signal (hit [7: 0]) is asserted. The hit [7: 0] signal indicates which of the eight DCQ buffers is hit by the current request. When this occurs, if the corresponding DCQ buffer contains data (ie, dcq_no_data is not asserted), the data string logic locks 2118 the value of the hit signal for the duration of the transaction (that is, as long as q2pif_cyc_complete is set up). The latched version of the hit signal forms a "delayed" hit signal (dly_hit [7: 0]). If either the hit signal or the delayed hit signal indicates that a DCQ buffer has been hit, a three will result Bit-DCQ-string-buffer-signal (dcq_stream_buff [2: 0]), the buffer number of hit DCQ buffer, then, if the cable decoder places delayed completion data in the buffer, while the cycle that hit the buffer is in progress (ie, cd_dcq_select is asserted and cd_dcq_buff_num [2: 0] corresponds to dcq_stream_buff [2: 0]), the data sequence logic block 2180 a data stream connection signal (dcq_stream_connect), which notifies the QPIF that a data string has been established. The QPIF then informs the bridge chip on the target bus that a data string has been established. If certain conditions are met, the target QPIF will continue to work in the data flow until it notifies to stop by initiating QPIF, as discussed in further detail below. Gates 2194 and 2196 , Multiplexer 2198 and 2200 and a flip-flop 2202 are arranged to produce the delayed hit signal. Gates 2204 . 2206 and 2208 and an encoder 2210 are arranged as shown to produce the dcq_stream_connect and dcq_stream_buff [2: 0] signals.

Like again 66 In some circumstances, the DCQ will automatically automatically pre-fetch data from the target bus at the expense of a PCI master in anticipation that the master will come back and request the data. A prefetch logic block 2212 in the DCQ, pre-sets data when the read master consumes all the data in its DCQ buffer and the prefetch logic 2212 expects the requesting device to return with a sequential read request (ie a request that receives data located at the next, sequential location in the memory). Because some devices, such as multi-threaded masters, routinely read all of the data requested in a transaction, and then return with a different non-sequential request, prefetching logic is included 2212 a prediction circuit that blocks the prefetching capabilities for each device on the PCI bus until the device has shown a tendency to issue sequential read requests. Once it returns a device that has received pre-set data with a non-sequential read request, the prediction circuit will disable the prefetching function for that master.

With reference also to the 69a and 69b includes the prefetch logic block 2212 a prefetch prediction register 2214 , the output of which is an eight-bit prefetch enable signal (prefetch_set [7: 0]) which judges whether the prefetching function is available for each of the devices on the PCI bus. All bits in the prefetch enable signal are cleared upon reset (RST) and when the QPIF requests a general clear of all of the DCQ registers (ie, general_flush is set up and q2pif_slot [2: 0] equals "000".) The general_flush Signal will be discussed in more detail below: Gates 2216 and 2218 generate the signal that resets the prefetch_set bits.

An individual bit in the prefetch enable signal is set when the corresponding PCI slot is selected by the q2pif_slot signal and the following conditions occur: the requesting device encounters a delayed completion buffer in the DCQ (FIG. ie one of the bits in the cycle_hit [7: 0] signal is asserted), the current transaction is a memory read line or a memory read multiple cycle (ie q2pif_cmd [3: 0] corresponds to "1100" or " 11110 "), the QPIF has indicated that the cycle is complete (ie q2pif_cyc_complete is set up) and the last word of data was taken from the DCQ buffer (ie last_word is asserted). Gates 2220 . 2222 . 2224 and 2228a - H and a decoder 2226 are arranged to set the prediction bits in this manner. The last_word signal is passed through the prefetch logic 2212 when the requesting device attempts to read past the end of the DCQ buffer. This occurs when the out pointer and the in pointer are equal, indicating that the end of the DCQ buffer has been reached (ie for a four-cache line) Buffer, out_pointer_x [4: 0] equals valid_pointer_x [4: 0] or, for an eight-cache line buffer, out_pointer_x [5: 0] equals valid_pointer_x [5: 0]), and when the requesting device attempts to read another part of data (ie q2pif_next_data is set up). Gates 2230 . 2232 and 2234 are arranged to generate the last_word signal.

An individual bit in the prefetch enable signal is cleared when the corresponding PCI slot is selected and either a PCI clear state occurs (p2q_flush is asserted), the QPIF tells the DCQ to reset the validity pointer of the buffer (q2p_step_back is asserted) or the requesting device initiates a transaction that misses all of the DCQ buffers (q2pif_check_cyc is asserted and dcq_hit is not set up). Gates 2236 . 2238 and 2240a - H and a decoder 2226 are arranged to clear the prediction enable bits in this manner.

If the prefetch function is enabled for a device on the PCI bus, the prefetch logic may be used 2212 generate two types of prefetch signals for the device: a prefetch line signal (dcq_prefetch_line) and a prefetch multiple signal (dcq_prefetch_mul). The prefetch line signal is generated when the current PCI command from the requesting device is a memory read line command signal, and the prefetch multiple signal is then generated when the current PCI command arrives Memory read multiple signal. In either case, the appropriate prefetch signal is generated when the following conditions occur: the prefetch_set bit for the requesting PCI slot is set; a corresponding prefetch enable bit in the configuration registers is set (cfg2q_auto_prefetch_enable); the DRQ in the input chip is not full (! tc_dc_full); the DCQ buffer has room for the corresponding amount of prefetch data (_! dcq_no_prefetch_room); the current cycle hits the DCQ buffer; and the requesting master has tried to read past the end of the DCQ buffer (last_word and q2pif_cyc_complete). Gates 2242 . 2244 . 2246 . 2248 . 2250 , and 2252 , a decoder 2254 and multiplexers 2256 and 2258 are arranged to generate the prefetch signals in this manner.

If the prefetch logic 2212 generating a prefetch signal, it generates a corresponding prefetch address signal (dcq_prefetch_addr [63: 2]) by concatenating the upper fifty-seven bits of the address stored in the corresponding DCQ buffer (q0_addr [63: 7] for buffer zero, q1_addr [63: 7] for buffer one, etc.) with the lower five bits of the output pointer of the buffer (out_pinter_0 [4: 0], etc.). A dual address cycle signal (dcq_prefetch_dac) indicates whether the prefetch transaction is a dual or single address cycle. The dcq_prefetch_cycle signal takes the value of the dual address bits stored in the DCQ buffer (q0_dac, q1_dac, etc.). For both the prefetch address and dual address cycle signals, the appropriate value is from a multiplexer 2260 or 2262 and selected by the three-bit DCQ buffer number signal, indicating which DCQ buffer was hit by the current request.

• 1. Leer (Empty). Verfügbar für eine Zuordnung. Ein Puffer ist leer (empty) nach einem Laden bzw. Hochfahren und nachdem er geleert ist.
• 2. Complete. Der Puffer enthält Abschluss-Informationen für einen verzögerten Abschluss von einer realen, verzögerten Anforderung von einer Vorrichtung auf dem PCI-Bus (d. h. keine Prefetch-Anforderung). Die PCI-Vorrichtung hat noch nicht wieder verbunden und Daten von dem Puffer genommen. Die verzögerte Abschluss-Transaktion ist abgeschlossen.
• 3. Prefetch. Der Puffer enthält Abschluss-Daten für eine Prefetch-Anforderung oder angeforderte Daten, die in dem Puffer belassen wurden, nachdem der anfordernde Master von dem Puffer getrennt ist. Alle Abschluss-Daten sind von dem Target angekommen.
• 4. PartComplete. Der Puffer ist für Abschluss-Informationen für eine reale, verzögerte Anforderung reserviert und kann diese enthalten (d. h. keine Prefetch-Anforderung). Der Master hat noch nicht wieder verbunden und Daten von dem Puffer genommen, und nicht alle Abschluss-Informationen sind von dem Target angekommen.
• 5. PartPrefetch. Der Puffer ist für Abschluss-Informationen für eine Prefetch-Anforderung reserviert oder enthält sie, oder der Puffer enthält angeforderte Daten, die in dem Puffer verblieben, nachdem der anfordernde Master von dem Puffer getrennt ist. Nicht alle Abschluss-Informationen sind von dem Target angekommen.
• 6. Discard. Der Puffer wurde gelöscht, während er in dem PartPrefetch-Zustand war, allerdings sind die letzten Abschluss-Daten bis jetzt noch nicht von dem Target angekommen. Der Puffer wird in den Discard-Zustand versetzt, um zu verhindern, dass er verwendet wird, bis die Transaktion auf dem Target-Bus abgeschlossen ist und die letzten Daten ankommen.

Again with reference to 66 , each DCQ data buffer has various possible states, each of which is represented by a buffer state logic block 2264 determined in the DCQ. The following are the possible buffer states.

• 1. Empty. Available for an assignment. A buffer is empty after a load and after it has been emptied.
• 2. Complete. The buffer contains completion information for a delayed completion of a real, delayed request from a device on the PCI bus (ie, no prefetch request). The PCI device has not reconnected yet and has taken data from the buffer. The delayed closing transaction has been completed.
• 3. Prefetch. The buffer contains completion data for a prefetch request or requested data left in the buffer after the requesting master is disconnected from the buffer. All completion data has arrived from the target.
• 4. PartComplete. The buffer is reserved for completion information for a real, delayed request and may contain it (ie, no prefetch request). The master has not yet reconnected and taken data from the buffer, and not all completion information has arrived from the target.
• 5. PartPrefetch. The buffer is reserved for or contains completion information for a prefetch request, or the buffer contains requested data remaining in the buffer after the requesting master is disconnected from the buffer. Not all completion information has arrived from the target.
• 6. Discard. The buffer was cleared while in the PartPrefetch state, but the final completion data has not yet arrived from the target. The buffer is placed in the discard state to prevent it from being used until the transaction on the target bus is completed and the last data arrives.

When the QPIF requests a DCQ buffer for a delayed request transaction, the buffer state logic maps 2264 add the buffers in the following order. If there is no buffer in the empty or prefetch state, the requesting master must be retried.

DCQ-Puffer-Zuordnung

DCQ buffer allocation

When a device on the PCI bus initiates a delayed read request and a DCQ completion buffer is set next to it, the buffer state logic changes 2264 the state of the buffer to PartComplete. If the DCQ initiates a prefetch read, the buffer state changes to PartPrefetch. When the last part of completion data arrives, the state of the buffer changes from PartComplete or PartPrefetch to Complete or Prefetch respectively. If the requesting device again provides a retry read request and hits the buffer, any valid completion data is given to the master if the buffer is in the Complete, Prefetch, PartComplete or PartPrefetch state.

If the master does not take all the data before an interruption will the state of the buffer changed to Prefetch or PartPrefetch to indicate that unclaimed data is viewed as such be that they are prefetch data. If the master is the last Part of data when the buffer in the Complete or prefetch state, the state of the buffer becomes too high Empty changed.

If a clear signal is received while a buffer is in the prefetch state, the prefetch data in the buffer is discarded and the buffer state is changed to Empty. If a clear event occurs while the buffer is in the PartPrefetch state and completion data is still arriving, the buffer is changed to the discard state until all prefetch data arrives. When the transaction is completed, the prefetch data is discarded and the buffer state is changed to Empty. If the buffer is in the complete or part-complete state, when a clear signal is received, the completion data is left in the buffer and the buffer state remains unchanged. If the clear signal occurs because the corresponding PCI device has issued a new request, ie, a request that is not currently queued, and all of which "miss" the completion buffer), as discussed below As discussed above, the DCQ allocates a new buffer for the transaction Therefore, a PCI device may have more than one terminating buffer allocated to it when the device has a buffer that contains or expects completion data (ie, the buffer is in the Complete or PartComplete state) and the device issues a new request. Because multi-threaded devices are the only devices that can maintain multiple transactions at once, only multi-threaded devices can have multiple-completion buffers reserved at the same time.

MASTER CYCLE ARBITER

Of the Master Cycle Arbiter (MCA) determines the execution order of posted memory write and delayed request transactions while the Order constraints between posted memory write, delayed request and delayed completion cycles retained in PCI Spec. 2.1. According to the PCI Spec 2.1 must guarantee the MCA that executed cycles maintain a strong write order and that no deadlocks occur. To make sure that no deadlocks will occur, posted memory write cycles must be enabled earlier in the Queue asked, delayed To pass requirement cycles, and the required order constraints to be maintained, being delayed Request cycles and delayed Completion cycles must never be allowed to queued earlier, to pass posted memory write cycles.

Referring again to 70 the MCA uses two transaction queues, a transaction run queue (TRQ) or (transaction execution queues) 2270 and a Transaction Order Queue (TOQ) 2272 to manage cycles queued to the PMWQ, the DRQ, and the DCQ. An MCA control block 2274 picks up transactions from the PMWQ, DRQ and DCQ in the form of four-bit valid request signals (pmwq_valid [3: 0], drq_valid [3: 0] and dcq_valid [3: 0]) and issues run instructions in the form of four-bit-run signals (mca_run_pmwq [3: 0], mca_run_drq_ [3: 0] and mca_run_dcq_ [3: 0]). The transactions are in the TRQ 2270 and the TOQ 2272 through a TRQ control block 2276 and a TOQ control block 2278 each moved in and out.

With reference also to 71 is the TRQ 2270 the queue from which the MCA determines the transaction execution order. Transactions in the TRQ 2270 can be executed in any order without violating the transaction order rules, however, once a posted memory write cycle in the TRQ 2270 is placed, no other cycle in the TRQ 2270 be placed until the posted memory write is removed. Transactions in the TRQ 270 are attempted in a circular order and are generally completed in the order in which they were received. However, if a transaction in the TRQ 2270 on the PCI bus, the MCA tries the next transaction in the TRQ 2270 which should be attempted on the PCI bus. Since deferred completion transactions are slave cycles, as opposed to master cycles, they never become in the TRQ 2270 placed. Furthermore, since delayed completion information can be made available to the requesting device as soon as it enters the DCQ, if no posted memory write cycles are pending in the PMWQ, delayed completion transactions in the TOQ will be delayed 2272 placed only when a posted memory write cycle in the TRQ 2270 is pending, as discussed in more detail below.

The TRQ 2270 is a circular queue that holds up to four transactions at once. Since the MCA must always be able to run at least one posted memory write transaction to maintain the required order constraints, the TRQ 2270 never hold more than three delayed request transactions at once. Furthermore, the TRQ can only hold one posted write transaction at a time because posted writes can not be passed through any later initiated transaction involving other posted writes. Every slot 2280a - d in the TRQ 2270 contains three bits of information: a one-bit cycle type indicator 2282 ("1" equal for posted memory write transactions and "0" equal for delayed request transactions), and a two bit validity pointer 2284 The four possible values of which identify which of the buffers in the PMWQ or the DRQ occupy the queued transactions. The TRQ 2270 also includes an input / output enable block 2286 That determines when a transaction enters the TRQ 2270 into or out of it, an input logic block 2288 who is placing a transaction in the TRQ 2270 into it, and an output logic block 2290 , which is a removal of a transaction from the TRQ 2270 controls. These logic blocks contain a standard queue management circuit.

A circular input pointer 2292 selects the next available slot to place an incoming transaction. The input pointer is circular to maintain as much historical order as possible of the incoming transactions.

A circular output pointer 2294 arbitrates between the transactions in the TRQ 2270 and determines their order of execution. The output pointer 2294 always starts with the top slot 2286a in the TRQ 2270 at startup and progressing circularly through the TRQ 2270 therethrough. The output pointer 2294 may be configured to operate in either an infinite retry or zero retry mode by setting or clearing, respectively, an infinite retry bit in the configuration registers (cfg2q_infretry). In an infinite retry mode, the output pointer remains 2294 on a transaction until the transaction successfully runs on the PCI bus. In a zero retry mode, the output pointer becomes 2294 at any time a transaction is attempted on the bus (ie, q2pif_cyc_complete was asserted on the previous PCI clock cycle), regardless of whether the transaction succeeds or is retried. Since PCI Spec 2.1 requires that posted memory write transactions be allowed to bypass delayed request transactions, the output pointer must 2294 in at least one of the bridge chips to be configured to operate in a zero retry mode. Here, the output side chip is always configured to operate in a zero retry mode. Alternatively, the output pointer may be configured to operate in a finite retry mode by allowing each transaction on the PCI bus to be retried a predetermined number (e.g., three) times before the output pointer elevated. Both the upstream and the downstream chip can be configured to operate in a finite retry mode, violating the PCI Spec. 2.1 ordering constraints. In any case, the output pointer will try the historical order of transactions stored in the TRQ 2270 , which only increases if a transaction can not be completed successfully on the target PCI bus.

If a posted memory write or delayed request cycle is from the TOQ 2272 is discarded (new_toq_cycle is set up), as discussed below, or if the TOQ 2272 is not enabled (! toq_enabled) and a new cycle is received by the MCA (new_valid_set), the cycle type bit and the validity bits for the new cycle are loaded into the next empty slot in the TRQ. If the cycle from the TOQ 2272 comes, the valid bits and the cycle type bit are supplied by the TOQ as valid and cycle type signals (toq_valid [1: 0] and toq_cyctype [0]) respectively. Otherwise, the new cycle information is provided by the MCA as valid and cycle type signals (d_valido [1: 0] and d_cyctype [0]). Gates 2296 and 2298 and multiplexers 2300 and 2302 are arranged to control the selection of cycles in the TRQ 2270 to be loaded. When a cycle successfully runs on the PCI bus, the cycle is removed from the transaction order queue and its cycle type bit and validity bits become the MCA control block 2274 as TRQ cycle type and validity signals (trq_cyctype [0]) and trq_valido [1: 0]), respectively.

The TRQ control block 2276 generates a trq_pmw signal indicating when a posted memory write transaction is in the TRQ 2270 queued. When this signal is asserted, subsequently issued, delayed request and delayed completion transactions must be entered into the TOQ 2272 be queued, as discussed below. The trq_pmw signal is then asserted when the MCA control block 2274 the TRQ 2270 has been instructed to queue a new posted memory write cycle (trq_slot_valid_set does not correspond to "0000" and d_trq_cyctype corresponds to "1"), or alternatively, if any of the TRQ slots 2280a - d one cycle (trq_slot_valid [3: 0] does not correspond to "0000"), at least one of the cycles is a posted memory write cycle (trq_cyctype corresponds to "1") and the posted memory write cycle is not from the corresponding slot 2280a - d deleted (! trq_slot_valid_rst [3: 0]). Gates 2304 . 2306 . 2308 . 2310 , and 2312 are arranged to generate the trq_pmw signal in this manner.

Like now the 72 shows is the TOQ 2272 a first-in-first-out (FIFO) queue containing the historical order of transactions received by the bridge after a posted memory write transaction in the TRQ 2270 is placed. Because all transactions must wait for previously issued, posted memory writes to run, all transactions involving posted memory write, delayed request, and delayed completion transactions in the TOQ 2270 placed when posting a memory write to the TRQ 2270 Queue is set. Transactions in the TOQ 2272 need in the TOQ 2272 remain until the posted memory write transaction from the TRQ 2270 is removed.

The TOQ 2270 , the eight slots 2314a - H has up to three posted memory write transactions (the fourth being in the TRQ 2270 stored), three delayed request transactions, and four delayed completion transactions. Each of the slots 2314a - H in the TOQ 2272 contains two cycle type bits 2316 identifying the corresponding transaction ("01" is a posted memory write, "00" is a delayed request, and "1x" is a delayed completion), and two validity bits 2318 that identify which of the buffers in the PMWQ, DRQ, and DCQ occupy the corresponding transaction. The TOQ 2272 also includes standard input and output logic blocks 2320 and 2322 that the movement of transactions into the TOQ 2272 in and out of this.

The positions involving transactions in the TOQ 2272 are placed in and removed from this by a three-bit input counter 2326 (inputr [2: 0]) and a three-bit output counter 2324 (outputr [2: 0]) each determined. Both counters begin at the first slot 2314a in the TOQ 2272 and increment through the queue as transactions are queued and removed. The input counter 2326 increases at the rising edge of each PCI clock cycle where the TOQ 2272 is released (toq_enabled is set up), and the MCA control block 2274 returns a new cycle to the TOQ 2272 (new_valid_set is set up). The validity bits and the cycle type bits for each new cycle are provided by the MCA as valid and the cycle type signals (d_valido [1: 0] and d_cyctype [1: 0]). The output counter 2324 increases at the rising edge of each PCI clock cycle at which the MCA control block 2274 the TOQ 2272 instructed to go to the next cycle (next_toq_cycle will be set up) and the TOQ 2272 is not empty: ie inputr [2: 0] does not match outputr [2: 0]). Cycles in the TOQ 2272 exist are represented by the TOQ validity and cycletype signals (toq_valido [1: 0] and toq_cyctypeo [1: 0]). Gates 2328 and 2330 and a comparator 2332 are arranged to suit the input pointer 2326 and the output pointer 2324 to clock.

If a delayed request transaction or a posted memory write transaction from the TOQ 2272 is singled out, the transaction is in the TRQ 2270 placed to wait for arbitration. However, because delayed deal transactions are target transactions rather than master transactions, delayed deals are not included in the TRQ 2270 placed. Instead, delayed trades simply get out of the TRQ 2272 Screened out and used to validate the corresponding data in the DCQ data buffers. However, as long as a posted memory write transaction must be in the TRQ 2270 queued, all delayed terminations into the TOQ 2272 even if two or more delayed terminations thereof correspond to the delayed request, and therefore the same delayed completion buffer as described above.

As the 73A to 73D show, the MCA control block controls 2274 the flow of transactions through the MCA. As discussed above, the PMWQ, DRQ and DCQ request validity of transactions in the queues by providing four-bit validity signals pmwq_valid [3: 0], drq_valid [3: 0] and dcq_valid [3: 0] each to the MCA. Among these signals, only one bit can change during each clock pulse since only a single, new transaction can be placed in the queue block at each clock pulse. Therefore, the MCA control block identifies new validity requests by monitoring the changing bits in the pmwq_valid, drq_valid, and dcq_valid signals. To do this, the MCA control block latches each signal and inverts it on the rising edge of each PCI clock to produce a delayed, inverted signal and compares the delayed inverted signal to the current signal (ie the signal at the next clock pulse). Since only a newly changed bit will have the same value as its delayed and inverted counterpart, the MCA control block is able to detect which bit has changed. Using flip-flops 2340 . 2342 and 2344 and gates 2346 . 2348 and 2350 , the MCA controller generates new_pmwq_valid [3: 0], new_drq_valid [3: 0] and new_dcq_valid [3: 0] signals that together identify, at each clock pulse, whether the DMWQ, DRQ or DCQ, if any, provided any new transaction for validation and which buffer in the corresponding queue contains the new transaction. As well as 74 shows, the MCA control block uses a look-up table 2352 to convert the twelve bits of the new_pmwq_valid, new_drq_valid, and new_dcq_valid signals to the two bit d_valid [1: 0] and d_cyctype [1: 0] signals supplied to the TRQ and the TOQ, as discussed above.

The MCA controller releases the TOQ by latching the toq_enabled signal to a value of "1" when either the trq_pmw is asserted, indicating that a posted memory write cycle is queued in the TRQ, or if the toq_enable signal is already set up and the TOQ is not empty (! toq_empty). Gates 2354 and 2356 and a flip-flop 2358 are arranged to generate toq_enabled in this way.

The MCA control block sets the new_toq_cycle signal instructing the TRQ to queue the cycle discarded from the TOP if there is not a posted memory write cycle in TRQ during the previous clock cycle (! s1_trq_pmw) was present if the TOQ is not empty (! toq_empty) and if the cycle to be discarded by the TOQ is not a delayed completion transaction (! (toq_cyctypeo [1] = "DC")). The MCA control unit uses a gate 2360 to generate the new_toq_cycle signal.

The next_toq_cycle signal, which is used to increment the TOQ output counter to the next cycle in the TOQ, is asserted when the TOQ is not empty (! Toq_empty) and either when no posted memory write cycles are currently in the TRQ are queued (! trq_pmw) and the next cycle in the TOQ is a delayed completion (toq_cyctype [1] = "DC"), or if the next TOQ cycle is a posted memory write or a delayed request Transaction is (! (Toq_cyctype [1] = "DC")) and there were no posted memory write transactions during the previous clock cycle (! S1_trq_pmw). The control block uses gates 2362 . 2364 . 2366 and 2368 to generate the next_toq_cycle signal.

The MCA controller generates the mca_run_dcq [3: 0] signal to indicate that a delayed completion transaction has been discarded by the TOQ. If the TRQ does not contain posted memory write cycles (! Trq_pmw), the TOQ is not empty (! Toq_empty), and the TOQ cycle is a delayed completion (toq_cyctype [1] = "DC") that mca_run_dcq [3 : 0] Signal takes on the value of the decoded toq_valido [1: 0] signal discussed above, otherwise the mca_run_dcq [3: 0] signal is equal to "0000". The gate 2370 , the decoder 2372 and the multiplexer 2374 are arranged to generate mca_run_dcq [3: 0] in this way.

The MCA control block generates new_mca_run_dr [3: 0] and new_mca_run_pmw [3: 0] signals to indicate that it has a new, delayed request transaction and a posted memory transaction, respectively, to be queued , The new_mca_run_dr [3: 0] signal takes the value of the 2 × 4 decoded d_valido [1: 0] signal, discussed above, when the new cycle is a delayed request cycle (d_cyctype [0] = "DR" Otherwise, all bits of the new_mca_run_dr [3: 0] signal are set to 0. Similarly, the new_mca_run_pmw [3: 0] signal assumes the value of the 2 × 4 decoded d_valido [1: 0] signal when the new cycle is a posted one Memory write transaction is, and is otherwise set to "0000". decoder 2376 and 2380 and multiplexers 2378 and 2382 are arranged to generate the new_mca_run_dr and the new_mca_run_pmw signals in this way.

The MCA controller generates toq_mca_run_dr [3: 0] and toq_mca_run_pmw [3: 0] signals to indicate when a new delayed request transaction or a posted memory write transaction, respectively, has been discarded by the TOQ. The toq_mca_run_dr [3: 0] signal takes the value of the 2 × 4 decoded toq_valido [1: 0] signal when a delayed request cycle is discarded from the TOQ and a value of "0000" otherwise the toq_mca_run_pmw [3: 0] signal indicates the value of the 2 × 4 decoded toq_valido [1: 0] signal when a posted memory write cycle is discarded from the TOQ and a value of "0000" otherwise. decoder 2384 and 2388 and multiplexers 2386 and 2390 are used to generate the toq_mca_run_dr and toq_mca_run_pmw signals in this way.

The MCA controller generates the trq_mca_run_dr [3: 0] and trq_mca_run_pmw [3: 0] signals to indicate when a new, delayed request transaction or a posted memory write transaction has each achieved arbitration in the TRQ, and ready to run on the PCI bus. The trq_mca_run_dr [3: 0] signal takes the value of the 2 × 4 decoded trq_valido [1: 0] signal when a delayed request cycle has been arbitrated and the TRQ is not empty. The trq_mca_run_dr [3: 0] otherwise assumes a value of "0000." Similarly, the trq_mca_run_pmw [3: 0] signal takes the value of the 2 × 4 decoded trq_valido [1: 0] signal when a posted memory Write cycle has reached arbitration and the TRQ is not empty The trq_mca_run_pmw [3: 0] signal is set to a value of "0000" otherwise. The gates 2392 and 2398 , the decoder 2394 and 2400 and the multiplexers 2396 and 2402 are used to generate the trq_mca_run_dr and trq_mca_run_pmw signals in this manner.

If the TRQ is empty, the MCA may issue a request to run the next transaction in the TOQ while placing the transaction in the TRQ. If both the TRQ and the TOQ are empty, transactions can begin to run even before they queue into the TRQ are moderately made. Therefore, the MCA control block includes logic that determines if the new_mca_run or toq_mca_run signals can be used asynchronously to indicate that a transaction on the PCI bus can be attempted. By converting the new_mca_run or toq_mca_run signals into asynchronous run signals, the MCA controller saves a PCI clock wait state. If the new_valid_set signal is asserted by the MCA control block and the TOQ is not enabled (! Toq_enabled), the async_mca_run_dr [3: 0] and async_mca_run_pmw [3: 0] signals take the values of new_mca_run_dr [3: 0] and new_mca_run_pmw [ 3: 0] signals on each. Otherwise, the asynchronous run signals assume the values of toq_mca_run_dr [3: 0] and toq_mca_run_pmw [3: 0] signals. The MCA control unit uses the gate 2404 and the multiplexers 2406 and 2408 to generate the asynchronous run signals.

If a PCI bus master has completed a transaction (s1_q2pif_cyc_complete is asserted), the TRQ is not empty (! Trq_empty) and is configured to operate in the zero retry mode (! Cfg2q_infretry), and any new transaction is from the TOQ has been discarded (new_toq_cycle) or the TOQ is not enabled (! toq_enabled) and the MCA has received a new cycle that is validated (new_valid_set), the MCA can not select one cycle to access on the PCI bus so that both the mca_run_dr [3: 0] and the mca_run_pmw [3: 0] signals are set to "0000." Otherwise, if the TRQ is empty (trq_empty) and either a new transaction is discarded by the TOQ (new_toq_cycle) or the TOQ is not enabled (! toq_enabled) and the MCA has received a new cycle that is declared valid (new_valid_set), then the mca_run_dr [3: 0] and mca_run_pmw [3: 0] signals the value of the asynchronous run signals async_mca_ run_dr [3: 0] and async_mca_run_pmw [3: 0], respectively. Otherwise, the mca_run_dr [3: 0] signal takes the value of the trq_mca_run_dr [3: 0] signal and the mca_run_pmw [3: 0] signal takes the value of the trq_run_pmw [3: 0] signal, with AND with the validity request Signal from the PMWQ linked (pmwq_valid [3: 0]). Gates 2410 . 2412 . 2414 . 2416 and 2418 and multiplexers 2420 . 2422 . 2424 and 2426 are arranged to generate the MCA run signals in this manner.

THE QUEUE BLOCK-TO-PCI INTERFACE (QPIF)

How the turn 4 and 75 show, heads the QPIF 148 the flow of transactions between the queue block 127 and the PCI bus 32 , The QPIF 148 also provides transactions initiated on the PCI bus 32 , to the cable interface 130 , The QPIF 148 works in two modes: a master mode and a slave mode. In the master mode, the QPIF 148 Control over the PCI bus and therefore carries out transactions intended for target devices on the bus. A master state machine 2500 in the QPIF 148 searches for transactions from the PMWQ and DRQ and executes them on the PCI bus when the QPIF is in master mode. In the slave mode, the QPIF receives 148 Transactions initiated by a device on the PCI bus and either provide the requested information to the initiating device (if the information is available), or retrieve the initiating device (if the transaction is a deferred request) and continue the transaction to the input side chip. The transaction is also visited if the corresponding one of the transaction counters 159 indicates that the other bridge chip is full, as discussed above. A slave state machine 2502 receives an incoming transaction from the PCI bus and then checks the DCQ for a corresponding completion message and / or routes the transaction to a cable message generator 2504 which in turn continues the transaction over the cable to the input bridge chip.

With reference also to the 76A and 76B The QPIF includes address and data latch logic 2506 which latches the incoming address phase and data phase information associated with each transaction initiated by a device on the PCI bus. The QPIF slave state machine 2502 Controls the operation of the address and data latch logic 2506 , When a new transaction, initiated on the PCI bus, is scheduled for the QPIF, it represents the slave state machine 2502 an address phase lock signal (reg_latch_first_request) indicating that the address phase information should be latched by the PCI bus. On the next falling edge of the PCI clock signal, the establishment of the reg_latch_first_request signal causes a delayed address phase lock signal (dly_reg_latch_first_request) to be asserted. When both the original and delayed address phase lock signals are asserted, the lock logic generates 2506 a first latch signal (latch1). A flip-flop 2508 and a gate 2510 are arranged to generate the first locking signal in this manner.

The locking logic 2506 loads the address phase information from the PCI bus (via the PCI interface) into three address phase registers when the first lock signal is asserted. The first register is a thirty-bit address register 2512 indicating the start address of the current transaction. When the first lock signal is asserted, the address signal from the PCI interface (p2q_ad [31: 2]) becomes the address register 2512 invited. The address register 2512 outputs the address signal used by the QPIF (q2pif_addr [31: 2]). The second register is a four-bit command register 2514 which receives the PCI command code from the PCI bus (p2q_cmd [3: 0]) and outputs the QPIF command signal (q2pif_cmd [3: 0]). The third register is a three-bit slot select register 2516 receiving the p2q_slot [2: 0] signal indicating which PCI device is the current bus master and outputting the QPIF slot select signal (q2pif_slot [2: 0]).

When the address phase of the PCI transaction ends, the slave state machine stops 2502 a data phase lock signal (reg_latch_second_request) indicating that the data phase information should be latched by the PCI bus. On the next falling edge of the PCI clock signal, the established reg_latch_first_request signal causes a delayed data phase lock signal (dly_reg_latch_second_request) to be asserted. When both the original and delayed data phase lock signals are asserted, the lock logic is generated 2506 a second latch signal (latch2). A flip-flop 2518 and a gate 2520 are arranged to generate the second latch signal in this manner.

The locking logic 2506 then loads the data phase information from the PCI bus (via the PCI interface) into three data phase registers when the second lock signal is asserted. The first data phase register is a thirty-two bit data register 2522 which receives the data associated with the current transaction on the PCI address / data lines (p2q_ad [31: 0]) and outputs the QPIF data signal (q2pif_data [31: 0]) , The second data phase register is a four-bit enable register 2524 which receives enable bits from the PCI bus (p2q_cbe [3: 0]) and outputs the QPIF byte enable signal (qq2pif_byte_en [3: 0]). The third register is a three-bit latch register 2526 receiving the PCI lock signal (p2q_lock) indicating that the current transaction should run as a locked transaction and issuing the QPIF lock signal (q2pif_lock).

How the turn 75 and also the 77 show, the QPIF comprises a "lock" logic block 2528 controlling the "lock" state of the QPIF The QPIF has three lock states: an unlocked state 2530 (lock_state [1: 0] = "00") indicating that no locked transactions are pending in the DCQ; a locked state 2532 (lock_state [1: 0] = "01") indicating that a locked transaction has been received in the DCQ or is in completion on the PCI bus, and an unlocked-but-retry state 2534 (lock_state [1: 0] = "10") indicating that the lock has been removed, but a posted memory write transaction pending in the other bridge chip must be in progress before the next transaction is accepted can be.

During a power-up or a reset and a reset occurs the interlock logic 2528 in the unlocked state 2530 and waits for a locked transaction to enter the DCQ (indicated by the placement of the dcq_locked signal). At the first clock pulse, after the dcq_locked signal is asserted, the latch logic enters the locked state 2532 one, which is the QPIF slave state machine 2502 to retry all transaction requests from the PCI bus. The PCI interface also sets a lock signal (p2q_lock) indicating that it has latched the PCI bus for the transaction. After the lock transaction is completed and the requesting device has retrieved the locked completion data from the DCQ, the dcq_locked signal is removed. At the first clock pulse, after the dcq_locked is removed while the p2q_lock signal is still asserted, if no posted memory writes are pending in the other bridge chip (ie, the pmw_empty signal is asserted by the cable decoder), it will turn the lock logic 2528 to the unlocked state 2530 back and the slave state machine 2502 is again able to accept transaction requests. However, if the pwm_empty signal is not asserted at the first clock pulse after the dcq_lock signal is removed, the latch logic occurs 2528 in the unlocked-but-retry state 2534 one, the slave state machine 2502 causes it to retry all transactions until the posted memory write cycle on the other PCI bus is completed.

After the posted memory write cycle is completed, the pmw_empty signal is asserted, and the latch logic 2528 returns to the unlocked state 2530 back.

How the turn 75 and also the 78 show, the QPIF comprises a buffer flush logic 2536 that determines when the DCQ should dump data from one or all of its data buffers. As discussed above, the PCI interface in the output side chip generates a p2q_flush signal when the input side chip issues an I / O or config write or a memory write that is the target memory range register TMRR) of an output-side device. The QPIF buffer flush logic 2536 sets a QPIF flush signal (general_flush) which dumps the corresponding data buffer or all data buffers (depending on the value of the p2q_slot signal, as discussed above) when the p2q_flush signal is received. Otherwise, the buffer flush logic 2536 the general flush signal only when a device on the secondary bus issues a delayed request that misses all of the DCQ buffers when checked by the DCQ control logic (ie! dcq_hit and q2pif_check_cyc are asserted). In either case, the general_flush signal is used to empty only buffers that are in the "prefetch" state, as discussed above Therefore, prefetch data is held in the DCQ until the PCI interface requires a flush or until the corresponding PCI device issues a non-sequential request (ie, misses the DCQ) 2538 and 2540 are arranged to generate the general_flush signal in this way.

If a multi-threaded device more than a completion buffer at least one of which has prefetch data contains remain the prefetch data in the appropriate buffer as long as the device is not Issue a request that misses all the DCQ buffers. As soon as the device issues a new request, all of them Prefetch buffer emptied. Alternatively, a prefetch buffer could be allocated a multi-threaded device, be emptied as soon as the device Issue a request that hits another DCQ buffer.

Like again 75 shows, the QPIF comprises a read command logic block 2542 which receives read commands from the PCI interface and prefetches commands from the DCQ and supplies an outbound message command signal (message_cmd) to the cable. In non-streaming situations, the outbound message command may be the same as the command received from the PCI bus or the DCQ, or the read command logic 2542 can turn the command into one that uses a larger amount of data. Because transactions, executed dword-by-dword, take longer to complete on the host bus than transactions that use an entire cache line of data, and because individual cache line transactions take longer to complete on the host bus. Bus to complete, as multiple cache line transactions, the read command logic often supports "smaller" commands to "larger" ones to reduce the number of clock cycles consumed by the transaction ("read promotion"). For example, if a device on the secondary PCI bus issues a memory read command and then polls for each dword of data in a cache line, the read command logic is 2542 being able to reduce the host latency by supporting the PCI command to a memory read line, which allows the input side chip to read the entire cache line of data at once instead of individually reading each dword.

As well as 79 If the DCQ indicates that a read data string has been established (ie, dcq_stream_connect is asserted), then, as discussed above, the read command logic generates 2542 a message command of "1000" informing the input side chip that a sequence of data is occurring If no sequence of data has been established, the read command logic must 2542 decide whether to send a memory read, a memory read line or a memory read multiple command. If the command received from the PCI bus is a memory read (MR) command (q2p_CMD [2: 0] corresponds to "0110") and the corresponding memory read-to-memory read line support Bit (cfg2q_mr2mr1) is set in the configuration registers, generates the read command logic 2542 On the other hand, if the PCI instruction is a memory read instruction, and the corresponding memory read-to-memory read multiple bit (cfg2q_mr2mrm) is set, a memory read line instruction ("1110") is set or if the instruction is a memory read line instruction (q2pif_cmd [3: 0] equal to "1110") from the PCI bus or a prefetch line instruction (dcq_prefetch_line is asserted) from the DCQ and the corresponding memory read row to memory multiple bit (cfg2q_mrl2mrm) is set, or if the instruction is a prefetch multiple instruction (dcq_prefetch_mu1) from the DCQ, the read instruction logic 2542 a memory read multiple command (ie message_cmd corresponds to "1100"). If the command is a prefetch line command and the corresponding memory read line to memory read multiple bit is not set, it will generate the read command logic 2542 an MRL command ("1110"). Otherwise, the read command logic gives 2542 the received PCI command (q2pif_cmd [2: 0]) as the message command signal. Gates 2544 . 2546 . 2548 . 2550 . 2552 . 2554 . 2556 and 2558 and multiplexers 2560 . 2562 and 2564 are arranged to generate the message_cmd signal in this way.

Like again 75 2, when the QPIF is operating in master mode and has received control over the bus, to generate a transaction stored in the PMWQ Write command logic block 2566 the command code that runs on the PCI bus. To reduce transaction time, as discussed above, write-to-command logic may convert memory-write (MW) instructions, which translates data transmissions one dword at a time into memory-write and invalidate instructions (FIGS. MWI), which uses transfers of at least one entire cache line of data. The Write Command Logic Block 2566 can convert a command midstream, if e.g. For example, the transaction begins as a memory write in the middle of a cache line and contains data that crosses the next cache line boundary and includes all eight dwords of data in the next cache line. In this situation, the write command logic terminates 2566 the memory write transaction when it reaches the first cache line boundary and initiates a memory write and invalidates a transaction to transfer next full cache lines of data. The write command logic 2566 may also terminate an MWI transaction midstream in favor of a MW transaction if less than one cache line of data is to be written to the target bus after a cache line boundary is crossed.

Like again 75 and also 80 show, holding the slave state machine 2502 also maintains two counters indicating when a posted write transaction initiated on the PCI bus should be terminated. A 4K page limit counter (Page Boundary Counter) 2594 generates a page count signal (page_count_reg [11: 2]) which indicates when data transferred from the PCI bus reaches a 4K page boundary. Since a single memory access is not allowed to cross a 4K page boundary, the posted write transaction on the initiating bus must be terminated when a limit is reached. The 4K page limit counter 2594 is loaded with the third to twelfth bits of the transaction address (q2pif_addr [11: 2]) when the state machine asserts a load_write_counter signal (the circumstances involving a listing of this signal will be discussed in further detail below ). The counter 2594 then increases by one on the rising edge of each clock pulse after the load_write_counter signal is removed. The counter 2594 is not increased at clock pulses during which the initiating device has initiated an initiator wait state (ie, p2q_irdy set up). The output of gate 2592 determines when the counter is allowed to increase. If all the bits in the page_count_reg [11: 2] signal are high, a 4K page boundary has been reached and the slave state machine must terminate the posted write transaction and retry the initiating device.

A dword counter 2598 generates a pmw_counter [5: 0] signal indicating the number of dwords written by the initiating bus during a posted write transaction. The pmw_counter [5: 0] signal is then used to indicate when an overflow has occurred or when the last line of the transaction has been reached, as discussed below. When the slave state machine 2503 When the load_write_counter signal is asserted, the third to fifth bits of the address signal (q2pif_addr [4: 2]) become the lower three bits of the counter 2598 while the upper three bits are set to zero. This address offset indicates at which dword in a cache line a posted write transaction was started. The counter 2598 then increases by one on the rising edge of each clock pulse after the load_write_counter signal is removed. The counter 2598 is not incremented at clock pulses during which the initiating device has initiated an initiator wait state (ie, p2q_irdy is asserted). The exit of the gate 2596 determines when the counter is allowed to increase. If all the bits in the pmw_counter [5L0] signal are high, the posted write has reached the end of the eighth cache line.

How the turn 81A to 81C show, the write command logic block generates 2566 a four-bit write command signal (write_cmd [3: 0]) indicating the instruction code of the posted write transaction to be executed on the PCI bus. If the command code stored in the PMWQ represents a memory write and invalidate command (pmwq_cmd [3] = "1"), the write command logic generates 2566 a write command code of "1111." If the PMWQ command code represents a memory write command, the write command logic locks 2566 to the memory write to memory write and invalidate configuration bit (cfg2q_mw2mwi) corresponding to the target PCI slot. If the cfg2q_mw2mwi bit is not set, the write command logic generates 2566 a store write command ("0111"). If the configuration bit is set, the write command logic generates 2566 an MWI instruction if the next row in the PMWQ data buffer is full (pmwg_full_line is asserted) and otherwise generates a MW instruction. The multiplexers 2568 and 2570 are arranged to generate the write_cmd signal in this manner.

When the QPIF executes a transaction on the PCI bus and has reached a cache line limit, the write command logic may 2566 Set up a new_write_cmd signal indicating that the current transaction must be terminated in favor of a new write command. If the transaction is the last has reached the cache line in the PMWQ data buffer (ie, pmwq_pointer [5: 3] corresponds to "111"), the new_write command signal is asserted to indicate that the transaction should be terminated if the next PMWQ transaction is completed. Buffer is not an overflow buffer containing valid data if the corresponding cfg2q_mw2mwi bit is not set, or if the full line bits corresponding to the current cache line and the next cache line are different (ie, pmwq_full_line [7] does not match pmwq_next_full_line). If the transaction has not reached the end of the PMWQ buffer, the new_write_cmd signal is asserted, either if the next line in the PMWQ buffer contains invalid data (! pmwq_valid_lines [x + 1]), or if the cdfg2q_mw2mwi Bit is set and the full-row bits are different for the current row and the next row (ie, pmwq_full_line [x] does not correspond to pmwq_full_line [x + 1]). Gates 2572 . 2474 . 2576 . 2578 and 2580 and a multiplexer 2582 are arranged to generate the new_write command signal in this manner.

After the new_write_cmd signal is asserted, the transaction is not terminated until the Write Command Logic Block 2566 sets up a synchronous new write command signal (held_new_write_cmd). The held_new_write_cmd signal is asserted on the first clock pulse after the new_write_cmd signal is asserted and the end_of_line signal is asserted, indicating that the end of the cache line has been reached as long as the PCI interface has not completed the transaction ( ie p2q_start_pulse is set up). The held_new_write command is deasserted on a reset and on the first clock pulse after the new_write_cmd, end_of-line, and p2q_start_pulse signals are cleared and the QPIF terminates the transaction (ie, the asynchronous early_cyc_complete signal is asserted). Otherwise, the held_new_write_cmd signal retains its current value. Gates 2584 and 2586 , an inverter 2588 and a flip-flop 2590 are arranged to generate the held_new_write_cmd signal in this manner.

Like again 75 and also 82A show, the QPIF comprises an overflow logic block 2600 who is the master state machine 2500 allows to manage overflow data, if any, when a posted write transaction is executed on the target bus. When the QPIF receives a transaction run signal (mca_run_pmw or mca_run_dr as discussed above) from the MCA, the overflow logic generates 2600 a two-bit initial queue select signal (start_queu_select [2: 0]), which indicates which of the buffers in the PMWQ or DRQ should be selected to run the current transaction. The following table shows how the start_queue_select signal is generated.

Erzeugung eines start_queue_select Signals

Generation of a start_queue_select signal

When the QPIF performs a posted write transaction on the target bus, a two-bit QPIF queue selection signal (q2pif_queue_select [1: 0]) is used to select the appropriate buffer in the PMWQ. When the transaction is initiated, the master state machine stops 2500 an initial_queue_select, which causes the q2pif_queue_select signal to take on the value of the initial queue select signal (start_queue_select). At the same time, a queue selection counter 2602 loaded with the value of the start_queue_select signal. After the initial_queue_select signal is removed, the q2pif_queue_select signal takes on the value of the count_queue_select signal generated by the counter 2602 , When the posted memory write transaction overflows into the next PMWQ buffer, the master state machine stops 2500 an increase queue selection signal (inc_queue_select), which causes the counter 2602 increased by one. As a result, the q2pif_select_signal is incremented and the next buffer in the PMWQ is selected to continue the transaction. A multiplexer 2604 determines the value of the q2pif_queue_select signal.

As well as 82B shows, sets the overflow logic 2600 an overflow_next_queue signal on when the master state machine 2500 should continue to gather information from the next PMWQ buffer during a posted memory write transaction. Using the q2pif_queue_select [1: 0] signal to determine which PMWQ is currently selected sets the overflow logic 2600 the overflow_next_queue signal if the valid bit (pmwq_valid) and an overflow bit (pwq_overflow) are set according to the next PMWQ buffer. The pmwq_valid and the pmwq_overflow characters are discussed below. Gates 2606 . 2608 . 2610 and 2612 and a multiplexer 2614 are arranged to generate the overflow_next_queue signal in this manner.

Like again 75 shows, the QPIF comprises a read alignment logic block 2616 that allows the QPIF to correct misaligned memory read line and memory read multiple transactions. A read-line correction occurs when the QPIF, while operating in the master mode, receives a MRL or MRM transaction that begins in the middle of a cache line. To reduce transaction time, the QPIF starts the read transaction at the cache line limit and ignores the unsolicited dwords instead of individually reading only the requested dwords of data.

With reference also to 83 activates the read alignment logic 2616 the read alignment feature by setting up an align_read signal. This signal is asserted when the instruction stored in the corresponding DRQ buffer is a memory read line or a memory read multiple instruction (ie drq_cmd [3: 0] corresponds to "1110" or "1100"). each), and when the read alignment configuration bit (cfg2q_read_align) is set corresponding to the target PCI device. Gates 2618 and 2620 are arranged to generate the align_read signal in this manner.

How the turn 84A to 84C include the read alignment logic 2616 a read alignment down counter 2622 which counts the dwords from each cache line boundary and displays if the master state machine 2500 reached the first, requested dword. The counter 2622 includes a state machine 2624 indicating the operation of the meter 2622 controls.

When a reset occurs, the counter 2622 in an IDLE_CNT state 2626 one in which no count occurs. If the MCA instructs the QPIF to run a delayed request transaction on the PCI bus (ie, if any bits are placed in the mca_run_dr [3: 0]), the QPIF will issue a delayed request run signal ( any_drq_run), indicating that it is attempting to run a delayed request transaction. While the counter is in the IDLE_CNT state 2622 its three-bit output signal (throw_cnt [2: 1]) is loaded with the dword offset of the transaction address (drq_addr [4: 2]) when the any_run_drq signal is asserted and the QPIF is controlling the PCI Bus gets (ie p2q_ack is set up). The gate 2623 generates the charge enable signal. Then, at the rising edge of the next PCI clock cycle, the counter occurs 2622 in the COUNT state 2628 one. If the transaction starts at a cache line limit, the dword offset equals "000" and no count is needed. When a read alignment is activated, the master state machine starts 2500 any MRL and MRM transaction at the cache line boundary, regardless of the actual start address.

While the counter 2622 in the COUNT state 2628 It decreases by one on each clock pulse as long as the p2q_ack signal is asserted, throw_cnt has not reached zero, the transaction is in the data phase (ie the asynchronous signal eary_data_phase is asserted) and the target device did not issue a target ready wait state (! p2q_trdy). The gate 2625 determines when the counter is lowered. If the PCI interface removes the bus from the QPIF (p2q_ack is removed) or if the data phase ends (early_data_phase is removed), the counter ends 2622 a decrease and reenter the IDLE_CNT normal state 2626 one. If the throw_cnt signal reaches "000" while the p2q_ack signal is still established, the counter stops 2622 a count and enters the DONE state 2630 one. Otherwise, the counter remains in the COUNT state 2628 ,

When the counter reaches "000", the read alignment logic sets 2616 a read_data_start signal is issued to the master state machine 2500 instructed to begin reading data from the target device. A comparator 2632 generates the read_data_start signal. After the read_data_start signal on is set, the counter remains 2622 in the DONE state 2630 until the data phase ends (early_data_phase is removed).

As 85 shows, the master state machine controls the operation of the QPIF when the QPIF is operating in the master mode. In the master mode, the QPIF executes posted write transactions and delayed request transactions on the PCI bus. The following table shows the events that cause state transitions in the master state machine.

Master-Zustand-Transaktionen

Master state transactions

Upon a reset, the master state machine enters an IDLE state 2700 in which the QPIF waits for instructions to run a transaction on the PCI bus. If the QPIF is a run-Si gnal from the MCA (any_run is asserted if any bit in the mca_run_pmw signal or the mca_run_dr signal is asserted), the cable is not busy, forwarding a message (! cable_busy), and the PCI interface is not attempting the previous transaction To finish (! p2q_master_dphase), the master state machine is trying to run the transaction on the PCI bus. If the transaction is a delayed request transaction (any_run_drq is asserted) and the other chip has no space for a delayed completion (tc_dc_full is asserted), the master state machine will be unable to run the request, and Forwards the MCA to the next transaction. Otherwise, if the PCI interface has given the QPIF control of the bus (p2q_ack is set up), the master state machine will begin executing the transaction on the PCI bus. In the IDLE state 2700 The master provides the address phase information discussed above to the PCI bus. If the transaction to be run is a dual address cycle (q2pif_dac_flag is asserted), the master state machine enters a MASTER_DAC state 2702 in which the second half of the address information is delivered. If the transaction is not a dual-address cycle and is a delayed request transaction (any_run_drq is asserted), then the master state machine enters an RDATA1 read state 2704 in that the master state machine begins the data phase of the delayed request transaction. If the transaction is not a dual address cycle and is not a deferred request, it is a posted memory write transaction, so the master state machine enters a WDATA1 write state 2706 occurs by the master state machine entering the data phase of the posted memory write transaction.

In the MASTER_DAC state 2704 = 2, the master state machine supplies the second half of the address phase information. Then, if the p2q_ack signal is still asserted and the transaction is a deferred request, the master state machine enters the RDATA1 state 2704 when it receives the start signal (p2q_start_pulse) from the PCI interface. If the transaction is not a deferred request, the master state machine enters the WDATA1 state 2706 when it receives the PCI start pulse. The master state machine also initiates a delayed completion message on the cable when the PCI start pulse is received by establishing an asynchronous completion message signal (early_master_send_message). If the p2q_ack signal has been removed by the PCI interface, the master state machine returns to the IDLE state 2700 back and waiting to try the transaction again.

The RDATA1 state 2704 is the initial state for delayed read and delayed write requests. In this state, the master state machine waits for the PCI start pulse before entering an RBURST burst data phase 2708 , When the state machine first enters the RDATA1 state 2704 If so, it initiates a completion message on the cable, if not already in the MASTER_DAC state 2702 is made. Then, if the p2q_ack is taken away by the PCI interface, the master state machine completes the transaction, advances the MCA to the next transaction, and reenters the IDLE state 2700 one. Otherwise, when the PCI startup pulse appears, the master state machine prepares to enter the RBURST state 2708 enter. If the QPIF indicates the end of the transaction (queue_cyc_complete) or if the transaction has reached a 4K page boundary (read_page_disconnect is asserted because all bits in the drq_addr [11: 2] signal are high), the master state machine clears the frame_signal from the QPIF, indicating that the next part of data is the last part (asynchronous signal early_last_master data is asserted), before entering the RBURST state 2708 is entered. The master state machine also asserts an asynchronous early_master_lastline signal indicating that the last row of data has been reached, if the read_page_disconnect_lastline signal is asserted or if the DRQ load line signal (drq_lastline) is asserted and the QPIF has not received a streaming signal from the other bridge chip (cd_stream or stream_match are not set up or cfq2q_stream_disable is not set). If the PCI start pulse is not established, the master state machine remains in the RDATA1 state 2704 until the QPIF completes the transaction or a 4K page boundary is reached, causing the state machine to go to the IDLE state 2700 or until the PCI start pulse appears, causing the state machine to enter the RBURST state 2708 enter.

In the RBURST state 2708 The master state machine bursts data to the PCI bus. If a completion message has not yet been initiated, the master state machine initiates a completion message entering the RBURST state 2708 , Then, if the p2q_ack signal is removed, or if the QPIF transaction is again attempted by the PCI interface (p2q_retry is asserted), or if the PCI interface discards the transaction (p2q_target_abort is asserted), then the master state terminates. Machine the transaction on the PCI bus, discard the completion message on the cable and return to the IDLE state. If the p2q_ack signal is gone is taken, the master cycle arbitrator continues to select the current transaction. However, if the transaction is retrieved or discarded, the master state machine continues the MCA to the next transaction.

While the p2q_ack signal is still asserted and the QPIF transaction is not retried or discarded, the master state machine never quits the transaction and returns to the IDLE state 2700 back if a 4K page boundary is reached and the PCI interface indicates that the target device has stopped recording data (p2q_trdy is no longer mounted). If the target device takes the last part of data, the state machine remains in the RBURST state 2708 ,

If the QPIF asserts the queue_cyc_complete signal, indicating that the transaction is complete, the master will generally terminate the transaction and return to the IDLE state 2700 return if the p2q_trdy signal is removed or in the RBURST state 2708 remains until the last dword is transferred to data if the p2q_trdy signal remains asserted. However, if the transaction is in the data phase and is not in the last data phase (p2q_master_dphase and! P2q_last_dphase) and a data string has been established with the other bridge chip (cd_stream and stream_match and! Cfg2q_stream_disable), the Master state machine indefinitely in the RBURST phase. When the QPIF is in a streaming operation, the master state machine sets up a streaming signal (q2pif_streaming) that causes the QPIF to continue to supply data to the requesting device on the other PCI bus until the device ends the transaction.

If the p2q_ack signal remains set up and neither the p2q_retry, p2q_target_abort, or queue_cyc_complete signal is asserted, the master state machine looks for the p2q_trdy signal. If the signal is not asserted, indicating that the target device has taken or delivered the last piece of data, the master state machine sets its next data signal (early_next_data) indicating that the QPIF is ready to transfer another part of data. The next data signal is asserted only if the transaction is not a correct read (align_read is not set up) or if the transaction is a correct read and the read_data_start signal has been asserted. If the p2q_trdy signal is asserted, indicating that the target has not performed the last data transfer, the state machine remains in the RBURST state 2708 ,

In the WDATA1 state 2706 The master state machine begins the data phase of a posted memory write transaction. If the p2q_ack signal is removed or the p2q_retry or p2q_target_abort signal is asserted while the master state machine is in this state, the transaction on the PCI bus is terminated and the state machine returns to the IDLE state 2700 back. When the p2q_ack signal is removed, the MCA remains at the current cycle; otherwise, the master state machine progressively advances the MCA to the next transaction.

If the p2q_ack signal remains asserted and the transaction is neither retrieved nor discarded, the master state machine must determine whether the write is using a single dword or more than one dword. If the queue_cyc_complete signal is asserted in the WDATA1 state, the new hold-write command signal is asserted, the end_of_line and new_write_cmd signals are asserted, or the transaction has reached the last dword of data, the transaction inserts a single dword. In this situation, the transaction ends and the state machine returns to the IDLE state 2700 only back if the target took the last part of data (! p2q_trdy). Otherwise, the state machine remains in the WDATA2 state 2710 , If the transaction uses more than one dword of data, the master state machine enters a WDATA2 burst data phase state 2710 one. Immediately before entering the WDATA2 state, the master state machine enters a q2p_irdy wait state if the overflow_next_queue signal has been asserted.

In the WDATA2 state 2710 The master state machine forwards the data bursty to the PCI bus. If the p2q_ack signal is taken away or the transaction is discarded by the PCI interface, the transaction in the QPIF is terminated and the master state machine reenters the IDLE state 2710 one. If the transaction is again attempted by the PCI interface, but the PCI interface took the data that has been delivered (! P2q_trdy), the master state machine again enters the IDLE state 2700 one. Otherwise, the state machine enters a WRETRY stepback state 2712 one leading the PMWQ out of the pointer back to the previous part of data by generating the return signal discussed above. From the WRETRY state 2712 the state machine repeatedly enters the IDLE state 2700 one.

If the p2q_ack signal remains asserted and the transaction is neither retried nor discarded, the master state machine determines whether the transaction is complete. If the QPIF indicates the end of the transaction (queue_cyc_complete is asserted) or the end of a cache line is reached and a new write command is needed (end_of_line and new_write_command are asserted), the state machine enters a WSHORT_BURST state 2714 if either the last part of the data was taken (! p2q_trdy) or the PCI start pulse is received. In any case, only two dwords of data have to be written to the PCI bus. Otherwise, the state machine remains in the WDATA2 state 2710 , When the state machine enters the WSHORT_BURST state 2714 occurs, the QPIF frame_signal remains asserted if the transaction may overflow into the next queue, and a new write command is not needed.

In the WSHORT_BURST state 2714 The master state machine prepares to write the final two dwords data to the PCI bus. If the p2q_ack signal is removed or the cycle is retried or discarded by the PCI interface, the state machine ends the transaction and returns to the IDLE state 2700 back. When the PCI aware signal disappears or the cycle is discarded, the master state machine sets the stepback signal to indicate that the PMWQ out pointer should be stepped back to the previous dword. If the transaction is again attempted by the PCI interface, the out pointer will only be paced backwards if the target device did not take the last part of data (p2q_trdy is set up). If the transaction is not completed and it can overflow into the next PMWQ buffer (overflow_next_cueue is asserted) and a new write command is not needed, the master state machine retains the QPIF frame signal that is asserted , and then enters a WCOMPLETE state 2716 if the target device took the last part of data or in the WSHORT_BURST state 2714 has, or otherwise remains in the WSHORT-BURST state 2714 , If the transaction can not overflow into the next queue or a new write command is needed, the state machine removes the frame signal to indicate the end of the QPIF transaction and then enters the WCOMPLETE state 2716 if the last part of data has been taken by the target device or remains in the WSHORT_BURST state 2714 otherwise.

In the WCOMPLETE state 2716 the master state machine terminates the posted memory write transaction. The state machine enters the IDLE state 2700 when the transaction is retried or discarded by the PCI interface. If the transaction is retried, the PMWQ Out pointer is incremented only if the target device took the last part of data. If the transaction can overflow to the next queue, a new write command is not needed, and the transaction is not in the last data phase, the master state machine increments the queue selection counter and returns to WDATA1 Status 2706 to continue the transaction from the overflow queue as long as the target device took the last part of data. If the target device did not take the last part of data, the master state machine remains in the WCOMPLETE state 2716 ,

If the transaction does not overflow into the next PMWQ buffer, the master state machine terminates the transaction and returns to the IDLE state 2700 back if the target took the last part of data. Otherwise, the state machine remains in the WCOMPLETE state 2716 until one of the terminating events discussed above occurs.

As the 86 shows, the slave state machine controls the operation of the QPIF when the QPIF is operating in the slave mode. In the slave mode, the QPIF receives posted write transactions and delayed request transactions from devices on the PCI bus and routes the transactions on to the target bus via the cable. The following table shows the events that cause state transitions in the slave state machine.

Slave-Zustand-Übergänge

Slave state transitions

Upon a reset, the slave state machine enters an IDLE state 2720 in which the QPIF is waiting for a transaction to be initiated by a device on the PCI bus. If a transaction initiated on the bus does not hit the QPIF as a destination (q2p_qcyc is not set up), the slave state machine goes into the IDLE state 2720 continued. If a transaction on the PCI bus does not hit the QPIF as a destination, the slave state machine enters a SLAVE_DAC dual address cycle state 2722 if the p2q_dac_flag is set up and an address parity error has not occurred (p2q_lock_ is low). If the transaction is not a dual-address cycle and is a posted memory write request, and if a parity error has not occurred in the address phase, the slave state machine loads the write counters (ie load_write_counter) and determines if it can accept the transaction. If the PMWQ in the other bridge chip is full (tc_dc_full is asserted by the DC transaction counter) or the DCQ is latched (dcq_locked is asserted) or the QPIF latch logic is in the unlocked-but-retry state (lock_state [1] equals "1"), then the slave state machine completes the transaction by asserting an asynchronous retry signal (early_retry), which is supplied to the PCI interface as q2pif_retry, and remains in the IDLE state 2720 , If the QPIF can accept the transaction, the slave state machine initiates the posted memory write message on the cable and enters a PMW1 state 2724 one in which the transaction continues to the cable.

If the transaction is not a dual address cycle or a posted memory write request If no, the slave state machine loads the dword counter (sets load_write_counter) and, if a parity error has not occurred, parses the delayed request transaction. If the transaction is a MRL or an MRM transaction and the QPIF lock logic is not in the unlocked-but-retry state, the slave state machine sets the QPIF verify cycle signal (q2pif_check_cyc) What the DCQ instructs to compare the locked request to the delayed completion messages in the DCQ buffers. If the request encounters a DCQ buffer that is not empty (dcq_hit and! Dcq_no_data), the slave state machine enters a STEP_AHEAD state 2726 in which the QPIF begins to supply the requested information to the PCI bus. If the MRL or MRM request misses all the DCQ data buffers (! Dcq_hit), the DCQ is not full (! Dcq_full), the delayed request queue in the other bridge chip is not full (! Tc_dr_full) and the DCQ and QPIF are not latched (! dcq_locked and! lock_state [1]), the slave state machine sets the q2pif_retry signal, passes the request on to the cable, and remains in the IDLE state 2720 , If the request misses the DCQ and the request can not be sent along the cable, the QPIF simply retries the requesting device and remains in the IDLE state 2720 ,

If the deferred request is not an MRL or MRM transaction, a second clock cycle is needed to verify the request, since the data or byte enables must be compared with the contents of the DCQ buffers so that the Slave state machine in a SECOND_CHECK state 2728 entry. If a parity error occurs or if the lock logic is in the unlocked-but-retry state, the state machine again attempts the requesting device and remains in the IDLE state 2720 ,

In the SLAVE_DAC state 2722 The slave state machine receives the second half of the address phase information. If the requesting device did not target the QPIF, the slave state machine ignores the transaction and remains in the IDLE state 2720 , If the QPIF is the target device, the state transition events are the same as those in the IDLE state 2720 , More specifically, if the transaction is a posted memory write request and a parity error has not occurred, the slave state machine loads the write counters and determines whether it can accept the transaction. If the PMWQ in the other bridge chip is full (tc_pmw_full is asserted), the DCQ is latched or the QPIF latch logic is in the unlocked-but-retry state, the slave state machine retries the requesting one Device and returns to the IDLE state 2720 back. If the QPIF can accept the transaction, the slave state machine initiates the posted memory write message on the cable and enters the PMW1 state 2724 one.

If the transaction is not a posted memory write request, the slave state machine loads the dword counter and, if no parity error has occurred, analyzes the delayed request transaction. If the transaction is a MRL or MRM transaction and the QPIF lock logic is not in the unlocked-but-retry state, the slave state machine sets the QPIF check cycle signal. If the request encounters a DCQ buffer that is not empty, the slave state machine enters the STEP_ADHEAD state 2726 one. If the MRL or MRM request misses all the DCQ data buffers, the DCQ is not full, the delayed request queue in the other bridge chip is not full (tc_dr_full is not set up) and the DCQ and QPIF are not locked, the slave state machine sets the q2pif_retry signal, continues the request along the cable, and returns to the IDLE state 2720 back. If the request misses the DCQ and the request can not be sent along the cable, the QPIF simply retries the requesting device and returns to the IDLE state 2720 back.

If the deferred request is not an MRL or MRM transaction, a second clock cycle is needed to verify the request, since the data or byte enables must be compared with the contents of the DCQ buffers so that the Slave state machine in the SECOND_CHECK state 2728 entry. If a parity error occurs or if the lock logic is in the unlocked-but-retry state, the state machine again tries the requesting device and returns to the IDLE state 2720 back.

In the PMW1 state 2724 the slave state machine passes a posted memory write transaction over the cable to the target device. When the state machine first enters the PMW1 state 2724 it takes away the load_write_counter signal. If the dword counter indicates that the posted memory write transaction is the last cache line (pmw_counter [5: 3] equals "111") and the PMWQ in the other bridge is full (tc_pmw_full) and the write overflow Feature is locked (! Cfg2q_write_overflow), or if the write_page_disconnect signal is asserted because the trans action has reached a 4K page boundary, or if the DCQ has asserted the dcq_disconnect_for_stream signal and the write interrupt feature is not disabled (! cfg2q_wr_discnt_disable), the slave state machine will assert the slave_lastline signal indicating that the current cache line will be the last one to be transferred. The slave state machine then remains in the PMW1 state 2724 until the p2q_qcyc signal is removed, indicating that the transaction was completed on the PCI bus. After leaving the PMW1 state 2724 , the slave state machine returns to the IDLE state 2720 one.

In the SECOND_CHECK state 2728 the slave state machine has had the DCQ compare the second phase of the request information to the delayed completion information in the DCQ buffers. If the transaction is not a deferred write request (! Io_write and! Config_write) or there is a parity error (! P2q_lock) and if the dcr is not latched and the dwr_check_ok signal is asserted, the slave state machine will the q2pif_check_cyc on. The dwr_check_ok signal is asserted either when the transaction is not a delayed write request or when it is a delayed write request and a p2q_irdy wait state has not been set. If the request hits one of the DCQ buffers and the buffer is not empty, the slave state machine enters the STEP_AHEAD state 2726 one. If the request misses all of the DCQ buffers, but the QPIF can send the message along the cable, the slave state machine retries the requesting device, continues the transaction along the cable, and reenters the IDLE state 2720 one. Otherwise, if the request missed all of the DCQ buffers and the QPIF could not send the transaction along the cable, or if a parity error occurs on a delayed write request, the state machine will retry and retry the requesting device in the IDLE state 2720 enter.

In the STEP_AHEAD state 2726 the slave state machine increments the DCQ output pointer to the next dword. This condition is necessary immediately after a DCQ buffer is hit because the PCI interface latches the first dword of data without accessing the! P2q_trdy signal. From the STEP_AHEAD state 2726 the state_machine enters a HIT_DCQ state 2730 in which data is supplied from the appropriate DCQ buffer to the requesting device if the last dword of data has not been taken. Otherwise, the state machine enters a HIT_DCQ_FINAL state 2732 in which the requesting device is retried because the DCQ buffer contains no further data.

From the HIT_DCQ state 2730 when the delayed request transaction ends on the PCI bus before it ends in the QPIF (ie, p2q_qcyc is removed), the state machine ends the transaction in the QPIF and sets the step back signal indicating that the DCQ out pointer should be decreased since the last piece of data was not taken by the requesting device. The state machine then enters the IDLE state again 2720 one. If the out-of-data DCQ buffer is running while the requesting device continues to request it (dcq_no_data and! P2q_irdy), or if the pmw_counter indicates that the last dword has been reached and the read_disconnect_for_stream signal has been asserted, the slave state machine again tries the requesting device and enters the HIT_DCQ_FINAL state 2732 one. If the transaction ends to establish a data sequence, the stepback signal is asserted and the output pointer of the appropriate DCQ buffer is decremented. In any other situation, the slave state machine continues to drive data in the HIT_DCQ_FINAL state 2732 provided.

In the HIT_DCQ_FINAL state 2732 the slave state machine has a dword of data left to transfer it. If the PCI bus completes the transaction before the requesting device takes the last portion of data (ie, p2q_qcyc is removed), the slave state machine resets the stepback signal and returns to the IDLE state 2720 back. If the p2q_qcyc signal remains stalled and the requesting device has not set an initiator wait state (! P2q_irdy), the requesting device is retried because the last piece of data has been taken. The state machine then enters the IDLE state again 2720 one. Otherwise, the slave state machine remains in the HIT_DCQ_FINAL state 2732 ,

As the 87 1, the cable message generator is a state machine that generates cable messages of transaction information obtained from the master and slave state machines. In addition to an IDLE state 2740 The message generator also includes a dual address cycle (CABLE_DAC) state 2742 , a master data phase (MASTER_DPHASE) state 2744 and a slave data phase (SLAVE_DPHASE) state 2746 , The following table represents the events that Zu to create state transitions in the cable message generator.

Kabel-Nachrichten-Generator-Zustand-Übergänge

Cable message generator state transitions

Upon a reset, the cable news generator enters the IDLE state 2740 one in which it waits for transaction information to arrive from the master or slave state machine. From the IDLE state 2740 If the cable message generator receives a prefetch multiple signal (dcq_prefetch_mul) or a prefetch line signal (dcq_prefetch_line), the cable address signal (early_cad [31: 2]) corresponds to the prefetch address signal (dcq_prefetch_addr [31: 2]). Otherwise, the early_cad [31: 2] signal will take on the value of the QPIF address signal (q2pif_addr [31: 2]). When the cable message is initiated by the master state machine, the message is a delayed completion message such that the command code (early_ccbe [3: 0]) corresponds to "1001." If the cable message is terminated by the Slave state machine is initiated, the command code assumes the value of the message_cmd [3: 0] signal as discussed above.

If the send_message signal is set up, indicating that either the master state machine or the slave state machine one Message has initiated, and the corresponding transaction is not is a dual address cycle, or if the cable message generator receives a prefetch request that not a dual-address cycle or if the cable news generator receives a data stream connection signal and no delay Requests from the CPU are pending in the output DRQ, the cable message generator sets a sent_pmw signal indicating a posted memory write request from the PCI bus will be sent along the cable. The sent_pmw Signal is not asserted if a stream of data passes through the DCQ has been set up. The cable news generator puts a sent_dr signal when a read request or a delayed write request from the Slave state machine is received or receive a prefetch signal is, and if a sequence of data has not been established by the DCQ is.

If the DCQ has established a data stream (dcq_stream_connect is asserted), the buffer count for the cable signal (early_cbuff [2: 0]) assumes the value of the DCQ stream buffer (dcq_stream_buff [2: 0]), the cable Command code (early_ccbe [3: 0]) is set equal to "1000", and the cable message generator enters the SLAVE_DPHASE state 2746 one. Otherwise, if the QPIF is in slave mode and the cable message generator receives either a prefetch multiple or a prefetch line signal, the cable buffer signal takes the value of the DCQ buffer number (dcq_buff [2: 0]) and the cable message generator enters the SLAVE_DPHASE state 2746 one. Otherwise, the QPIF operates in master mode and the cable message generator enters the MASTER_DPHASE state 2744 one.

If the cable message generator receives the send_message signal and a transaction that is a dual address cycle, or if it receives a prefetch request that is a dual address cycle, the message generator enters CABLE_DAC state 2742 one. For a prefetch signal, the cable address signal is set equal to the upper thirty-two bits of the dcq_prefetch_addr [63: 0] signal; otherwise, the cable address corresponds to the upper thirty-two bits of the q2pif_addr [63: 0] signal. Also, if the cable message generator receives the transaction from the slave state machine, the cable buffer number corresponds to the DCQ buffer number; otherwise, the cable buffer number equals the DRQ buffer number (no completion messages are generated for posted memory write transactions).

In the CABLE_DAC state 2742 The cable message decoder generates the second half of the address phase information. As in the IDLE state 2740 the cable address signal assumes the value of the prefetch address if the received transaction is a prefetch line or prefetch multiple request, and otherwise assumes the value of q2pif_addr [31: 2]. The sent_pmw signal is asserted when the message generator receives a posted memory write transaction from the slave state machine, and the sent_dr signal is asserted if it receives a prefetch request or a delayed request from the slave device. State Machine receives. If a prefetch request or request is received from the slave state machine, the cable message generator enters the SLAVE_DPHASE state 2746 one. Otherwise, the message generator enters the MASTER_DPHASE state 2744 one.

In the MASTER_DPHASE state 2744 The cable message generator attempts to send a delayed completion message along the cable. However, if the PCI interface issues the bus to a device on the PCI bus before the QPIF gets control of the bus, the cable message generator must have the MASTER_DPHASE state 2744 leave to send the newly received message. Therefore, if the send_message signal is asserted, while the message generator is in the MASTER_DPHASE state 2744 placed the q2c_new_req signal to indicate the start of a new message. If the q2pif_dac_flag is asserted, the new transaction is a dual address cycle and the cable message generator enters the CABLE_DAC state 2742 one. Otherwise, the message generator enters the SLAVE_DPHASE state 2746 one.

If the send_message signal is not established, the cable message generator will send a delayed completion message from the master state machine. If the master state machine has completed the last data transfer with the PCI bus and the target device has acknowledged the transfer (! P2q_trdy), or if the master has discarded the transaction on the cable, the cable messages Generator sends a sent_dc signal indicating that the delayed completion message has been sent along the cable and reenters the IDLE state 2740 one. Otherwise, the message generator remains in the MASTER_DPHASE state 2744 and continues to generate the delayed completion message.

From the SLAVE_DPHASE state 2746 For example, as long as a data string is established with the upstream chip, no delayed requests from the CPU in the downstream DRQ are pending, and the requesting device continues to send data to the QPIF (q2p_qcyc is asserted), the cable news generator remains in the SLAVE_DPHASE state 2746 and continues to continue the transaction from the requesting device. Otherwise, if the cable message generator receives a delayed request or prefetch request, the cable message generator will pass the request, and in the case of a delayed write request, the dword of data to the input side device Next, and then enters the IDLE state 2740 one. Otherwise, the cable message generator has received a posted memory write request. In this situation, the cable message generator remains in the SLAVE_DPHASE state 2746 and continues to continue the posted memory write information along the cable until the early_last_slave_data signal is asserted is, which indicates that the last piece of data has been sent by the slave state machine. The message generator then terminates the cable transaction and reenters the IDLE state 2740 one.

CABLE INTERFACE

To ensure the valid transfer of data between the two bridge chips, data must be sent through the cable 28 , suitable for the clocks of the clock generators 102 and 122 be synchronized. The output side clock generator 122 sets its clocks based on an input clock (which in turn is based on the PCI bus clock PCICLK1) transmitted along the cable 28 with the data. As a result, input side data transferred to the output side are synchronized to the clocks generated in the output side bridge chip 48 , However, the phase delay is associated with the cable 28 , between the main clocks, generated in the input side chip 26 , and the data, transmitted back on the input side of the output side chip 48 , unknown. The length of the cable 28 ranges from 10 to 100 feet (if a suitable interface technology is used). The receiving logic in the input-side cable interface 104 is effectively an asynchronous limit with respect to the input clock. Consequently, the receiving logic has to input-side to output-side data to the clock from the input-side clock generator 102 resynchronize.

In 5 now the clock distribution scheme is shown in the 2-chip in the 2-chip PCI-PCI bridge. Transactions moving forward between the bridge chips 46 and 48 are encoded into multiple, time-multiplexed messages. The format of the messages is similar to the PCI transaction format (with the exception of time multiplexing) and includes an address and one or more data phases and modified handshake signals in addition to the signals added to a buffer Number and special bridge function commands. Every cable interface 104 or 130 includes a master cable interface ( 192 or 194 ) and a slave cable interface ( 196 or 198 ). The master cable interface 192 or 194 transfers messages to the cable 28 and the slave cable interface 196 or 198 receives messages from the cable 28 ,

The clock generator 102 or 122 in each bridge chip comprises two on-chip PLLs for clock generation. A PLL 184 in the input side bridge chip 26 locks on the primary PCI bus input clock PCICLK1. In the output side bridge chip 48 the PLL locks 180 on an incoming clock PCICLK2 from a clock buffer 181 ,

In the following description, a "1X clock" refers to a clock having the same frequency as the clock PCICLK1, while a "3X clock" refers to a clock having three times the frequency of the clock PCICLK1. A 1X clock PCLK generated by the PLL 184 or 180 (in the bridge chip 26 or 48 respectively), is for the PCI bus interface logic 188 or 190 is used for the bridge chip, and the 3X clock PCLK3 is used to provide the cable message generation logic in the master cable interface 192 or 194 to run. The other PLL 186 or 182 is used to lock on a cable input clock CABLE_CLK1 (from the input side) or a CABLE_CLK2 (from the output side) and to generate a 1X clock CCLK and a 3X clock CCLK3 to detect incoming cable data. The clock outputs of the PLL 186 and 182 become the slave cable interface 196 and 198 each continued.

The PLLs are arranged in the layout so as to keep the 1X and 3X bars close as possible balance to minimize the shift therebetween.

The PLL 184 or 180 generates a phase indicator signal PCLKPHI1, which is the master cable interface 192 or 194 indicates when the first phase of data to the cable 28 should be present. On the input side, the signal PCLKPHI1 is based on the PCI clock PCICLK1; on the output side, the signal PCLKPHI1 is based on the PCI clock PCICLK2. The PLL 186 or 182 generates a phase indicator signal CCLKPHI1 based on the cable clock CABLE_CLK1 or CABLE_CLK2 to the slave cable interface 196 or 198 display when the first phase of data along the cable 28 has arrived. The PCI clock PCICLK2 for the secondary PCI bus 32 is outside of a 1X clock BUFCLK the PLL 182 in the output side bridge chip 48 generated. The clock BUFCLK controls the clock buffer 181 via a driver 179 at. The buffer 181 gives a separate clock signal to each of the six slots on the secondary PCI bus 32 as well as the clock PCICLK2, which goes back to the bus input clock to the output side bridge chip 48 to be led. By clock PCLK on clock PCICLK2 from the clock buffer 181 is based, the clock schemes of the input side and output side chips are made to appear more similar because both are based on the external bus clock.

The cable clock CABLE_CLK1 is a 33% clock cycle. The PLL 182 first converts the 33% clock cycle to a 50% clock cycle to output as BUFCLK.

The PCI Specification, Version 2.1, requires that the PCI bus clock be the must meet the following requirements: Clock cycle time greater than or equal to 30 ns; Clock high time greater than 11 ns; Clock-low-time greater than or equal to 11 ns and clock rate between 1 and 4 ns.

When the computer system is started up, the input-side chip is started up last, the input-side PLL 184 sends the clock CABLE_CLK1 (via the master interface 122 ) down along the cable 28 which then passes through the output PLL 182 and PLL 180 is locked. The output PLL 180 then sends the clock CABLE_CLK2 back on the input side, through the PLL 186 to be locked. The system is not fully operational until all four PLLs have been locked.

If the input side bridge chip 26 starts up and the output side bridge chip 48 not yet switched on, behaves the input side bridge chip 26 as a PCI-PCI bridge, with nothing to the output side bus (the cable 28 ) connected is. As a result, the input side bridge chip decreases 26 do not do any cycles until the output side bridge chip 48 is powered up or turned on and the output side PLL 186 has received a "lock" from the cable clock CABLE_CLK2.

The input side bridge chip 26 Floats all of its PCI output buffers and state machines asynchronously with setting up the PCI reset signal PCIRST1_ on the primary bus 24 , During a reset, the PLL 184 try to get a lock on the PCI bus clock PCICLK1. Since the PCI specification guarantees that the signal PCIRST1_ will remain active for at least 100 μs after the PCI bus clock becomes stable, the PLL has 184 about 100 μs to get a lock.

The output side bridge chip 48 resets all internal state machines upon detection of the PCIRST1_ signal for the primary bus. The output side bridge chip then places a slot-specific reset to each slot on the secondary PCI bus 32 as well as a reset signal PCIRST2_ for a secondary PCI bus.

As 6 shows, each PLL comprises a voltage-controlled oscillator (VCO) 200 who has an exit 201 (the 3X clock) between 75Mhz (for a 25Mhz PCI bus) and 100Mhz (for a 33Mhz PCI bus). The VCO 200 receives a reference clock 197 which is the PCI bus clock. Each PLL has a latch detection circuit 205 indicating by a lock indication bit that the PLL phase is locked to its reference accurately enough to perform its intended function.

The lock indication bits become a status register in the configuration space 105 or 125 written every bridge chips. On the output side, a power-good / lock status bit becomes the input-side bridge chip 26 transmitted to indicate that the main elements of the output side bridge chips 48 are stable (energy is stable) and the output side PLLs are locked (lock indication bits of the two PLLs are active). The lock-indicating bit is also gate-controlled with the EDC status bits so that EDC errors are not reported as such until the PLLs are locked. As a result, the bridge-chip pair may arrive at an error-free communication state without software intervention. The lock-indicating bit also provides certain diagnostic information that can distinguish between a PLL lock error and other data errors. The clock generating circuit includes a four-state machine 202 to divide by 3 divided clock (1X clock) of the VCO output 201 to create. The 1X clock will go back to the PLL on the input 203 guided.

Data gets along the cable 28 under a 3X clock (PCLK3) rate in three time-multiplexed phases to produce a 1X clock message transmission rate. As 7 shows, the circuit includes in the master cable interface 192 or 194 for disassembling and transmitting the cable message a register 204 that scans the outgoing message under a local PCLK boundary. The flip-flop 208 provides an additional zone for a hold time in the third phase of the transmitted message by holding this phase for an additional half of a PCLK. Because the output register 212 With the 3X clock PCLK3 clocked, this reduces the need for tight control over the offset between the 1X and 3X clocks. From the phase indication signal PCLKPHI1 generates a set of three flip flops 210 consecutive PHI1, PHI2 and PHI3 signals, the phases 1 . 2 and 3 each representing what in turn is a 60:20 multiplexer 206 controls. The three phases of data (LMUXMSG [19: 0], LMUXMSG [39:20], {LMUXMSG [51:40], EDC [7: 0]}) are successively entered into the register 212 multiplexed and over the cable 28 driven. The third phase of data includes error correction bits EDC [7: 0] generated by an ECC generator 206 ( 17 ), from the output bits LMUXMSG [51: 0] of the register 204 , The flip-flop 214 clocked by PCLK3 receives the PHI1 signal and clocks it out as the cable clock CABLE_CLK1 or CABLE_CLK2.

Because the master cable interface 192 or 194 is a 1X-to-3X communication interface, an ON-3X clock latency is caused resulting in a single 3X clock phase shift of the transmitting cable message from the PCI bus clock, as shown in FIG 8th is shown. In the period T0, a message A becomes the input of the register 204 and the first phase clock indicator PCLKPHI1 is set high. The signal PHI1 is set high from a previous cycle. In the period P1, the cable clock CABLE_CLK1 or CABLE_CLK2 is driven high depending on the signal PHI1, which goes too high. The PCLKPHI1 pulse causes the signal PHI2 to be pulsed high in the period T1. Next, in the period T2, the signal PHI3 is pulsed in response to the signal PHI2. In the period T3, the signal PHI1 is pulsed high in response to the signal PHI3 which is high. A message A is also in the register 204 at the rising edge of the clock PCLK in the period T3. Next, in the period T4, the signal PHI1 causes the multiplexer 206 the first phase data A1 for loading into the registor 212 selects. Next, in the period T5, the second phase data A2 is selected and entered into the register 212 invited. Then, in the period T6, the third phase data A3 becomes the register 212 invited. This process is repeated for the messages B, C, D and E in the following cycle periods.

As in 8th is shown, the cable clock CABLE_CLK has a 33% clock cycle. Alternatively, the cable clock CABLE_CLK may be designed to have an average clock cycle of 50%, which, for example, is done by sending the cable clock as 33% high - 66% low - 66% high - 33% low can. By having an average 50% clock cycle this could result in better pass characteristics in the cable 28 to lead.

As 9 shows a slave cable interface first in first out buffer (FIFO) 216 incoming data from the cable 28 and transfers the aggregated data to the queues and PCI state machines in the receiving bridge chip. The FIFO 216 is 4 entries deep, with each entry being able to hold a full cable message. The depth of the FIFO 216 allows cable data to be synchronized to the clock of the local bridge chip without losing any effective bandwidth in the cable interface. In addition, on the input side, the FIFO 216 an asynchronous boundary for the cable data coming from the output side bridge chip 48 Arrive. The FIFO 216 ensures that the cable data is properly synchronized with PCLK before being output to the rest of the chip.

The entries of the FIFO 216 are indicated by an input pointer INPTR [1: 0] from an input pointer pointer 226 selected, which is clocked by the signal CCLK3, is cleared when a signal EN_INCENT is low, and is enabled by the phase indicator CCLKPHI1. The negative edge of the 3X clock CCLK3 from the PLL 186 or 182 is used to receive incoming data from the cable 28 to lock first in a 20-bit register 218 into and then into a register 220 in, if a phase-in indication signal PHI1_DLY is established, or into a register 222 if a phase 2 indication signal PHI2_DLY is set up. The Phase 1 data, the Phase 2 data and the Phase 3 data from the registers 220 . 222 and 218 each will be in the selected input of the FIFO 216 is selected on the negative edge of CCLK3 when the PHI3_DLY phase 3 indication signal is asserted. The four sets of outputs from the FIFO 216 be through a 240: 60 multiplexer 228 received by an output pointer OUTPTR [1: 0] from an output pointer pointer 224 clocked by PCLK and cleared when a signal EN_OUTCNT is low is selected.

As the 10 2, the input pointer and output pointer pointers are running 226 and 224 continuously through the FIFO 216 what fills and empties data. The counters 226 and 224 are offset in such a way as to guarantee valid data in a location before being read out. The initialization of the pointers is different for an input side bridge chip 26 opposite an output side bridge chip 48 , due to synchronization uncertainties.

Flip-flops 236 and 238 synchronize the reset signal C_CRESET, which is synchronous with the clocks in the bridge chip, to the CLK clock limit. The EN_INCNT signal is passed through the flip-flop 238 generated. The input pointer is incremented on the rising edge of the clock CCLK3 when the first pha sen indication signal CCLKPHI1 and the signal EN_INCNT present. The output pointer is then started on a later, local PCLK clock boundary PCLK, if it can be guaranteed that the data in the FIFO 216 will be valid. The input side and output side bridge chips must handle starting the output pointer differently, since the phase relationship of the cable clock to the local clock is not for the input side bridge chip 26 is known, but for the output side bridge chip 48 is known.

In the output side bridge chip 48 For example, the phase relationship between the incoming cable clock CABLE_CLK1 and the secondary PCI bus clock PCICLK2 is known because the PCI clock PCICLK2 is generated by the cable clock. As a result, there is no synchronization penalty for the output pointer OUTPTR [1: 0] in the output side bridge chip 48 , and the output pointer may track the input pointer INPTR [1: 0] as close as possible. A flip-flop 230 , which is clocked on the negative edge of the clock PCLK, is used to cause any timing shift problems between the clock CCLK generated by the PLL 182 , and the clock PCLK generated by the PLL 180 , to avoid. Although these two clocks have identical frequencies and should be in phase with each other, there is an unknown shift between the two clocks since they are generated by two different PLLs. On the output side, the signal EN_OUTCNT is the signal EN_INCNT latched on the negative edge of the signal PCLK by the flip-flop 230 , A multiplexer 234 selects the output of the flip-flop 230 because the signal UPSTREAM_CHIP is low.

In the input side bridge chip 26 the cable interface or the cable interface is treated as completely asynchronous. The phase uncertainty is due to the unknown phase shift of the cable 28 itself. Exposing to this uncertainty leads to complete freedom in terms of the length of the cable 28 , The one thing that is known is that the clocks in the input side and output side bridge chips have the same frequency, since both have their origin in the input side PCI bus clock PCICLK1. In the input side bridge chip 26 the signal EN_OUTCNT is the signal EN_INCNT latched on the positive edge of the clock PCLK by a flip-flop 232 , The multiplexer 234 selects the output of the flip-flop 232 because the signal UPSTREAM_CHIP is high. The flip-flop 232 ensures that just for the "worst case" line clock of the cable clock CABLE_CLK2 and the local PCI clock PCLK (a complete PCLK period-phase shift) valid data in the FIFO 216 are present before the data is transferred to the rest of the chip.

As 11 shows, the cable data is through the slave cable interface 196 or 198 as three-phase, time-multiplexed, signals A1, A2 and A3; B1, B2 and B3; C1, C2 and C3; etc., received. A previous transaction is completed in periods T0, T1 and T2. Beginning in the period T3, the first phase data A1 becomes the register 218 presented and the first phase indicator CCLKPHI1 is pulsed to high. On the falling edge of CCLK3 in the period T3, the data A1 becomes the register 218 and the indication signal PHI_DLY of the local phase 1 is pulsed to high. In the period T4, on the falling edge of the clock, the data of phase 1 is A1 in the register 220 invited, the data A2 phase 2 will be in the register 218 and the PHI2_DLY indication signal of phase 2 is pulsed high. In period T5, on the falling edge of CCLK3, the phase 2 data is written to the register 222 Invited, the data A3 phase 3 will be in the register 218 and the indication signal PHI3_DLY of the phase is pulsed to high. In the period T6, the contents of the registers 220 . 222 and 218 into the selected input of the FIFO 216 invited to the next flank CCLK3. Also, in the period T6, the data B1 becomes the register 218 presented together with the indication signal CCLKPHI1. Messages B and C are in the FIFO 216 in the same way as a message A is invited in subsequent periods.

As 12 2, the input pointer INPTR [1: 0] starts at the value 0 in the period T0 on the rising edge of the clock CCLK3. Also, in a period T0, a message A is loaded into the FIFO0 on the falling edge of the clock CCLK3. In the output side bridge chip 48 the output pointer OUTPTR [1: 0] is raised to the value 0 on the next rising edge of the clock PCLK in the period T3. Also, in the period T3, the input pointer INPTR [1: 0] is incremented to the value 1 on the rising edge of the clock CCLK3, and the message B is loaded into the FIFO1 on the falling edge of CCLK3. Cable data is thus loaded into FIFO0, FIFO1, FIFO2 and FIFO3 in a circular fashion.

On the output side, if the input pointer INPTR [1: 0] in the time period T0 is 0, the output pointer OUTPTR [1: 0] is increased to 0 in the period T6, two PCLK periods after Input pointer INPTR [1: 0]. The two PCLK period delays in the output side bridge chip 26 allows the phase shift in the cable 28 any value is, which has the advantage that the cable length does not have to be of a specific, fixed value.

As 13 For example, the input and output flip flops at the cable interface are placed by the manufacturer of the chips to minimize the displacement between the cable data and the clock passed therethrough. The amount of wire between each flip-flop and the I / O is kept as consistent as possible between all the cable interface signals.

CABLE MESSAGE

Sixty bits of cable data form a message. The 60 bits are multiplexed on 20 cable lines and are transmitted every 10 ns over the cable 28 transfer. The table in 14 represents the bits and the phase of each bit is assigned. The first three columns represent the input-to-output data format, and the last three columns represent the output-to-input data transmission format. The following is a description of the signals.

EDC [7: 0]: The signals are the eight syndrome bits, used to detect and correct errors that occur when transmitting data over the cable 28 be found.

CAD [31: 0]: The signals are the 32 address or data bits.

CFRAME_: The signal is used to start and end a cable transaction to signal, similar to the PCI FRAME_ signal.

CCBE [3: 0]: The four bits form byte enables in some PCI clock phases and either a PCI command or a message code in others PCI clock phases.

CBUFF [3: 0]: In the address phase, the signals indicate a buffer number for initializing the delayed completion queue (DCQ) of the bridge chip, 148 to specify an input-side and output-side delayed read completion (DRC) and a delayed read request (DRR) transactions. After the address phase, the signals include the parity bit, a parity error indication, and the data ready signal.

COMPLETION REMOVED: The bit is used to signal that a delayed completion from the Transaction Ordering Queue (TOC) on the other side of the cable 28 has been removed.

PMW ACKNOWLEDGE: The bit is used to signal that completed a posted memory write (PMW) on the other side has been received from the Transaction Run Queue (Transaction Run Queue - TRQ) has been removed.

LOCK_: The bit is transferred to the output (but not to the input), to identify locked cycles.

SERR_: The bit is used to provide a SERR_ indication to the input side to transfer but not transmitted to the output side.

INTSYNC and INTDATA: The bits carry the eight interrupts from the output side to the input side in a serial multiplexed format. The signal INTSYNC is the synchronization signal indicating the start f0 of the interrupt sequence, and the signal INTDATA is the serial data bit. The signals INTSYNC and INTDATA are on separate lines (lines) via the cable 28 guided.

RESET SECONDARY BUS: The bit is set up when the CPU 14 to the secondary reset bit in a bridge control register in the input side bridge chip 26 writes. It causes the output side bridge chip 48 reset to a power-up state. The reset signals for the slots are also set up. The signal RESET for the secondary bus is on a separate line via the cable 28 continued.

Since the address and data in each PCI transaction are multiplexed over the same lines, each PCI transaction includes an address phase and at least one data phase (more than one for Burst transaction). The PCI specification also supports single-address transactions (one 32-bit addressing) and dual-address transactions (one 64-bit addressing).

In 15A Fig. 12 illustrates a table of what information appears on each area of the bus during addresses and data phases of the single-address transactions. For a single-address transaction, the first phase is the address phase and the second and subsequent phases are data phases. In the address phase of a delayed read / write request transaction, signals CBUFF [3: 0] indicate the DCQ buffer number to initialize the bridge chip DCQ 148 to specify input and output DRC and DRR transactions. After the address phase, the signal CBUFF [3: 0] contains the parity bit. The signals CCBE [3: 0] _ contain the PCI command in the address phase and the byte enable bits in the data phases.

For posted Memory write transactions are not the signals CBUFF [3: 0] " safe "in the address phase and contain the data-ready indication, the parity-error indication and a parity bit in the data phases.

In a delayed one Read / Write Completion Transaction Contains CBUFF Signals [3: 0] the DCQ buffer numbers in the address phase and the end completion indication, one Data Ready Indication, a Parity Error Indication and a Parity bit in the data phases. The signals CCBE [3: 0] _ contain a code the one DRC transaction in the address phase and the status bits of the DRC transaction in the data phases represent. delayed Close transactions lead return the status of the destination bus for each data phase. The Data parity bit is transferred to CCBE [3] _. Other status states will be coded to the CCBE [2: 0] _BUS, where a binary value 000 is a normal one Showing completion and a binary Value 001 indicates a target rejection condition. The addresses / data bits CAD [31: 0] are not safe "in the address phase and contain data during the data phases.

In the data sequence connection transaction contain the signals CBUFF [3: 0] a buffer number in the address phase and the signal CBUFF [2] contains the data-ready indication in the Data phases. The signals CCBE [3: 0] contain a code which is a Represents data sequence connection transaction in the address phase, and are not "safe" in the data phases. The Address Data Bits CAD [31: 0] will not be during a data sequence connection transaction used.

The table in 15B illustrates the encoding of the signals for dual address transactions. In delayed read / write request transactions, the signals CBUFF [3: 0] include a buffer number in the first and second address phases and the signal CBUFF [0 ] contains the parity bit in the data phase. The signals CCBE [3: 0] _ include a code representing a dual address cycle in the first address phase, the PCI command in the second phase, and the byte enable bits in the data phase. The signals CAD [31: 0] contain the most significant address bits in the first address phase, the least significant address bits in the second address phase, and the data bits in the data phase. In a posted dual-address memory write transaction, the signals CBUFF [3: 0] are "not safe" in the first two address phases, but the signals CBUFF [1: 0] contain the parity error indication. Bits and the parity bit in the data phases The signals CCBE [3: 0] _ contain a code representing a dual address cycle in the first address phase, the PCI command bits in the second address The signals CAD [31: 0] contain the most significant address bits in the first address phase, the remaining address bits in the second address phase, and the data Bits in the data phases.

there are three possible conditions for the Data transmission available: not last (not-last), last of a cable transmission (last-of-cable-transfer) and last of (last-of) request. The non-last state becomes by setting the CBUFF [2] bit while FRAME_ is active, what indicates that there is another word of data. The last-of-cable transmission state is displayed by setting the CBUFF [2] bit while the Signal CFRAME_ is inactive. The last-of-request condition is through Setting up the CBUFF [3] and CBUFF [2] bits while the Signal CFRAME_ is inactive.

The following four IEEE 1149.1 Boundary-Scan (JTAG) signals are in the cable 48 to effect a JTAG test chain: TCK (the test clock), TDI (test data input), TDO (test data output), and TMS (test mode selection). The optimal TRST_ is not transmitted along the cable, but TRST_ can be generated from "power-good".

The JTAG signals are sent from the system PCI connector via the input side bridge chip 26 , including JTAG Master 110 , along the cable 28 to the output side bridge chip 28 to the JTAG Master 128 Transfer what the JTAG signals to each of the six PCI slots on the secondary PCI bus 32 distributed. The return path is from the JTAG Master 128 to the cable 28 back to the input side bridge chip 26 and then to the PCI slot on the primary PCI bus 24 , The signals TDO, TCK and TMS are output side bound signals. The signal TDI is an input-side bound signal.

A type of cable 28 which can be used is a cylindrical 50 pair shielded cable designed to support a high performance parallel interface (HIPPI) standard. A second type of cable is a shielded five-pair ribbon cable. The advantages of the first are standardization, robustness and reliable, uniform manufacturing. The advantages of the second are greater mechanical flexibility, automatic connection to the connector during assembly and possibly lower costs.

The table of 16 represents some of the HIPPI cable specifications. The grounding shield is made from a wrapped aluminum tape and carries only mini DC currents due to the different type of buffers that are to be used. The method of signaling is actually differential, which provides several disadvantages, with the differential buffers being used to send signals over the cable 28 to send and receive. First, the only differential method is less expensive than fiber optics for this short distance and less complex to interface than other serial methods. Differential signaling provides substantial noise immunity for a common mode and operating range for a common mode, is available in ASICs and faster than TTL. Using twisted pair and shielding minimizes electromagnetic radiation. When low voltage oscillations are used, it minimizes energy loss.

The signaling levels selected as a target are in the IEEE Draft Standard for Low-Voltage Differential Signal (LVDS) for Scaleable Coherent Interface (SCI), Draft 1.10 (May 5, 1995).

Of the Cable Connector is an AMP metal-shell connector with 100 pins, with two rows of pins. The rows are 100 mils apart spaced and the pins are centered at 50 mils. The metal shell provides a EMI shield and gives connections to the ground path of the Cable shield to the PCB connector. The right, right-angled one PCB connector fits only to a PCI carrier. The connector is like this, that he owns a staff, between the two rows and pens runs, to dissipate electrostatic discharges from signal pins when the connector is disconnected. A pair of thumbscrews attached to The cable connector will secure the proper connector.

ERROR DETECTION AND CORRECTION

An error detection and correction (EDC) method is performed on each bridge chip to provide communication through the cable 28 to protect. Because the data is time-multiplexed into three 20-bit groups to be sent over 20 pairs of wires, each triplet is of "contiguous" bits (ie, bits that are the same wire in the cable 28 are assigned) so as to be transmitted on a single wire pair. The EDC method can correct single-bit errors and multiple-bit errors occurring in the same bit position in each of the three time-multiplexed phases. The multi-bit errors are typically associated with a hardware fault, e.g. As a broken or defective wire or a faulty pin on the bridge chips 26 . 48 ,

Twenty wire pairs of cable 28 are used for output-side communication and 20 others for input-side communication. For the remaining 10 pairs in the 50 pair HIPPI cable 28 (which passes such information as the clock signals CABLE_CLK1 and CABLE_CLK2, reset signals and the power good / PLL lock signal), error detection and correction is not performed.

The following are the background assumptions for the EDC algorithm. Most errors are single-bit errors. The likelihood of having random multi-bit errors in the same transaction is extremely far-fetched because of the cable 28 is not prone to interference from internal or external sources. Errors caused by a defective wire can cause a single bit or group of bits to be transmitted on that wire. When a hardware failure occurs, the logical state of the corresponding differential buffer is a single-validity logic state.

As 17 shows, the output signals FIFOOUT [59: 0] from the multiplexer 228 in the slave cable interface 196 or 198 to the input of a test bit generator 350 supplied, the check bits CHKBIT [7: 0] generated. The check bits are parsed according to the parity check matrix shown in 18 , in which the first row corresponds to CHKBIT [0], the second row corresponds to CHKBIT [1], etc. The bits above a row correspond to data bits FIFOOUT [0:59].

The check bits are generated by an exclusive OR of all of the data bits FIFOOUT [X] (X equals 0-59) having a value of "1" in the parity check matrix Bit CHKBIT [0] is an exclusive OR of data bits FIFOOUT [7], FIFOOUT [8], FIFOOUT [9], FIFOOUT [12], FIFOOUT [13], FIFOOUT [16], FIFOOUT [22], FIFOOUT [23], FIFOOUT [24], FIFOOUT [26], FIFOOUT [32], FIFOOUT [33], FIFOOUT [34], FIFOOUT [35], FIFOOUT [38], FIFOOUT [39], FIFOOUT [45], FIFOOUT [46], FIFOOUT [48], FIFOOUT [49], FIFOOUT [51] and FIFOOUT [52] Similarly, the check bit CHKBIT [1] is an exclusive OR of bits 0, 1, 4, 5, 9, 10, 12, 14, 15, 16, 23, 27, 35, 37, 38, 40, 43, 46, 47, 48, 50 and 53. Check bits CHKBIT [2: 7] are processed in a similar manner according to the parity check matrix of 18 generated. The parity check matrix is on the 20 subchannels or wires per time-multiplexed phase, and a probability that multiple errors in the accumulated data are attributable to a faulty subchannel or wire affecting the same data position in each time-multiplexed phase , based.

In the master cable interface 192 or 194 the check bits CHKBIT [7: 0] are supplied as error detection and correction bits EDC [7: 0] together with other cable data to error correction logic in the slave cable interface 196 or 198 to enable data errors to be detected and corrected.

The check bits CHKBIT [7: 0] become a fix-bit generator 352 fed, the fix bits FIXBIT [59: 0] according to the syndrome table, presented in 19 , generated. The check bits CHKBIT [7: 0] have 256 (2 ⁸ ) possible values. The syndrome table in 19 contains 256 possible positions. Each of the 256 positions in the syndrome table contains two entries, the first entry being the hexadecimal value of the check bits CHKBIT [7: 0] and the second entry indicating the cable data status associated with that position. Accordingly, for example, a hex value of 00 indicates a non-error state, a hex value of 01 indicates an error in a data bit 52, a hex value of 02 indicates an error in the data bit 53 , a hexadecimal value of 03 indicates an uncorrectable error (UNCER), and so on.

The EDC logic is capable of detecting up to three erroneous bits as long as these data bits are adjacent to one another, ie, associated with the same wire. Thus, for example, if the check bits CHKBIT [7: 0] contain a hexadecimal value 3D, then the data bits 3, 23 and 43 are erroneous. The cable 28 carries cable data CABLE_DATA [19: 0]. Accordingly, the data bits FIFOOUT [3], FIFOOUT [23] and FIFOOUT [43] are associated with the fourth position of the cable data, ie, CABLE_DATA [3]. The EDC method can also correct two-bit errors associated with the same cable wire. Thus, for example, a hexadecimal check bit value of OF indicates errors in data bits FIFOOUT [4] and FIFOOUT [24], both associated with CABLE_DATA [4].

The fix bit generator 352 also generates signals NCERR (non-correctable error) and CRERR (correctable error). If no error is indicated by the check bits, then the signals CRERR (Correctable Error) and NCERR (Non-Correctable Error) are both set low. In these positions in the syndrome table containing the uncorrectable state UNCER, the signal NCERR is set high and the signal CRERR is reset to low. Otherwise, where a correctable data error is indicated, the NCERR signal is pulled low and the CRERR signals are reset to high.

The lower 52 bits of the fixed bits FIXBIT [51: 0] become an input of 52 exclusive-OR gates 354 whose other input receives one of each of the lower 52 bits of the FIFO data FIFOOUT [51: 0]. The upper 8 FIFO bits FIFOOUT [59:52] associated with the error detection and correction bits EDC [7: 0] are used to generate the check bits and the syndrome bits, but do not subject to error correction. The exclusive OR gates 354 execute a bitwise exclusive OR operation of the fixed bits FIXBIT [51: 0] and the data bits FIFOOUT [51: 0]. If the data signals FIFOOUT [51: 0] contain correctable erroneous data bits, these data bits are "flopped" by the exclusive-OR operation, the Exclusive OR gates 354 provide the corrected data CORRMSG [51: 0] to the 1 input of a multiplexer 360 , The 0 input of the multiplexer 360 takes the data bits FIFOOUT [51: 0] and the multiplexer 360 is through a configuration signal CFG2C_ENABLE_ECC selected. The output of the multiplexer 360 generates signals MUXMSGI [51: 0]. If the system software releases error detection and correction by setting signal CFG2C_ENABLE_ECC high, then the multiplexer selects 360 the corrected data CORRMSG [51: 0] for an output. Otherwise, if the error detection and correction is disabled, the data bits FIFOOUT [51: 0] are used.

The uncorrectable and correctable error indicators NCERR and CRERR become AND gate inputs 356 and 358 each delivered. The AND gates 356 and 358 are enabled by the signal CFG2C_ENABLE_ECC. The outputs of the AND gates 356 and 358 generate signals C_NLERR and C_CRERR, respectively. The signals C_NLERR and C_CRERR can only be set if an error detection and a correction are enabled. If an error is detected, the fixed bits are locked and used for diagnostic purposes.

If a correctable error is indicated (the signal C_CRERR is high), then an interrupt is made to the interrupt receive block 132 towards the interrupt output block 114 , and then transferred to the system interrupt controller, and then to the CPU 14 to call an interruption trader. The uncorrectable errors, indicated by the signal C_NCERR, will cause the system error SERR_ to be asserted, which in turn causes the system interrupt controller (not shown) to assert the non-maskable interrupt (non-maskable interrupt). NMI) to the CPU 14 sets up. In the output side bridge chip 48 uncorrectable errors will cause the Power-Good / PLL-Lock indication bit to continue to the cable 28 is sent to be neglected, so the input side bridge chip 26 no cycles sent to the exit side.

To prevent random interrupts during and after a power-up, fault detection and correction on both the input and output bridge chips is disabled during a power up operation until the input side PLL 186 and the output PLL 182 locked to the clock CABLE_CLK1 or CABLE_CLK2.

A System mangament software pointing to the interruption for correctable Fault responds, determines the cause by reading the locked Fix bits. If a hardware failure is determined (eg multiple data error bits, assigned the same cable wire), then the system management software can Alert user to the condition to eliminate the hardware error. The system management software responds to SERR_ caused by an uncorrectable Error, turn off the system, or perform other functions programmed by the user.

SECONDARY BUS ARBITER

As the 3 shows, each bridge chip includes a PCI arbitrator 116 or 124 , As the input side bridge chip 26 normally installed in a slot becomes the PCI arbitrator 116 blocked. The PCI arbitrator 124 supports 8 master: 7 general PCI master (REQ [7: 1] _, GNT [7: 1] _), comprising the six PCI slots and the hot-plug control unit in the SIO 50 , and the bridge chip itself (BLREQ_, BLGNT_). The signals BLREQ_ and BLGNT_ are from and to the PCI master block 123 guided. The bridge chip asserts the signal BLREQ_ if a transaction from the CPU 14 , intended for the secondary PCI bus 32 , through the input side and output side bridge chip 26 and 48 is received. The request and grant lines REQ [1] _ and GNT [1] _ for the SIO 50 be internal to the output side bridge chip 48 forwarded. The PCI arbitrator 124 sets a PCICLK2 delay between negating a GNT_ signal for one master and establishing a GNT_ signal for another master.

In the output side bridge chip 48 becomes the PCI arbitrator 124 enabled or disabled based on the sampled value of REQ [7] _ at the rising edge of the PCIRST2_ signal. If the bridge chip 48 REQ [7] _ low samples on PCIRST2_, it becomes the PCI arbiter 124 lock. If the PCI arbiter 124 is locked, then an external arbitrator (not shown) is used and the hot-plug request is triggered on the REQ [1] pin and the hot-plug grant is entered on the GNT [1] pin. The bridge PCI bus request is driven on the REQ [2] pin and its issuance is entered on the GNT [2] pin. If the bridge chip 48 REQ [7] _ scans high on PCIRST2_, it becomes the PCI arbiter 124 release.

The PCI arbitrator 124 negates a GNT_ signal of the master, either by an initiator with higher Priority or to the REQ_ signal of the master to be negated. Once its GNT_ signal is negated, the current bus master holds ownership over the bus until the bus returns to idle.

If no PCI agents are currently using or requesting the bus, the PCI arbitrator takes 124 one of two things depending on the value of a PARKMSTRSEL configuration register in the configuration space 125 in front. If the register contains the value of 0, the PCI arbitrator uses 124 the last active master to get on the bus 32 to park; if it contains the value 1, then the bus on the bridge chip 48 parked.

The PCI arbitrator 124 includes a PCI minimum grant timer 304 ( 21 ) that controls the minimum active time of all the GNT_ signals. The error value for the timer 304 is the hexadecimal value 0000 indicating that there is no minimum grant time requirement. The timer 304 can be programmed with a value from 1 to 255 to indicate that the number of PCICLK2 clock periods of the GNT_ line is active. Alternatively, the individual minimum grant timer may be any PCI master on the secondary bus 32 be assigned for greater flexibility. The minimum grant time is only applicable when the current master asserts its REQ_ signal. Once the REQ_ signal is removed, the GNT_ signal may be issued regardless of the minimum grant time value.

As 20A shows, in normal operation, the PCI arbitrator 124 a round robin priority scheme (second level arbitration scheme). The eight masters in the round-robin scheme include devices connected to the six slots of the expansion box 30 , the SIO 50 and a posted memory write (PMW) request from the upstream bridge chip 26 are connected. All master on the PCI bus 32 in this scheme have the same priority as the bridge chip 48 , After the master the secondary PCI bus 32 and the master has issued the FRAME_ signal, the bus is again arbitrated and the current master is placed at the bottom of the round robin stack. If the master negates this request or the minimum grant timer 304 expires, the PCI bus 32 the master with the next highest priority. Locked cycles will not be different in any way by the PCI arbiter 124 treated.

In response to certain events, the arbitration scheme is modified to optimize a system function. The events include: 1) an input-to-output delayed read or delayed write request is pending, 2) an output-to-input delayed read request is pending without providing a read complete indication, and 3) a streaming possibility exists while the bridge chip 26 the current master on the input side bus 24 is.

When a delayed request is detected, the bridge chip becomes 48 the next master, the secondary PCI bus 32 to be granted. If ever the bridge chip 48 the bus 32 is granted, he retains ownership of the bus 32 until it completes any pending, deferred requests or retries one of its cycles. If the bridge chip 48 retry is a two-level arbitration scheme by the arbitrator 124 executed. A primary cause for the bridge chip read cycle being retried is that the target device is a bridge to a posted write buffer that needs to be cleared. In this case, the optimal operation is the bus 32 to grant to the retrying target to allow it to empty its posted write buffer so that it can accept the bridge chip read request.

As 20B 2, a two-level arbitration protocol includes a first-level arbitration scheme, which is a round-robin scheme, among three possible masters: the delayed request from the CPU 14 , a request from the retry master, and a master selected by the second level arbitration scheme. Each of these three masters in the arbitration scheme under the first level is issued to each third arbitration slot. For memory cycles, the slot associated with the retry target may be from the target memory area configuration registers in the configuration space 125 of the bridge chip 48 which stores the memory area associated with each PCI device. If the retrying master can not be determined (as in the case of I / O reading), or if the master trying again does not have the secondary bus 32 requesting, then the arbitration scheme would be at the first level between the bridge chip 48 and a Level Two Master.

The re-trying master is not masked by the level two arbitration. As a result, is it is possible for him to have two back-to-back arbitration wins if he is the next master in the level two arbitration scheme.

For example, if an input-to-output read is retried and the master C (the retrying master) attempts the bus 32 as well as requesting a master B and a master E, the order of the bus schedules will be in a descending order as follows: the bridge chip 48 , the Master again trying (Master C), the Master C, the bridge chip 48 , the Master Master C, the Master E, the bridge chip 48 , etc., until the bridge chip 48 is able to complete its transaction, and the PCI arbitrator 152 back to its level two arbitration scheme for normal operation.

If, as another example, the bridge chip read is retried and the only others the requesting masters are master A and master D (ie, the retry master does not request the bus or it could not be identified as it does is accessing an I / O space), the order of the bus grants is as follows: the bridge chip 48 , the master A, the bridge chip 48 , the master D, etc ..

The two-level arbitration scheme gives delayed requests from the CPU 14 the highest priority. Although this arbitration method is strong the CPU 14 favors every requesting device on the bus 32 finally the PCI bus 32 granted. By doing so, there is less chance that the other, secondary bus masters would be neglected if a PCI bridge chip request is retried.

With reference to 21 includes the PCI arbitrator 124 an L2 state machine 302 to execute the level two round robin arbitration scheme. The L2 State Machine 302 receives signals RR_MAST [2: 0] indicating the current round robin master. The L2 State Machine 302 also receives request signals RR_REQ [7: 0] corresponding to the 8 possible masters of the secondary PCI bus 32 , Based on the current master and the status of the request signals, the L2 generates state machine 302 a value representing the next round robin master. The output of the L2 state machine 302 becomes the 0 input of a 6: 3 multiplexer 306 whose 1-input signals receive Q2A_STRMAST [2: 0]. The selection or select input of the multiplexer 306 receives a STREAM_REQ signal high on an AND gate 308 is set, if a streaming opportunity exists (Q2A_STREAM is high), the streaming master on the secondary PCI bus 32 its request line (MY_REQ [Q2A_STRMAST [2: 0]] is high) and a delayed request is not pending (BAL_DEL_REQ is low).

The output of the multiplexer 306 drives signals N_RR_MAST [2: 0] representing the next round robin master in the level two arbitration scheme. The signals N_RR_MAST [2: 0] are passed through an L1 state machine 300 which also receives the following signals: a signal RTRYMAST_REQ (representing the request of the retrying bus master); a signal MIN_GRANT (which is asserted when the minimum grant timer 304 timely); the delayed request signal BAL_DEL_REQ; the data sequence request signal STREAM_REQ; a CURMAST_REQ signal (indicating that the current master is maintaining its request signal asserted); a signal ANY_SLOT_REQ (asserted high if any of the request signals REQ [7: 0] _ is high but not including the bridge chip request BLREQ_); and signals L1STATE [1: 0] (representing the current state of the L1 state machine 300 group). The L1 state machine 300 selects one of three possible L1 masters, including the retrying master (RTRYMAST_REQ), the delayed request from the bridge chip 48 (BAL_DEL_REQ) and the level two master (ANY_SLOT_REQ).

The request signal of the retrying master RTRYMAST_REQ is passed through an AND gate 312 which generates the signal BAL_DEL_REQ, the signal MY_REQ [RTRY_MAT [2: 0]] (indicating whether the retrying master makes its request) and the output of an OR gate 310 receives. The inputs of the OR gate 310 pick up the signals RTRY_MAST [2: 0]. Thus, if a retry master has been identified (RTRY_MAST [2: 0] is non-zero), a deferred request exists (BAL_DEL_REQ is high), and a retry master has asserted its request, then the signal RTRYMAST_REQ is asserted.

The L1 state machine 300 generates signals N_L1STATE [2: 0] (representing the next state of the L1 state machine 300 as well as signals N_CURMAST [2: 0] (representing the next master according to the Represent level two arbitration scheme). The L1 state machine 300 also generates an OPEN_WINDOW signal indicating when a re-arbitrating window for a grant state machine 306 exists to master on the secondary PCI bus 32 to change. A signal ADV_RR_MAST, supplied by the L1 state machine 300 , points to the grant state machine 306 when the value of the signals N_RR_MAST [2: 0] are to be loaded into the signals RR_MAST [2: 0] to continue the next level two round robin master.

The Grant State Machine 306 Issues GNT [7: 0] as well as a CHANGING_GNT signal to indicate ownership of the bus 32 will be changed. The grant signals GNT [7: 1] _ are inverted by the GNT [7: 1] signals, and the grant signal BLGNT_ is inverted by the GNT [0] signal. The Grant State Machine 306 also generates signals L1STATE [1: 0] and signals RR_MAST [2: 0].

The minimum grant timer 304 is clocked by the signal PCLK and generates the signal MIN_GRANT. The minimum grant timer 304 also receives the CHANGING_GNT and NEW_FRAME signals (indicating that a new FRAME_ signal has been established). The initial value of the minimum grant timer 304 is loaded as a value {CFG2A_MINGNT [3: 0], 0000}, with the signals CFG2A_MINGNT [3: 0] stored configuration bits in the configuration space 125 are the initial value of the minimum grant timer 304 define. The minimum grant timer 304 is reloaded after counting down to zero, and the CHANGING_GNT signal is set high. After the minimum grant timer 304 is loaded with a new value, it starts to degrade when the signal NEW_FRAME is set high and the signal CHANGING_GNT is set low by the grant state machine 306 is withdrawn, indicating that a new transaction on the PCI bus 32 has begun.

Signals MY_REQ [7: 1] are passed through a NOR gate 314 whose inputs receive the request signals REQ [7: 1] _ and masking signals Q2AMASKREQ [7: 1]. Setting the mask bit Q2AMASKREQ [X], X = 1-7, masks the request REQ [X] _ of the corresponding master, which prevents the PCI arbitrator 124 respond to the request signal. A signal MY_REQ [0] is given by an inverter 316 which receives the bridge request BLREQ.

As 22 Fig. 1 includes the grant state machine 306 four states: PARK, GNT, IDLE4GNT and IDLE4PARK. Upon asserting a RESET signal (generated by the PCI reset signal PCIRST2_), the grant state machine enters 306 in a state PARK, where it remains while a signal ANY_REQ is removed. The ANY_REQ signal is set high if any of the request lines to the PCI arbiter 124 is set up. The PARK state becomes the PCI-PCI bridge 48 as the owner of the PCI bus 32 parked if another requirement does not exist.

If the signal ANY_REQ is asserted, the grant state machine goes 306 from state PARK to state IDLE4GNT, and signal CHANGING_GNT is set high to indicate that the PCI arbitrator 124 Master changes. The grant signals GNT [7: 0] are all cleared to zero, and the signals CURMAST [2: 0] are updated with the value of the next master N_CURMAST [2: 0]. In addition, the round robin master signals RR_MAST [2: 0] are updated with the next round robin master value N_RR_MAST [2: 0] when the signal ADV_RR_MAST is cleared by the L1 300 is set up. The signal ADV_RR_MAST indicates, if high, that the next L1 master is one of the L2 masters.

From a state IDLE4GNT passes the grant state machine 306 next to the GNT state, and the signals GNT [7: 0] are set to the state of new grant signals NEWGNT [7: 0] and the signal CHANGING_GNT are set to low. The signals NEWGNT [7: 0] are based on the state of the current master signals CURMAST [2: 0], as shown in FIG 24 is shown.

From state GNT three transitions are possible. The Grant State Machine 306 returns to the PARK state if an arbitration window is open (OPEN_WINDOW is high), no request is pending (ANY_REQ is low), the PCI bus 32 is empty (BUS_IDLE is high) and the next master is the current master (ie the current master is the parked master). In the transition back from the GNT state to the PARK state, the signals L1STATE [1: 0] are updated with the signals N_L1STATE [1: 0]. However, if no requests are pending and the bus is empty, but the current master is not the parked master (ie the signals N_CURMAST [2: 0] are not equal to the value of the signals CURMAST [2: 0]), an idle state is needed and the grant state machine 306 goes from the GNT state to the IDLE4PARK state. The L1 state values L1STATE [1: 0] are updated. From the IDLE4PARK state goes the grant state machine 306 to the PARK state, setting the grant signals GNT [7: 0] equal to the new grant signals NEWGNT [7: 0] to the PCI bus 32 to grant the new master. The CHANGING_GNT signal is also set low.

If the arbitration window opens (OPEN_WINDOW is high) and the next master is not the current master (the N_CURMAST [2: 0] signals are not equal to the CURMAST [2: 0] signals), then the grant state goes -Machine 306 to idle state IDLE4GNT over to change bus master grants. During the transition, the signal CHANGING_GNT is set high, the signals GNT [7: 0] are all cleared to zeros, the signals CURMAST [2: 0] are updated with the next master value N_CURMAST [2: 0], and the L1 state signals L1STATE [1: 0] are updated with the next state value N_L1STATE [1: 0]. In addition, the round robin master signals RR_MAST [2: 0] are updated with the next round robin master RR_MAST [2: 0] if the signal ADV_RR_MAST is set high. The grant signals GNT [7: 0] are then set to the value NEWGNT [7: 0] at the transition from the IDLE4GNT state to the GNT state.

As 23 shows, the L1 state machine starts 300 ( 21 ) into one, state RR setting up the RESET signal, where the state machine 300 remains while a delayed request signal BAL_DEL_REQ is set low (indicating that there is no pending request pending). In the RR state, the signal ADV_RR_MAST is set high to the grant state machine 300 to allow the round-robin master to be updated (ie, setting signals RR_MAST [2: 0] equal to the value N_RR_MAST [2: 0]). The RR state is the round robin state in which the level two arbitration scheme is used. In the RR state, the next master signals N_CURMAST [2: 0] are set equal to the next round robin master N_RR_MAST [2: 0], and the signal OPEN_WINDOW is set high if the data string request occasion exists (STREAM_REQ is high), or the minimum grant timer 304 has expired (MIN_GRANT is high) or the current master has made his request (CURMAST_REQ goes low). When high up, the OPEN_WINDOW signal allows a new arbitration to take place.

If a delayed request is detected (BAL_DEL_REQ goes too high), the L1 state machine goes 300 from the RR state to the BAL state, the next master state N_CURMAST [2: 0] as the bridge chip 48 adjusting and taking away the signal ADV_RR_MAST to disable the level two round robin arbitration. In the BAL state, the OPEN_WINDOW signal is set high if the deferred request is cleared (BAL_DEL_REQ goes low), or the deferred request has been retried (BAL_RETRIED goes high). If the BAL_DEL_REQ signal is low, or if the delayed request BAL_DEL_REQ is set high, but the request of the retrying master is set low (RTRYMAST_REQ is low) and the slot request ANY_SLOT_REQ is set high, then the L1 goes state machine 300 back to the RR state. At the transition, the signal ADV_RR_MAST is set high and the next master signals N_CURMAST [2: 0] are set equal to the next round robin master N_RR_MAST [2: 0]. If the signal BAL_DEL_REQ is removed, this indicates that the arbitrator 124 should return to the level two round robin scheme. If the delayed request signal is asserted, but the request of the retrying master is removed, then the level one arbitration scheme is between the slots on the PCI bus 32 and the bridge chip 48 ,

If both the delayed request BAL_DEL_REQ and the request of the retrying master RTRYMAST_REQ are set up, then the L1 state machine goes 300 from the state BAL to the state RETRY_MAST, and the retrying master is set as the next master (N_CURMAST [2: 0] is set equal to RTRY_MAST [2: 0]). The signal ADV_RR_MAST is kept low. In the RETRY_MAST state, if none of the PCI slot masters make a request (ANY_SLOT_REQ is low), then the level one arbitration scheme is between the retrying master and the bridge chip 48 , and the L1 state machine 300 goes back to the BAL state. The bridge chip 48 is set as the next master (N_CURMAST [2: 0] is equal to the state BAL-BOA), and the signal ADV_RR_MAST is kept low. However, the L1 state machine goes 300 from the RETRY_MAST state to the RR state if any of the slot master makes a request (ANY_SLOT_REQ is high). During the transition, the signal ADV_RR_MAST is set high, and the next round robin master is set as the next master (N_CURMAST [2: 0] is set equal to N_RR_MAST [2: 0]).

To take advantage of the bridging chip's streaming capabilities when data for a DRC starts from the cable 28 To arrive, the master assigned to this DRC becomes the highest priority device (assuming its REQ_ is established). This allows the master, the data sequence, of the cable 28 incoming, while the selection window is there for streaming. If the bridge chip 48 can not connect the master before the DRC queue is filled, then the input side bridge chip 24 and only a portion of the data would be passed to the requesting master, requiring that the master request another read on the input bus 24 emits. The streaming master keeps the highest priority from the cable as long as DRC data continues 28 to arrive. If the master repeats a different cycle address, this will be retried, but it will be owned by the secondary PCI bus 32 until his request goes away or the opportunity for streaming is over.

TRYING AGAIN REQUIREMENTS AND MULTI-THREADED MASTER

Since each bridge chip is a delayed transaction device, if a device is on the output side bus 32 Issue a read request, destined for an input-side target, becomes the output-side bridge chip 48 a retry transaction (described in the PCI specification) on the secondary bus 32 spend and the request continues to the cable 28 to lead. The retry transaction causes the requesting master to control the PCI bus 32 give up and take away his REQ_ line. After removing its REQ_ line, the retrying master will again assert a request for the same cycle at a later time, causing its GNT_ to be asserted (if its REQ_ line is unmasked) and the bus master to retry until the Read completion indication in the output side bridge chip 48 is set up.

As the 25 In order to avoid unnecessarily handling re-try requests, the REQ_ line will issue a secondary bus master with a retry to issue a delayed read or write request by asserting the appropriate one of the signals Q2A_MASK_REQ [7: 1 ] (Request from the bridge chip 48 that are tried again are not masked), masked until the delayed completion returns. In this way, other requesting masters are given priority to bring their requests in. Once the first information associated with the delayed completion is returned, the REQ_ line of the corresponding master is freed from masking and the retrying master is able to reenter arbitration.

However, a special case exists for multi-threaded (or multi-headed) masters on the output side bus 32 ( 26B ) who are able to make a first request to be retried and come back with a different request. One such multi-threaded bus device is a PCI-PCI bridge 323 that the secondary PCI bus 32 and a subordinate PCI bus 325 combines. The bus 325 is available with Network Interface Cards (NICs) 327A and 327B connected to two different networks. Consequently, if the request from the NIC 327A for the primary PCI bus 32 again through the bridge chip 48 trying to get the NIC 327B create a different requirement. In this case, the REQ_ lines of the multi-threaded master are not masked as indicated by the signal CFG2Q_MULTI_MASTER [X] being set high.

A status register 326 determines if a slot is single or multi-threaded. When reset, the register becomes 326 cleared to assume that each secondary bus device is single threaded. The slot is then monitored to determine if it is requesting a different cycle while another cycle is pending from the same master. If a multi-threaded behavior is observed in a master, then one is marked high by setting the corresponding bit CFG2Q_MULTI_MASTER [X].

The input of the status register 326 comes with the output of a 14: 7 multiplexer 328 whose 0 input is connected to the output of a 14: 7 multiplexer 330 whose 1-input is connected to address bits P2Q_AD [22:16]. A selection signal CFGWR_MM selects the 0 and 1 inputs of the multiplexer 328 out. When high, the signal CFGWR_MM causes a configuration write of the status register 326 from the data bits P2Q_AD [22:16], which provides software control of the bits in the register 326 allows. The 1 input of the multiplexer 330 takes multi-master signals MULTI_MASTER [7: 1] on, the 0 input receives the output of the register 326 and the multiplexer 330 is selected by a signal MULTI_SEL. The signal MULTI_SEL is passed through an AND gate 338 whose first input receives signal Q2PIF_CHECK_CYC (set high to indicate that the current transaction information should be checked against information contained in the queue block 127 in terms of adaptation, such as during a delayed memory read or write request from a bus device on the secondary PCI bus 32 ), and the other input receives the inverted state of the DCQ_HIT signal (indicating that the current address information does not match the address information corresponding to a pending request from the requesting master in the DCQ) 148 assigned). As a result, if an erroneous comparison occurred, the value of the signals CFG2Q_MULTI_MASTER [7: 1] is updated.

One Bit MULTI_MASTER [X] is set high if the master X is a pending Request that has been retried and the master X subsequently to back comes to a different request. This is done by comparing the transaction information (eg address, byte shares, data for a Letter) of the pending Requested request with the address of the new request. One Failed comparison indicates that the master is in multi-threaded operation is. If once a multi-master configuration bit CFG2Q_MULTI_MASTER [X] (X = 1-7) is set high, the bit is kept high.

The MULTI_MASTER [7: 1] signals are passed through a decoder 336 generated. The decoder 336 takes signals Q2PIF_SLOT [2: 0] (slot number for the current, delayed request from a master), Q [7: 0] _MASTER [2: 0] (the master assigned to each of the eight buffers in the DCQ 148 ), Q [7: 0] _COMPLETE (the completion status of each of the eight queues), and Q [7: 0] _PART_COMPLETE (the partial completion status of each of the buffers in the deferred completion queue). For example, if the signal Q0_MASTER [2: 0] contains the value 4, it indicates that the DCQ buffer 0 is the transition information of a delayed request from the bus device in the slot 4 stores. The signal QY_COMPLETE, Y = 0-7, indicates if "high" is asserted that the DCQ buffer Y has received all the data associated with the delayed request transaction The signal QY_PART_COMPLETE, Y = 0-7 , if high, indicates that the DCQ buffer Y has been allocated as the DCQ delayed transaction buffer by one of the masters, but all the data associated with the delayed transaction has not yet been received.

If the current slot number Q2PIF_SLOT [2: 0] is equal to the value of any of the eight queue master indication signals Q [7: 0] _MASTER [2: 0], and the corresponding DCQ buffer is in the terminator or partial completion state, then the corresponding one of the MULTI_MASTER [7: 1] bits is set high if the signal DCQ_HIT is low and the signal Q2PIF_CHECK_CYC [2: 0] is high. As a result, for example, if the signal Q2PIF_SLOT [2: 0] contains the value 2, indicating that the device is in slot 2 the master is the delayed request, and the DCQ buffer 5 a pending request for the slot 2 -Master stores (Q5_MASTER [2: 0] = 5), and any of the signals Q5_COMPLETE or Q5_PART_COMPLETE is high, and if the signal Q2PIF_CHECK_CYC is high and the signal DCQ_HIT is low, then the bit MULTI_MASTER [2] is set high to indicate that the slot 2 device is a multi-threaded master.

A mask request generation block 332 generates signals Q2A_MASK_REQ [X] (X = 1-7) in response to signals Q [7: 0] _MASTER [2: 0], Q [7: 0] _STATE [3: 0], (indicating the state of delayed completion Queues 0-7), SLOT_WITH_DATA [7: 0] (indicating whether a delayed completion contains Qs 0-7 valid data), CFG2Q_MULTI_MASTER [X] (X = 1-7), CFG2Q_ALWAYS_MASK, and CFG2Q_NEVER_MASK.

As 26A The mask request generation block comprises 332 a 2: 1 multiplexer 320 for generating the signal Q2A_MASK_REQ [X] (X = 1-7). The 1 input of the multiplexer 320 is with the output of an OR gate 322 connected and the 0 input is set to low. The selection input of the multiplexer 320 is controlled by a signal MASK_MUXSEL. An input of the OR gate 322 is at the output of a NOR gate 324 which receives a signal CFG2Q_MULTI_MASTER [X] (indicating a multi-threaded master), and the other input receives a signal CFG2Q_NEVER_MASK (a configuration bit indicating that the request line should not be masked if a multi -Hreaded master is detected). The other input of the OR gate 322 receives a signal CFG2Q_ALWAYS_MASK which is a configuration bit indicating that the corresponding mask bit Q2A_MASK_REQ [X] should always be masked if the signal MUXSEL is set high. The signal MASK_MUXSEL is set high if the request from the secondary bus master does not Data already exists in the queue block 127 exist, ie the request must be to the primary PCI bus 24 be transmitted. As a result, at any time, a request from a device on the secondary PCI bus becomes 32 on the input side to the primary PCI bus 24 a check is made for bits CFG2Q_MULTI_MASTER [7: 1] to determine if a multi-threaded master has been detected.

The masking of requests can be done by setting the appropriate bits in the configuration registers 125 to be ignored. The available modes include: 1) normal mode in which request masking is enabled, except in the case of a multi-threaded master (CFG2Q_NEVER_MASK = 0, CFG2Q_ALWAYS_MASK = 0), 2) always a masking mode in which Requests of retrying masters are masked even if multi-threaded (CFG2Q_ALWAYS_MASK = 1), and 3) never masking mode in which the requests are never masked (CFG2Q_NEVER_MASK = 1, CFG2Q_ALWAYS_MASKED = 0).

EXPANSION CARD INSERTION AND REMOVAL OF CONNECTION EXPANSION CARDS

As in the 1 and 27A have the two expansion boxes 30a and 30b , by a common design 30 , each of the six hot-plug slots 36 ( 36a - f ), in which the conventional expansion cards 807 can be inserted and removed (hot-plugged) while the computer system 10 remains powered up or remains on. The six mechanical levers 802 are used to selectively expand the expansion cards 807 To secure (if closed, or locked, is) in the appropriate hot-plug slots 36 be used. For purposes of removing or inserting the expansion cards 807 in one of the slots 36 must be the appropriate lever 802 be opened or unlocked, and as long as the lever 802 is open, the corresponding slot remains 36 off.

When the lever 802 who is the expansion card 807 at his slot 36 secures, opens, captures the computer system 10 this appearance and drives the map 802 down (and the corresponding slot 36 ) before the card 807 from their slot or slot 36 can be removed. Slots or slots 36 that are shut down, similar to other slots 36 that do not have cards 807 hold, remain shut down or shut down until software of the computer system 10 selectively the slots or slots 36 boots up.

The map 46 , inserted in the card slot 34 , owns the bridge chip 48 that the fuse status (open or closed) of the lever 802 supervised and any card 807 (and a corresponding slot 36 ), which is not shut down by its lever 802 is secured. A software of the computer system 10 can also selectively use any of the slots 36 shut down.

The cards 807 are powered up by a startup sequence and shut down by a shutdown sequence. In the power up sequence, energy first becomes the card 807 which is to be powered up, and thereafter a PCI clock signal (from the PCI bus 32 ) to the map 807 delivered, which is raised. Remaining PCI bus signal lines of the card 807 are then with corre sponding lines of the PCI bus 32 connected. Last is the reset signal for the card 807 , which is raised, taken away what the card 807 outside a reset state.

The boot sequence allows the circuit of the card 807 in that it powers up to become fully functional with the PCI clock signal before delivering the remaining PCI bus signals. When the clock signal and the remaining PCI bus signals with the card 807 be connected and before the card 807 is reset, owns the bridge chip 48 a control of the PCI bus 32 , Because the bridge chip 48 a control over the PCI bus 32 During these times, potential failures interfere with the PCI bus 32 from the power-up sequence not the operations of the cards 807 that started up.

In the shutdown or power-down sequence, the card becomes 807 to be shut down, reset first. Next, the PCI bus signals, without the PCI clock signal, from the card 807 away. The bridge chip 48 Subsequently, it interrupts the PCI clock signal from the card 807 before energy from the card 807 Will get removed. The power-down sequence minimizes the propagation of false signals from the card 807 to be shut down to the bus 32 because the circuit is on the card 807 maintains its full function until the PCI bus signal lines are removed.

When the PCI clock signal and the remaining PCI bus signals are interrupted, and if the card 807 reset or put into a reset state, has the bridge chip 48 a checkpoint of the PCI bus 32 , Because the bridge chip 48 a control over the PCI bus 32 during these times, potential defects interfere with the PCI bus 32 from the power-down or shutdown sequence not the operations of the cards 807 they started up.

The bridge chip 48 includes the serial input / output (SIO) circuit 50 showing the startup and shutdown sequences of the slots or slots 36 controls over twenty-four control signals POUT [39:16]. The control signals POUT [39:16] are a subset of forty output control signals POUT [39: 0] generated by the SIO circuit 50 , The control signals POUT [39:16] are latched versions of slot bus enable signals BUSEN # [5: 0], slot power enable signals PWREN [5: 0], slot clock enable signals CLKEN # [5: 0] and slot reset signals RST # [5: 0], all internal signals of the SIO circuit 50 as further described below. The control signals POUT [39: 0] and their relation to the signals BUSEN # [5: 0], PWREN [5: 0], CLKEN # [5: 0] and RST # [5: 0] are described in the following table :

PARALLEL OUTPUT CONTROL SIGNALS (POUT [39:01])

As in the 2 and 28 is shown, each has a hot-plug slot 36 the associated switching circuit 41 for connecting and disconnecting the slot 36 with and from the PCI bus 32 , The switching circuit 41 for every slot 36 receives four of the control signals POUT [39:16]. As an example, for the slot 36a when the control signal POUT [28] is established, or low, the slot 36a with the bus signal lines of the PCI bus 32 through a switching circuit 47 connected. When the control signal POUT [28] is taken off, or is high, the slot becomes 36a from the bus signal lines of the PCI bus 32 separated.

When the control signal POUT [22] is asserted, or is low, the slot becomes 36a with a PCI clock signal CLK via a switching circuit 43 connected. When the control signal POUT [22] is taken off, or is high, the slot becomes 36a separated from the clock signal CLK.

When the control signal POUT [34] is asserted, or is high, the slot becomes 36a with a card voltage supply level V _ss via a switching circuit 45 connected. When the control signal POUT [34] is taken out, or is low, the slot becomes 36a separated from the card voltage supply level V _ss .

When the control signal POUT [16] is set up or is low, the slot becomes 36a reset, and when the control signal POUT [16] is removed, or is high, the slot passes 36a from its reset state.

As in 2 can be seen, the SIO circuit 50 selectively up to one hundred twenty-eight (sixteen bytes) of latched status signals STATUS [127: 0] supplied by the expansion box 30 , keep the watch over. The status signals STATUS [127: 0] form a "snapshot" of selected states of the expansion box 30 , The status signals STATUS [127: 0] include six status signals STATUS [5: 0] indicating the fuse status (open or closed) of each of the levers 802 Show. The SIO circuit 50 monitors status signals STATUS [31: 0] for changes in their logic voltage levels. The SIO circuit 50 shifts the status signals STATUS [127: 32] serially into the SIO circuit 50 into it when through the CPU 14 instructed to do so.

The SIO circuit 50 serially receives the status signals STATUS [127: 0], the least significant signal first, via a serial data signal NEW_CSID. The data signal NEW_CSID is passed through the serial output of the parallel input shift register 82 with thirty-two bits, arranged on a circuit board of the expansion box 30 , along with the slots or slots 36 , delivered.

The registry 82 receives, via its parallel inputs, twenty-four parallel status signals PIN [23: 0], four assigned to each of the hot-plug slots 36 which are included in the thirty-two least significant status signals STATUS [31: 0]. When the status indicated by one or more of the status signals STATUS [31: 0] changes (the logic voltage level changes), the bridge chip generates 48 an interrupt request to the CPU 14 by setting, or driving low, a serial interrupt request signal SI_INTR #, via an interrupt receive block 132 Will be received. The status signals PIN [23: 0] include two PCI card presence signals (PRSNT1 # and PRSNT2 #) associated with each slot 36 ,

Six status signals PIN [5: 0] corresponding to their locked versions, status signals STATUS [5: 0], indicate the locking or engagement status (open or closed) of each of the levers 802 at. Six sliding switches 805 ( 27A - 27C ) are the movement of their corresponding lever 802 and are used to electrically lock the fuse status of the corresponding lever 802 display. Every switch 805 has a first terminal connected to ground, and a second terminal which supplies the corresponding one of the status signals PIN [5: 0]. The second terminal is at a supply voltage level V _DD via one of six resistors 801 connected.

If one of the levers 802 opens and the card 807 , secured by the lever 802 is unlocked, the corresponding one of the status signals PIN [5: 0] is set, or driven high. As an example, for the slot 36a , the status signal PIN [0] taken away or driven low when the corresponding lever 802 closed is. When the lever 802 for the slot 36a is open, the status signal PIN [0] is set up or driven high.

The registry 82 Also receives a serial data string of latched status signals STA TUS [127: 32], which will not interrupt when the logic voltage level of one of the STATUS [127: 32] signals changes. The status signals STATUS [127: 32] are indicated by the shift register 52 with sixteen bits, arranged on the circuit board of the expansion box 30 , with the slots 36 , educated. The move register 52 receives status signals at its parallel inputs and latches the status signals STATUS [127:32] when through the SIO circuit 50 is instructed to do so. The move register 52 serializes the status signals STATUS [127: 32] and supplies the signals STATUS [127: 32] to the serial input of the register 82 via a serial data signal CSID_I.

If through the SIO circuit 50 instructed locks the register 82 Status signals PIN [23: 0], forms the status signals STATUS [31: 0], provides the status signals STATUS [31: 0] and supplies one byte or more of the status signals STATUS [127: 32] ( if so by the CPU 14 is requested), in a least significant signal of a first kind, to the SIO circuit 50 , via the serial data signal NEW_CSID. The status signals STATUS [127: 0] are described by the following table:

STATUS [127: 0]

As in the 2 and 30 is shown locked when an SIO circuit 50 sets up a register load signal CSIL_O_ or low, the shift register 52 the status signals STATUS [127: 32] and the shift register 82 locks the status signals STATUS [31: 0]. If the SIO circuit 50 the signal CSIL_O_ takes away, or on high, both registers move 52 and 82 serial their data to the SIO circuit 50 on the positive edge of the clock signal CSIC_O, supplied by the SIO circuit 50 , The clock signal CSIC_O is synchronized to and at a quarter of the frequency of the PCI clock signal CLK.

As in 29 For purposes of monitoring, or for sampling, the status signals STATUS [31: 0], the SIO circuit is used 50 a 32-bit interrupt register 800 whose bit positions correspond to the signals STATUS [31: 0]. The SIO circuit 50 updates the bits of the interrupt register 800 to equalize the corresponding status signals STATUS [31: 0] that have been debounced, as further described below. Two status signals STATUS [7: 6] are for additional hot-plug slots 36 reserved, and the seventh and eighth, most significant bit of the interrupt register 800 also be for the extra slots 36 reserved. The interrupt register 800 is a part of a register logic block 808 the SIO circuit 50 that with the PCI bus 32 is coupled.

A serial scan input logic 804 the SIO circuit 50 sequentially, or monitors, the status signals STATUS [31: 0], the least significant signal first, for changes as indicated by transitions in their logical voltage levels. If the status of one or more of the status signals STATUS [5: 0], associated with the levers 802 , changes, the serial scan input logic occurs 804 in a slow scan mode, so that the status signals STATUS [5: 0] are sampled thirty-two times within a predetermined debounce time interval. If one or more of the status signals STATUS [5: 0] changes, the serial scan input logic updates 804 the interruption register 800 (and asserts the serial interrupt signal SI_INTR #) if the changed status signal STATUS [5: 0] remains at the same logic voltage level for at least a predetermined debounce time interval. The serial scan input logic 804 is with programmable timers 806 which generate and indicate the end of the debounce delay interval initiated by the serial scan logic 804 , Demanding the status to remain stable for debounce time minimizes the unintentional power-down of one of the hot-plug slots 36 due to an incorrect value (ie, a "defect") indicated by one of the status signals STATUS [5: 0]. If all of the status signals STATUS [5: 0] are at the same logic voltage level for at least the debounce time. Interval remain, then the serial scan input logic proceeds 804 to once again sample all thirty-two status signals STATUS [31: 0] in the faster scan mode.

If the serial scan input logic 804 detects a change in any of the status signals STATUS [31: 6], instructs the serial scan input logic 804 the timers 806 to measure another debounce delay interval, thereon sets up the serial interrupt signal SI_INTR #, updates the interrupt register 800 with the signals STATUS [31: 6] that have changed, and ignores further changes in the status signals STATUS [31: 6] until the debounce time interval expires. Upon expiration of the debounce time interval, the serial scan input logic proceeds 804 to detect changes in the thirty-two status signals STATUS [31: 0].

When the serial interrupt signal SI_INTR # is asserted, the CPU reads 14 subsequently the interrupt register 800 , determines which (it may be more than one) status signals STATUS [3: 0] caused the interrupt, and takes the serial interrupt signal SI_INTR # by writing a "1" to the bit or bits of the interrupt register 800 who have changed away.

The CPU 14 selectively selects interrupt requests caused by the status signals STATUS [31: 0] by writing a "1" to a corresponding bit of an interrupt mask register 810 with thirty-two bits mask. The CPU 14 Also, selectively, any byte of the status signals STATUS [47: 0] may be selectively written by writing a byte number of the selected byte to a serial input byte register 812 read. The SIO circuit 50 then transmits the desired byte to a serial data register 815 into it.

For example, to read the thirtieth byte (byte number two) of the status signals STATUS [23:16], the CPU writes 14 a "2" into the serial input byte register 812 , The serial scan input logic 804 then serially shifts byte two of the status signals STATUS [23:16] into the serial data register 815 into it. A busy status bit BS of the serial input byte register 812 is equal to "1" when the CPU 14 initially the desired byte count to the serial input byte register 812 writes. The bit BS is passed through the SIO circuit 50 deleted after the requested byte in the serial data register 815 has been moved into.

The CPU 14 can one of the slots 36 by writing a "1" to a corresponding bit of a slot enable register 817 boot up and the slot 36 by writing a "0" to this bit 14 one of the slots 36 by writing a "1" to a corresponding bit of a slot reset register 819 reset to default. The contents of the slot release 817 and the slot reset 819 Registers are represented by signals SLOT_EN [5: 0] and SLOT_RST_ [5: 0], respectively.

To initiate the request, indicated by the slot release 817 and reset 819 Register, initiate, writes the CPU 14 a "1" to an SO bit of a control register 814 , After the SO bit is asserted (which asserts a GO_UPDATE signal or goes high), the SIO circuit initiates 50 the required power-down and / or power-up sequences and controls them.

The serial scan input logic 804 is with ON / OFF control logic 820 connected, which controls the power-up and power-down sequences. The ON / OFF control logic 820 provides the signals BUSEN # [5: 0], CLKEN # [5: 0], RST # [5: 0] and PWREN [5: 0] to a serial output logic 824 ,

Each power-up and power-down sequence includes four shift phases during which another step of the power-down or power-up sequence is performed. During each shift phase, the ON / OFF control logic instructs 820 the serial output logic 824 to combine the control signals BUSEN # [5: 0], CLKEN # [5: 0], RST # [5: 0] and PWREN [5: 0]; to lock these signals; and serially supplies these signals (via a serial data signal CSOD_O) to the serial input of an output shift register 80 , At the end of each shift phase, the ON / OFF control logic instructs 820 the shift re gister 80 to update the control signals POUT [35:12].

The ON / OFF control logic 820 also interfaces with the register logic 808 and a control logic 822 connected to a light emitting diode (LED). The LED control logic 122 controls the on / off status of the six LEDs 54 that visually indicate if the appropriate levers 802 are locked or unlocked. The LEDs 54 may be programmed to flash when they are powered up via register control logic LED control registers (not shown) 808 ,

As in 31A includes the serial scan input logic 804 a scan state machine 840 controlling the sampling of the status signals STATUS [31: 0] for changes and shifting a selected byte of the status signals STATUS [47: 0] into the serial input byte register 815 into it.

The scan state machine 840 is clocked on the negative edge of a clock signal DIV2CLK, which is synchronized to a PCI clock signal CLK, and is one-half the frequency of the PCI clock signal CLK. The load and clock signals, CSIL_O_ and CSIC_O, respectively, are passed through the scan state machine 840 delivered. The clock signal, when enabled, is synchronized to the clock signal CSIC_O.

One bit / byte counter 841 indicates, via a thirty-two-bit signal BIT_ACTIVE [31: 0], which bit of the status signals STATUS [3: 0] is currently represented by the serial data signal NEW_CSID. The established bit of the signal BIT_ACTIVE [31: 0] has the same bit position as the status signal STATUS [31: 0], represented by the data signal NEW_CSID.

The counter 841 also supplies a three-bit signal BIT [2: 0] which represents which bit of the current byte of the status signals STATUS [31: 0] is currently being sampled by the scan state machine 840 is scanned. The counter 841 is clocked on the negative edge of a signal SHIFT_ENABLE. The outputs of the counter 841 are reset, or cleared when the output of an AND gate 842 , connected to the clear input of the counter 840 , is negated.

The scan state machine 840 provides a signal SCAN_IN_IDLE which, when asserted or asserted high, indicates that the scan state machine 840 is in an IDLE state and is not currently sampling any of the status signals STATUS [127: 0]. The signal SCAN_IN_IDLE is otherwise removed.

The signal SCAN_IN_IDLE becomes an input of the AND_gate 842 delivered. The other input of the AND gate 842 is with the output of an OR gate 843 connected. An input of the OR gate 843 receives an inverted HOLD_OFF signal, and the other input of the OR gate 843 receives a signal GETTING_BYTE.

The signal HOLD_OFF, when asserted or driven high, indicates that a change has been detected in the one of the status signals STATUS [5: 0] and the serial scan logic 804 has entered the slow-scan mode. In this slow scan mode, the serial scan input logic waits 804 to a predetermined slow-scan interval before the status signals STATUS [31: 0] are resumed. The serial scan input logic 804 counts the number of times that the serial scan signals STATUS [5: 0] are sampled during the slow scan mode, and uses that count to determine when one of the status signals STATUS [5: 0] remained unchanged for the debounce delay interval, as will be further described below.

Therefore, when the scan state machine 840 is in the IDLE state and either the HOLD_OFF signal is removed or the scan state machine 840 reading a selected byte (selected by the CPU 14 ) of the status signals STATUS [47: 0], all outputs of the counter 841 deleted or immediately set to zero.

The SHIFT_ENABLE signal is passed through the output of an AND gate 844 delivered. An input of the AND gate 844 picks up the clock signal CSIC_O. Another input of the AND gate 844 picks up a signal DIV2CLK #. Signal DIV2CLK # is asserted, or driven low, on the negative edge of signal CLKDIV4. The third input of the AND gate 844 receives a signal SCAN_IN_PROGRESS which, when asserted or driven high, indicates that the scan state machine 840 momentarily the status signals STATUS [127: 0] is scanning, and the signal SCAN_IN_PROGRESS is otherwise removed.

Therefore, when the scan state machine 840 does not move the status signals STATUS [127: 0], the counter 841 blocked. Furthermore, when enabled, the counter becomes 841 clocked on the negative edge of the clock signal DIV2CLK.

The interrupt register 800 receives input signals D_INTR_REG [31: 0] at their corresponding thirty-two inputs. The load enable inputs of the interrupt register 800 pick up appropriate load enable signals UPDATE_IRQ [31: 0]. The interrupt register 800 is clocked on the positive edge of the PCI clock signal CLK.

For purposes of keeping a log of status signals STATUS [5: 0] after each scan, provides a multi-bit, D-type flip-flop 836 Status signals SCAN_SW [5: 0]. The clear input of the flip-flop 836 picks up the reset signal RST, and the flip-flop 836 is clocked on the positive edge of the clock signal CLK. The entrance of the flip-flops 836 is at the output of a multi-bit OR gate 850 connected to an input to the output of a multi-bit AND gate 846 and an input to the output of a multi-bit AND gate 847 has connected. An input of the AND gate 846 picks up six bit enable signals BIT_ENABLE [5: 0] (described below) and the other input of the AND gate 846 picks up the serial data signal NEW_CSID. An input of the AND gate 847 receives inverted bit enable signals BIT_ENABLE [5: 0], and the other input of the AND gate 847 picks up the signals SCAN_SW [5: 0].

Only one of the bit enable signals BIT_ENABLE [5: 0] is asserted at a time (when the scan state machine 840 sampling), and the established bit indicates which one of the corresponding status signals STATUS [31: 0] is represented by the signal NEW_CSID. Consequently, when the scan state machine 840 samples, on each positive edge of the clock signal CLK, the signals SCAN_SW [5: 0] updated.

The bit enable signals BIT_ENABLE [31: 0] are passed through the output of a multi-bit multiplexer 832 which receives the bits BIT_ACTIVE [31: 0] at its one input. The zero input of the multiplexer 832 receives a thirty-two bit signal indicative of a logical zero. The selection input of the multiplexer 832 receives the signal SHIFT_ENABLE.

For purposes of detecting a change in the status signals STATUS [5: 0], provides a multi-bit, exclusive-OR (XOR) gate 848 Shift change signals SW_CHG [5: 0]. When one of the signals SW_CHG [5: 0] is asserted or high, the logic voltage of the corresponding status signal STATUS [5: 0] changed during successive scans. An input of the XOR gate 848 is with the input of the flip-flop 836 connected, and the other input of the XOR gate 848 receives the signals SCAN_SW [5: 0].

As in 31D For purposes of indication, when the logic voltage level of a selected status signal STATUS [5: 0] has remained at a logic voltage level for at least the duration of the debounce delay interval, it has the scan input -Logic 804 six signals LSWITCH [5: 0]. The non-inverting input of a flip-flop 900 the D-type signal is provided by LSWITCH [5] at its non-inverting output. The signal LSWITCH [5] is asserted or driven high to indicate the condition described above, and is otherwise removed. The flip-flop 900 is clocked on the positive edge of the clock signal CLK, and the clear input of the flip-flop 900 picks up the RST signal.

The entrance of the flip-flops 900 is with the output of a multiplexer 902 which provides a D_LSWITCH [5] signal. The selection input of the multiplexer 902 is connected to the output of an AND gate 903 connected receiving a MAX5 signal and a SCAN_END signal. The SCAN_END signal, when asserted, indicates that the scan state machine 840 whose current scan has completed. Five signals (MAX5, MAX4, MAX3, MAX2, MAX1 and MAX0) indicate whether the corresponding status signal is STATUS [5], STATUS [4], STATUS [3], STATUS [2], STATUS [1] or STATUS [0], respectively, remains at the same logical voltage level for at least the duration of the debounce time interval. The zero input of the multiplexer 902 receives the signal LSWITCH [5], and the one input of the multiplexer 902 receives the signal SCAN_SW [5]. The signal SCAN_END is passed through the output of an AND gate 851 delivered ( 31B ). The AND gate 851 receives a signal STOP SCAN and a signal SCAN_DONE. The STOP_SCAN signal is asserted or driven high when conditions for stopping sampling by the scan state machine 840 are present, as described further below. The signal SCAN_END is a pulsed version (for one cycle of the CLK signal) of the signal STOP_SCAN. The signals LSWITCH [4] -LSWITCH [0] and D_LSWITCH [4] -D_LSWITCH [0] are generated in a similar manner from the respective SCAN_SW [4] -SCAN_SW [0] signals and the respective signals MAX4-MAX0.

For update purposes, the logic voltage level of the status signals STATUS [31: 6] is keyed in as these signals, a multi-bit D-type flip-flop 905 ( 31D ) provides twenty-six signals SCAN_NSW [31: 6]. One of the signals SCAN_NSW [31: 6] is asserted, or driven high to indicate this condition, and is otherwise removed. The flip-flop 905 is clocked on the positive edge of the clock signal CLK and the clear input of the flip-flop 905 picks up the RST signal.

The entrance of the flip-flops 905 is with the output of a multi-bit multiplexer 906 connected. The selection input of the multiplexer 906 picks up an inverted CHECK_SWITCH_ONLY signal. The CHECK_SWITCH_ONLY signal is asserted or driven high when the scan state machine 850 only samples the status signals STATUS [5: 0] or the status signals STATUS [127: 32] (ie ignores changes in the signals STATUS [31: 6]) and otherwise removes them. The zero input of the multiplexer 906 receives the signals SCAN NSW [31: 6], and the one input of the multiplexer 906 is at the output of a multi-bit OR gate 907 connected. An input of the OR gate 907 is connected to the output of a multi-bit AND gate 908 connected, and the other input of the OR gate 907 is connected to the output of a multi-bit AND gate 872 connected.

An input of the AND gate 908 receives the signals BIT_ENABLE [31: 6]. The other input of the AND gate 908 is with the output of a multi-bit multiplexer 909 connected. If the NEW_CSID signal is asserted, or high, the multiplexer will deliver 909 Otherwise, the multiplexer will supply a signal of twenty-six bits equal to "0". An input of the AND gate 872 is with the inverted output of the AND gate 908 connected and the other input of the AND gate 872 picks up the signals SCAN_NSW [31: 6].

For purposes of storing the logic voltage level of the status signals STATUS [31: 6] after each scan provides a multi-bit D-type flip-flop 871 twenty-six signals LNON_SW [31: 6]. One of the signals LNON_SW [31: 6] is asserted, or set high to indicate this condition, and is otherwise removed. The flip-flop 871 is clocked on the positive edge of the clock signal CLK, and the clear input of the flip-flop 871 receives the RST signal.

The entrance of the flip-flops 871 is with the output of a multi-bit multiplexer 870 which supplies the signals D_LNON_SW [31: 6]. The selection input of the multiplexer 870 receives the signal SCAN_END. The zero input of the multiplexer 870 receives the signals LNON_SW [31: 6], and the one input of the multiplexer 807 receives the signals SCAN_NSW [31: 6].

As in 31B for purposes of generating the MAX0, MAX1, MAX2, MAX3, MAX4 and MAX5 signals, the serial input logic 804 six counters 831a - f , respectively, of a common design 831 , Every counter 831 is initialized (to a predetermined count value) when an AND gate 892 setting up its output, or heading for high. For the meter 831a receives the AND gate 892 the signal BIT_ENCABLE [0], the signal SW_CHG [0] and an inverted signal QUICK_FILTER. The signal QUICK_FILTER, if set up or high, can be used to bypass the debounce time interval. The QUICK_FILTER signal is normally removed or set low. The clock input of the counter 831 is connected to the output of an AND gate 893 connected. For the meter 831a receives the AND gate 893 the BIT_ENABLE [0] signal, the inverted SW_CHG [0] signal, the inverted GETTING_BYTE signal, and the inverted MAX0 signal. Therefore, for the counter 831a once the logic voltage of the status signal STATUS [0] changes, at any time when the serial scan logic changes 804 the status signal STATUS [0] is sampling, the counter 831a elevated. When the counter 831a reaches its maximum value, the signal MAX0 is asserted, indicating that the debounce time interval has expired. If the logic voltage of the status signal STATUS [0] changes during counting, the counter becomes 831a reinitialized, and counting starts again. The other counters 831b - f operate in a similar manner with respect to their corresponding status signals STATUS [5: 1].

The HOLD_OFF signal instructs one of the timers when it is set up 806 to measure a predetermined slow-scan interval comprising the serial scan state machine 840 placed in the slow-scan mode. If the timer 806 completes a measurement of this delay interval sets the timer 806 an FTR_TIMEOUT signal, or drives it high, which is otherwise removed, or negated. The product of this slow sample interval and the number of counts for the counter 831 to reach its maximum value is equal to the debounce time interval (8 ms).

The HOLD_OFF signal is through the output of a JK flip-flop 885 delivered. The flip-flop 885 is clocked on the positive edge of the CLK signal, and the clear input of the flip-flop 885 receives the RST signal. The J input is connected to the output of an AND gate 883 connected and the K input is connected to the output of an AND gate 884 connected. An input of the AND gate 884 is with the output of a flip-flop 896 connected by the JK-type, and the other input of the AND-gate 893 receives the SCAN_END signal. An input of the AND gate 884 is with the inverted output of the AND gate 883 connected, an input of the AND gate 884 receives the FTR_TIMEOUT signal, and another input of the AND gate 884 receives a SCAN_IN_IDLE signal which is asserted when the scan state machine 840 in its IDLE state, as described further below.

The flip-flop 895 is clocked on the positive edge of the CLK signal and the clear input of the flip-flop 895 receives the RST signal. The J input is at the output of a NAND gate 894 which receives the MAX0, MAX1, MAX2, MAX3, MAX4 and MAX5 signals. The K input is connected to the output of an AND gate 826 connected to the inverted J input of the flip-flop 895 and receives an inverted SCAN_IN_PROGRESS signal which is asserted when the scan state machine 840 the status signals STATUS [31: 0] is scanned.

For purposes of generating the CHECK_SWITCH_ONLY signal, the serial scan input logic includes 804 a flip-flop 864 of JK type providing the CHECK_SWITCH_ONLY signal at the non-inverting output, and is clocked on the positive edge of the CLK signal. The clear input of the flip-flop 864 receives the RST signal, and the J input of the flip-flop 864 receives a DEBOUNCE signal which, when asserted or driven high, indicates that one of the logic voltage levels has changed one or more of the status signals STATUS [31: 6]. The K input of the flip-flop 864 is connected to the output of an AND gate 865 connected. An input of the AND gate 865 picks up the inverted DEBOUNCE signal and an input of the AND gate 865 picks up the SCAN_IN_IDLE signal.

As in 31C is shown, the debounce signal DEBOUNCE by the non-inverting output of a flip-flop 860 supplied by the JK-type. The flip-flop 860 is clocked by the positive edge of the clock signal CLK, and the clear input of the flip-flop 860 receives the reset signal RST. The J input of the flip-flop 860 receives a CHANGE_ON_INPUT signal. The signal CHANGE_ON_INPUT is asserted or driven high when a change in one of the status signals STATUS [31: 6] at the end of a scan by the serial input logic 804 is captured, and is otherwise taken away. The K input is connected to the output of an AND gate 861 connected, which receives a DB_TIMEOUT signal at one of its inputs. The other input of the AND gate 861 picks up the inverted CHANGE_ON_INPUT signal. The DB_TIMEOUT signal is given by the timers 106 is asserted for one cycle of the CLK signal when the debounce time delay (initiated by the DEBOUNCE signal being asserted) has expired. Setting up the DB_TIMEOUT signal negates the DEBOUNCE signal on the next positive edge of the CLK signal.

The CHANGE_ON_INPUT signal is through the non-inverting output of a flip-flop 866 of the JK type clocked on the positive edge of the CLK signal. The clear input of the flip-flop receives the RST signal. The J input of the flip-flop 866 is connected to the output of an AND gate 869 connected, which receives the SCAN_END signal, and the other input of the AND gate 869 is with the output of an OR gate 867 connected. The OR gate 867 logically ORs all of a set of NSW_CHG [31: 6] signals. The bit positions of the signals NSW_CHG [31: 6] correspond to the bit positions of the status signals STATUS [31: 6] and indicate, by setting them up, whether the corresponding status signal STATUS [31: 6] is after the last scan has changed. The AND gate 869 continues to receive the SCAN_END signal. The K input of the flip-flop 866 is connected to the output of an AND gate 868 connected, the inverted SCAN_IN_PROGRESS signal and the inverted output of the AND gate 869 receives. The signals NSW_CHG [31: 6] are passed through the output of a multi-bit XOR gate 862 which receives the signals D_LNON_SW [31: 6] and LNON_SW [31: 6].

The non-inverting output of a multi-bit D-type flip-flop 912 returns bits SI_DATA [7: 0] for the serial data register 815 , The clear input of the flip-flop 912 receives the signal RST and the flip-flop 912 is clocked on the positive edge of the CLK signal. The signal input of the flip-flop 912 is with the output of a multi-bit multiplexer 916 connected. The selection input of the multiplexer 916 is connected to the output of an AND gate 914 connected, and the zero input of the multiplexer 916 takes the bits SI_DATA [7: 0]. The AND gate 914 picks up the signals GETTING_BYTE and SHIFT_ENABLE. As a result, when the serial scan logic 804 does not shift a requested byte of status signals STATUS [47: 0], which preserves the values of bits SI_DATA [7: 0].

The one input of the multiplexer 916 is with the output of a multi-bit multiplexer 910 connected. The one input of the multiplexer 910 is at the output of a multi-bit OR gate 911 connected, and the zero input of the multiplexer is connected to the output of a multi-bit AND gate 915 connected. The selection input of the multiplexer 910 receives the signal NEW_CSID.

An input of the AND gate 915 receives the bits SI_DATA [7: 0], and an inverting input of the AND gate 915 is with the output of a 3 × 8 decoder 913 connected. The decoder 913 receives the signal BIT [2: 0]. An input of the OR gate 911 receives the bits SI_DATA [7: 0], and the other input of the OR gate 911 receives the output of the decoder 913 ,

The serial input logic 804 supplies five signals RST_SWITCH [5: 0] (corresponding to the bit positions of the status signals STATUS [5: 0]) to the ON / OFF control logic 820 , which, by setting it up, indicates whether the corresponding slot 36a - f should be shut down. The ON / OFF control logic 820 indicates if the slot 36 (indicated by the RST_SWIITCH [5: 0] signals) has been shut down by the subsequent setting of one of five signals CLR_SWITCH [5: 0] whose bit positions correspond to the signals RST_SWITCH [5: 0]. Upon receiving the indication that the slot or slot 36 has shut down, takes the serial logic 804 then the corresponding RST_SWITCH [5: 0] signal back.

The signals RST_SWITCH [5: 0] are passed through the non-inverting output of a multi-bit flip-flop 891 D type ( 31B ) delivered. The clear input of the flip-flop 891 receives the reset signal RST and the flip-flop 891 is clocked on the positive edge of the clock signal CLK. The entrance of the flip-flops 891 is at the output of a multi-bit OR gate 857 connected to an input to the output of a multi-bit AND gate 859 has an input and the output of a multi-bit AND gate 855 has connected. An input of the AND gate 859 is with the output of a multiplexer 853 connected, and the other input of the AND gate 859 receives locked slot enable signals LSLOT_EN [5: 0], which indicate, by setting it up, whether the corresponding slot 36a - f has started up. An input of the AND gate 855 picks up the signals CLR_SWITCH [5: 0]. Another input of the AND gate 855 picks up the signals RST_SWITCH [5: 0]. Another input of the AND gate 855 is with the inverted output of the multiplexer 853 connected.

The zero input of the multiplexer 853 receives a six-bit signal that is indicative of zero. The one input of the multiplexer 853 is connected to the output of a multi-bit AND gate 849 connected. An input of the AND gate 849 receives the signals D_LSWITCH [5: 0], and the other input of the AND gate 849 receives the inverted signals L_SWITCH [5: 0]. The selection input of the multiplexer 853 receives the SCAN_END signal.

For purposes of generating the SI_INTR # signal, the serial scan logic includes 804 a flip-flop 882 of the D type which supplies the serial interrupt signal SI_INTR # at its inverting output. The flip-flop 882 is clocked on the positive edge of the CLK signal, and the clear input of the flip-flop 882 receives the RST signal. The entrance of the flip-flops 882 is with the output of an OR gate 881 which receives thirty-two pending interrupt signals PENDING_IRQ [31: 0] which, by asserting or driving high, indicate whether an interrupt is pending for the corresponding one of the status signals STATUS [31: 0]. The signals PENDING_IRQ [31: 0] are otherwise removed.

As in 31E is shown, provides a multi-bit flip-flop 979 D-type signals PENDING_IRQ [31: 0] at its non-inverting output. The flip-flop 979 is clocked on the positive edge of the signal CLK and receives the signal RST at its clear input. The entrance of the flip-flops 979 is connected to the output of a multi-bit AND gate 981 which receives inverted interrupt masking signals INTR_MASK [31: 0] at an input. The signals INTR_MASK [31: 0] are for a corresponding bit of the interrupt mask register 810 indicative. The other input of the AND gate 981 is at the output of a multi-bit OR gate 835 connected. An input of the OR gate 835 is connected to the output of a multi-bit AND gate 862 connected and the other input of the OR gate 835 is connected to the output of a multi-bit AND gate 834 connected.

The AND gate 862 picks inverted PENDING_IRQ [31: 0] signals and signals SET_IRQ [31: 0]. The signals SET_PIRQ [31: 0] are asserted to indicate that an interrupt request should be generated for the corresponding one of the status signals STATUS [31: 0]. Therefore, the signals PENDING_IRQ [31: 0] are updated with the signals SET_PIRQ [31: 0] if they are not masked by the signals INTR_MASK [31: 0].

The AND gate 834 receives the signals PENDING_IRQ [31: 0], inverted signals SET_PIRQ [31: 0] and inverted WR_INTR_REG [31: 0] signals. The signals WR_INTR_REG [31: 0] indicate the write data supplied by the CPU 14 to the interrupt register 800 out. The CPU clears an interrupt by writing a "1" to the corresponding bit of the interrupt register 800 , Therefore, if this occurs and no new interrupt requests for the corresponding one of the status signals STATUS [31: 0] are displayed, the corresponding one of the signals PENDING_IRQ [31: 0] is cleared.

The signals SET_PIRQ [31: 0] are passed through the output of a multi-bit AND gate 839 delivered. An input of the AND gate 839 receives the signals UPDATE_IRQ [31: 0]. The other input of the AND gate 839 is with the output of a multi-bit XOR gate 837 connected. An input of the XOR gate 837 receives the signals D_INTR_REG [31: 0], the other input of the XOR gate 837 receives the signals INTR_REG [31: 0]. Therefore, if the bits of the interrupt register 800 transition from one logical state to another, generates an interrupt request.

For purposes of updating the bits of the interrupt register 800 the signals UPDATE_IRQ [31: 0] become the corresponding load inputs of the register 800 delivered. If one of the UPATE_IRQ [31: 0] signals is asserted or driven high, the corresponding bit is loaded with the corresponding one of the D_INTR_REG [31: 0] signals.

The UPDATE_IRQ [31: 0] signals are passed through the output of a multi-bit OR gate 971 delivered. An input of the OR gate 971 is connected to the output of a multi-bit AND gate 973 connected. An input of the AND gate 973 is with the output of a multi-bit multiplexer 977 connected, and the other input of the AND gate 973 picks up inverted PENDING_IRQ [31: 0] signals. The selection input of the multiplexer 977 receives the signal SCAN_END, which is an input of the multiplexer 977 receives a thirty-two bit signal indicative of "hFFFFFFFF" and the zero input of the multiplexer 977 receives a thirty-two bit signal, indicative of "0." Therefore, at the end of a scan, UPDATE_IRQ [31: 0] signals enable the bits of the interrupt register 800 which correspond to the established PENDING_IRQ [31: 0] signals.

Another input of the OR gate 971 is connected to the output of a multi-bit AND gate 975 connected. An input of the AND gate 975 receives the inverted INTR_MASK [31: 0] signals, another input of the AND gate 975 receives the signals PENDING_IRQ [31: 0], and the other input of the AND gate 975 receives the signals WR_INTR_REG [31: 0]. That's why the CPU can 14 delete selective bits of the signals PENDING_IRQ [31: 0].

The signals D_INTR_REG [5: 0] are passed through the output of a multi-bit multiplexer 830 delivered. When the SCAN_END signal is asserted, the signals D_INTR_REG [5: 0] are equal to the signals D_LSWITCH [5: 0]. When the SCAN_END signal is removed, the signals D_INTR_REG [5: 0] are equal to the signals LSWITCH [5: 0].

The signals D_INTR_REG [31: 6] are passed through the output of a multi-bit multiplexer 845 delivered. When the SCAN_END signal is asserted, the signals D_INTR_REG [31: 6] are equal to the signals D_LNON_SW [31: 6]. When the SCAN_END signal is removed, the signals D_INTR_REG [5: 0] are equal to the signals LNON_SW [31: 6]. The interrupt register 800 picks up new values only if the signal SCAN_END is set up.

As in the 32A - B is shown, the scan state machine enters 840 in an IDLE state after setting the RESET signal RST. If it is not in the IDLE state, the scan state machine toggles 840 the states of the serial input clock CSIC_O to the shift register 82 to clock. Further, when not in a first loading state LD1, the scanning state machine 840 the load signal CSIL_O_ on or drives it high to the registers 82 and 52 to serially assert the status signals STATUS [127: 0] to the SIO circuit 50 to move. In the IDLE state, the scan state machine resets 840 the signal SCAN_DONE equal to zero.

The scan state machine 840 goes from the IDLE state to state LD1 when either the GETTING_BYTE signal is asserted or the HOLD_OFF signal is deasserted. Otherwise, the scan state machine remains 840 in the IDLE state. In the LD1 state, the scan state machine 840 the load signal CSIL_O_ on or drives it low, the registers 82 and 52 enables to lock and begin recording STATUS [127: 0] status signals.

The scan state machine 840 goes from the LD1 state to a charge two state LD2. In the LD2 state, the load signal CSIL_O_ is maintained asserted, giving the registers 82 and 52 allows the status signals STATUS [127: 0] to be shifted serially.

The scan state machine 840 subsequently goes to a scan state SCAN. In the SCAN state, the serial scan input logic is sampling 804 the status signals STATUS [127: 0] on each negative edge of the clock signal DIV2CLK. When the STOP_SCAN signal is asserted, the scan state machine goes 840 back to the IDLE state. The STOP_SCAN signal is asserted when either the desired byte of the status signals STATUS [127: 0] into the serial data register 815 has been moved into it; the lever status signals STATUS [5: 0] have been keyed in and the serial interrupt signal SI_INTR # has been asserted; or all status signals STATUS [31: 0] have been shifted into it. In the SCAN state, the SCAN_DONE signal is set equal to the STOP_SCAN signal.

As in 33A includes the ON / OFF control logic 820 an ON / OFF state machine 998 that receives the RST_SWITCH [5: 0] signals, SLOT_EN [5: 0], and SLOT_RST_ [5: 0]. Based on the states indicated by these signals, the ON / OFF state machine indicates 998 the appropriate start-up and shutdown sequences and controls them. The ON / OFF state machine 998 provides control signals to the control logic 999 ,

The ON / OFF state machine 998 supplies a serial output update signal SO_UPDATE to the serial output logic 824 , When the SO_UPDATE signal is asserted or driven high, the serial output logic begins 824 the shift phase and shifts serial control data to the register via the signal CSOD_O 80 , The serial output logic 824 indicates completion of the shift phase by asserting a signal SO_UPDATE_DONE by the ON / OFF state machine 998 Will be received. The ON / OFF state machine 998 subsequently updates the control signals POUT [39: 0] by negating, or clocking, the latch signal CSOLC_O passing through the register 80 Will be received.

The control logic 999 supplies the signals PWREN [5: 0], CLKEN # [5: 0], BUSEN # [5: 0] and RST # [5: 0] to the serial output logic 824 , The control logic 999 also supplies a PCI bus request signal CAYREQ # to and receives a PCI bus grant signal CAYGNT # from the arbitrator 124 , The ON / OFF control logic 820 sets the CAYREQ # signal or drives it low to the PCI bus 32 to request if the arbitrator 124 the signal CAYGNT # sets up or drives low, the arbitrator has 124 a controller via the PCI bus 32 to the ON / OFF control logic 820 granted.

As in the 33B - G is shown, the ON / OFF state machine enters 998 in an idle state IDLE by setting the reset signal RST on. If there is no idle, the ON / OFF state machine controls 998 one of three sequences: the power down sequence, the power on sequence, or the one pass sequence uses to update the control signals POUT [39: 0] as indicated by the slot enable signal. 817 and the LED control (not shown) register is displayed. The ON / OFF state machine 998 sets the load signal CSOLC_O for one cycle of the clock signal CLK of the register 80 on, or control it up, until the ON / OFF state machine 998 determines that the control signals POUT [39: 0] must be updated. When the control signals POUT [39: 0] are updated, the ON / OFF state machine negates 998 the signal CSOLC_O, which updates the control signals POUT [39: 0].

The ON / OFF state machine 998 The power-down sequence will begin when either the software shuts down or powers down at least one of the slots or slots 36 requests, as indicated by the removal of the signals SLOT_EN [5: 0]; or the serial scan input logic 804 determines that at least one of the slots or slots 36a - f should be subjected to the power-down sequence as indicated by setting up the RST_SWITCH [5: 0] signals. To start the power-down sequence, set the ON / OFF state machine 998 the SO_UPDATE signal to begin a shift phase and transitions from the IDLE state to an RSTON state.

During the RSTON state, the control logic negates 999 the reset signals RST # [5: 0] for the slots 36 which are to be powered down and the serial output logic 824 serially shifts the reset signals RST # [5: 0] to the output register 80 , The ON / OFF state machine 998 also negates the signal SO_UPDATE. Once every forty control signals through the serial output logic 824 to the register 80 are shifted, as indicated by the setting of the signal SO_UPDATE_DONE, the ON / OFF state machine goes 998 from the RSTON state to an OFF_ARB1 state.

In the OFF_ARB1 state, the ON / OFF state machine is requesting 998 a controller over the secondary PCI bus 32 by asserting the request signal CAYREQ #. The ON / OFF state machine 998 then goes to an OFF_WGNT1 state, where it waits for the grant of the secondary PCI bus 32 waiting. If the arbitrator 124 a control over the bus 32 as indicated by the assertion of the CAYREQ # signal negates the ON / OFF state machine 998 the signal CSOLC_O for one cycle of the signal CLK; to update the control signals POUT [39: 0], and goes to an OFF_LCLK1 state.

In the OFF_LCLK1 state, the ON / OFF state machine 998 signal SO_UPDATE to start another shift phase. The ON / OFF state machine 998 goes from the OFF_LCLK1 state to a bus-off state BUSOFF. During the BUSOFF state, the control logic is decreasing 999 the BUS enable signals BUSEN # [5: 0] for the slots 36 away or steers them to high, which should be shut down energetically, and the serial output logic 824 serially shifts the bus enable signals BUSEN # [5: 0] to the output register 80 , The ON / OFF state machine 998 also negates the signal SO_UPDATE. Once every forty control signals through the serial output logic 824 are shifted, as indicated by the setting of the signal SO_UPDATE_DONE, the ON / OFF state machine goes 998 from the BUSOFF state to an OFF_ARB2 state via where the state machine 998 again a check of the secondary PCI bus 32 requests. The state machine 998 then goes to an OFF_WGNT2 state where it waits for the grant of the PCI bus 32 waiting. Once the grant is received, the state machine goes 998 to an OFF_LCLK2 state where the control signals POUT [39: 0] are updated by negating the signal CSOLC_O for one cycle of the signal CLK. The state machine 998 then goes to a clock-off state CLKOFF.

During the CLKOFF state the control logic is decreasing 999 the clock enable signals CLKEN # [5: 0] for the slots 36 away, or steers you to high, which should be shut down by energy. The bus enable signals BUSEN # [5: 0] do not change, and the serial output logic 824 serially shifts the clock enable signals CLKEN # [5: 0] to the output register 80 , The ON / OFF state machine 998 also negates the signal SO_UPDATE. Once every forty control signals through the serial output logic 824 are shifted, as indicated by the setting of the signal SO_UPDATE_DONE, the ON / OFF state machine goes 998 from the CLKOFF state to an OFF_ARB3 state via where the state machine 998 again control over the PCI bus 32 requests. The state machine 998 then goes to an OFF_WGNT3 state where it waits for the grant of the PCI bus 32 waiting. Once the grant is received, the state machine goes 998 to an OFF_LCLK3 state where the control signals POUT [39: 0] are updated by negating the signal CSOLC_O for one cycle of the signal CLK. The state machine 998 then goes to a power off state PWROFF.

During the PWROFF state, the control logic is decreasing 999 the power enable signals PWREN [5: 0] for the slots 36 away or set them low, which should be shut down by energy. The signals REST # [5: 0], BUSEN # [5: 0] and CLKEN # [5: 0] do not change, and the serial output logic 824 serially shifts the power enable signals PWREN [5: 0] to the output register 80 , The ON / OFF state machine 998 also negates the signal SO_UPDATE. Once every forty control signals through the serial output logic 824 are shifted, as indicated by the setting of the signal SO_UPDATE_DONE, the ON / OFF state machine goes 998 from the PWROFF state to an OFF_LCLK4 state, where the signals POUT [39: 0] are updated by negating the signal CSOLC_O for one cycle of the signal CLK. The state machine 998 then goes to the IDLE state which completes the power-down sequence.

If a power-down sequence is not required, then the ON / OFF state machine determines 998 whether the power-up sequence is required. If either the software has at least requested that at least one of the slots 36 energized to be raised, or booting the expansion box 30 is pending, then goes the ON / OFF state machine 998 from the IDLE state to a power-on PWRON state to begin the power-on sequence. To the power-on sequence To start, set the ON / OFF state machine 998 the SO_UPDATE signal to start a shift phase, and transitions from the IDLE state to a power-on state PWRON.

During the PWRON state, the control logic sets 999 the power enable signals PWREN [5: 0] for the slots 36 which are to be powered up and the serial output logic 824 serially shifts the power enable signals PWREN [5: 0] to the output register 80 , The ON / OFF state machine 998 negates, also the signal SO_UPDATE. Once every forty control signals through the serial output logic 824 are shifted, as indicated by the setting of the signal SO_UPDATE_DONE, the ON / OFF state machine goes 998 from the PWRON state to an initialization state LDCNT1 of a timer 806 Over and negates the load signal CSOLC_O to update the control signals POUT [39: 0].

In the LDCNT1 state, the ON / OFF state machine initializes 998 the timers 806 so that the timers 806 provide an indication when a predetermined stabilization delay interval has expired. The stabilization delay interval allows sufficient time for the card 807 which is to be powered up to stabilize, once the voltage level V _ss to the card 807 is supplied. In the LDCNT1 state, the ON / OFF state machine 998 also the signal CSOLC_O on. The ON / OFF state machine 820 goes from the LDCNT1 state to a CLKON state.

During the CLKON state, the control logic sets 999 the clock enable signals CLKEN # [5: 0] for the slots or slots 36 on or low on, which are to be powered up by energy. The PWREN [5: 0] signals remain unchanged, and the serial output logic 824 serially shifts the clock enable signals CLKEN # [5: 0] to the output register 80 , The ON / OFF state machine 998 also negates the signal SO_UPDATE. Once the stabilization delay interval has elapsed, the ON / OFF state machine goes off 998 from the CLKOFF state to an ON_ARB1 state.

In the ON_ARB1 state, the ON / OFF state machine is requesting 998 control over the secondary PCI bus 82 by asserting the request signal CAYREQ #. The ON / OFF state machine 998 then goes to an ON_WGNT1 state where it waits for the grant of the secondary PCI bus 32 waiting. If once the control or control of the bus 32 is issued, as indicated by the setting up of the CAYGNT signal, negates the ON / OFF state machine 998 the signal CSOLC_0 to update the control signals POUT [39: 0], and goes to an ON_LCLK1 state where the signals POUT [39: 0] are updated.

The ON / OFF state machine 998 goes from the ON_LCLK1 state to an LDCNT2 state where the timers 806 be initialized so that the timers 806 provide an indication when another, predetermined stabilization delay interval has expired. This delay interval is used to match the clock signal on the card 807 to be powered up to stabilize before the power-up sequence continues. The ON / OFF state machine 998 goes from the LDCNT2 state to a bus on state BUSON.

During the BUSON state, the control logic sets 999 the bus enable signals BUSEN # [5: 0] for the slots 36 on or low on, which should be shut down by energy. The signals CLKEN # [5: 0] and PWREN [5: 0] remain unchanged, and the serial output logic 824 serially shifts the bus enable signals BUSEN # [5: 0] to the output register 80 , The ON / OFF state machine 998 also negates the signal SO_UPDATE. Once the stabilization delay interval has elapsed, the ON / OFF state machine goes off 998 from the BUSON state to an ON_ARB2 state via where the state machine 998 again a check of the PCI bus 32 requests. The state machine 998 then goes to an ON_WGTN2 state, where it is on issuing the bus 32 waiting. Once the grant is received, the state machine goes 998 to an ON_CLK2 state where the signals POUT [39: 0] are updated by negating the signal CSOLC_O for one cycle of the signal CLK. The state machine 998 then goes to a reset-off state RSTOFF over.

During the RESTOFF state, the control logic sets 999 the reset signals RST # [5: 0] for the slots 36 on or negates them, which are to be powered up, depending on their respective SLOT_RST_ [5: 0] signals. The signals CLKEN # [5: 0], PWREN [5: 0] and BUSEN # [5: 0] remain unchanged, and the serial output logic 824 serially shifts the reset signals RST # [5: 0] to the output register 80 , The ON / OFF state machine 998 also negates the signal SO_UPDATE. Once every forty control signals through the serial output logic 824 are moved, as by putting up of the signal SO_UPDATE_DONE is indicated, the ON / OFF state machine goes 998 from the RSTON state to an ON_ARB3 state over where the state machine 998 again a check of the bus 32 requests. The state machine 998 then goes to an ON_WGTN3 state, where it is on issuing the bus 32 waiting. Once the grant is received, the state machine goes 998 to an ON_CLK3 state where the signals POUT [39: 0] are updated by negating the signal CSOLC_O for one cycle of the signal CLK. The state machine 998 then go back to the IDLE state.

If neither the power-up sequence nor the power-down sequence is required, then the ON / OFF state machine determines 998 whether a one-pass sequence is needed to update selected ones of the signals POUT [39: 0]. If the GO_UPDATE signal is asserted and if any bits of the slot enable register 817 or the slot reset register 918 change, then go the ON / OFF state machine 998 to an ONEPASS state and sets the SO_UPDATE signal.

The ON / OFF state machine 998 remains in the ONEPASS state until the forty control signals to the register 80 have been moved. The ON / OFF state machine 998 then goes to an OP_ARB state where the state machine 998 a control of the PCI bus 32 by requesting the signal CAYREQ #. The state machine 998 then goes to an OP_WGNT state, where it is on issuing the bus 32 waiting. Once the grant is received, the state machine goes 998 to an OP_LCLK state where the signals POUT [39: 0] are updated by negating the signal CSOLC_O for one cycle of the signal CLK. The state machine 998 then go back to the IDLE state.

As in 34 includes the serial output logic 824 a shift output bit counter 921 which provides a six bit counter output signal BIT_CNTR [5: 0] which logs the control signal from the serial output logic 824 shifted out via the signal CSOD_O. If the signal BIT_CNTR [5: 0] is equal to "39" equal to a six digit number, then a MAX_CNT signal is asserted, and the MAX_CNT signal becomes the input of an AND gate 922 delivered. The AND gate 922 also receives a signal SHIFT4 which is asserted when the output shift state machine 920 in the SHIFT4 state, which is described further below. The output of the AND gate 922 supplies the signal SO_UPDATE_DONE.

The output shift state machine 920 provides an increment counter signal INC_CNTR to the bit counter 921 , When the INC_CNTR signal is asserted, the bit counter increases 921 the value represented by the signal BIT_CNTR [5: 0]. When a load counter signal LOAD_CNTR is asserted or when the RST signal is asserted, the output of an OR gate clears 925 , connected to a clear input of the bit counter 921 , the signal BIT_CNTR [5: 0].

The signal BIT_CNTR [5: 0] becomes the select input of a multi-bit multiplexer 924 supplied, which provides the signal CSOD_O. The zeroth to eleventh input of the multiplexer 924 receive the LED control signals LEDS [11: 0]. The twelfth to fifteenth input of the multiplexer 924 receive output signals GPOA [3: 0] for general purpose. The sixteenth to twenty-first inputs receive the reset signals RST # [5: 0]. The twenty-second to twenty-seventh inputs receive the clock enable signals CLKEN # [5: 0]. The twenty-eighth to thirty-third inputs receive the bus enable signals BUSEN [5: 0]. The thirty-fourth to thirty-ninth inputs receive the power enable signals PWREN [5: 0].

As in the 35A - B is shown, the output shift state machine enters 920 in an IDLE state when the RST signal is asserted. If the SO_UPDATE signal is asserted, then the output shift state machine goes 920 from the IDLE state to a SHIFT1 state.

Since the output shift state machine 920 is clocked on the positive edge of the PCI clock signal CLK, the output shift state machine goes 920 via a SHIFT1 state, a SHIFT2 state, a SHIFT3 state, and a SHIFT4 state to produce the clock signal CSOSC_O that is one quarter of the frequency of the clock signal CLK. During the SHIFT1 and SHIFT2 states, the clock signal CSOSC_O is negated and set low, and during the SHIFT3 and SHIFT4 states, the clock signal CSOSC_O is asserted or set high. When the current shift phase is completed, as indicated by the assertion of the MAXCNT signal, the shift state machine returns 920 to the IDLE state and the clock signal CSOSC_O is asserted until the beginning of the next shift phase.

As in 36 is shown, a signal HANG_PEND by the clear input of the register 80 receive. Setting up, or driving high, of the HANG_PEND signal asynchronously clears the appropriate output control signals POUT [39: 0] to all slots 36 shut down energetically when the PCI bus 32 is in a locked state, as further described below.

FAULT ISOLATION

The bus observer or watcher 129 may be a faulty or hanging state on the secondary PCI bus 32 to capture. If a hanging condition is detected, the bus observer issues 129 a Bus Hanging Pending bit which causes the SIO 50 the slots or slots on the secondary PCI bus 32 power down, and a Non-Maskable Interrupt (NMI) becomes the CPU 14 transfer. The CPU 14 Reaches the NMI by invoking an NMI program to isolate the slot (s) causing the hanging state. Once the defective slot (s) are identified, they are disabled or turned off by the power.

For software diagnostic purposes, the bus observer includes 129 in the output side bridge chip 48 a bus history FIFO and a bus vector FIFO. If the secondary PCI bus 32 works properly, the bus history information, which is an address group (comprising the PCI address, the PCI command signals, the PCI master number and the address parity bit) and a data group ( comprising the PCI data, the byte enable signals C / BE [3: 0] _, a parity error signal PERR_, the data parity bit, a burst cycle indication bit, and a data validity Sign) by the bus watcher 129 recorded at every transaction. If the PCI signal is FRAME_ on the secondary PCI bus 32 is set up to start a bus transaction, the address group and each subsequent data group are stored in the Bus Hinstorie FIFO. If the transaction is a burst transaction, then the burst cycle indication bit is set active in the second data phase. After the first data phase, the address field in the address group associated with the subsequent data group in the burst transaction is incremented by four, and the new address group and data group are stored in the next location of the bus random FIFO , If data is not transmitted because there is a retry state or a no-interrupt state, the validity data indication bit is set low.

Both the address group and the data group flow through a 2-stage pipeline to allow time for the data group to collect the data parity bit and the data parity error bit, and the Stop recording if a data parity error occurs before the next address group is saved. If the bus hangs in the middle of a write data phase, the data is stored and a bus hanging status bit is placed in a bus hang indication register 482 ( 42 ), accessible via a Kofigurations room, set. If the bus hangs in the middle of a read data phase, the data is marked invalid and the bus hanging bit is set.

Bus state vectors are compiled and stored in the bus vector FIFO, comprising the following PCI control signals: slot request signals REQ [7: 0] _; Slot grant signals GNT [7: 0] _; the FRAME_ signal; the PCI device selection signal DEVSEL_; the PCI initiator ready signal IRDY_; the PCI target ready signal TRDY_; the stop_ signal; the PCI parity error signal PERR_; the PCI system error signal SERR_; and the LOCK_ signal. At every PCI clock, in which the Bus State Vector changes, d. H. any of the listed ones; Signals changes a state, the new Vector cached in the Bus Vector FIFO.

The bus watcher 129 includes a watchdog timer 454 ( 40 ) to determine if the secondary bus 32 has locked. If the watchdog timer 554 expires, then the bus has 32 hung. The following are examples of bus hanging states that are triggered by the watchdog timer 454 can be detected: the FRAME_ signal is set high or low; the signal TRDY_ is not established in response to IRDY_; the PCI arbitrator 124 do not give the bus to any master; and a master who drives the bus 32 request, keep trying.

If the watchdog timer 454 expires, the Bus Hanging Pending bit becomes active in the Bus Hanging Indication Register 482 set. If the Bus Hanging Pending bit is set active, there is the Bus Watcher 129 free. Next, the slot enable bits in the SIO 50 cleared, which causes the slots to be shut down by energy. The SIO 50 then sets the system error signal SERR_.

To isolate the cause of a bus hanging condition, the system error signal SERR_ causes the interrupt logic in the system to move the NMI to the CPU 14 outputs. As 37 shows, the NMI handler first determines 400 Whether the Bus Hanging Pending bit is set by reading the Hanging Bus Indication Register 482 , If so, the NMI handler calls, 401 , a BIOS isolation handler for isolating the defective slot or slots. Otherwise, other NMI procedures are called, 402 ,

As an error-security mechanism, the computer system also includes the automatic server recovery (ASR) timer 72 which is cleared when certain software programs are executed by the operating system. If the ASR timer expires (for example, after 10 minutes), it indicates that the operating system has locked. The secondary PCI bus 32 Hanging can be the cause of the system lock, in which case the NMI never goes to the CPU 14 can go. If the ASR timer expires, then an ASR-generated reboot occurs. The ASR timer also ensures that if the BIOS isolation handler is in the middle of isolation of an error slot on the PCI bus 32 In order to cause an ASR reboot, the isolation program may hang and the computer system hangs on where it was left just before the ASR time-out event.

As 38 indicates a BIOS ASR handler is called in response to an ASR reboot state. The ASR handler first checks 444 to determine if an isolation in progress event variable (EV) contains active information indicating that the isolation process was in progress prior to the ASR time out event. Isolation-In-Progress-EV is stored in non-volatile memory (NVRAM) 70 and includes header information that is set to active to indicate that the isolation process has started. The isolation-in-progress EV is also updated with the current state of the isolation process, including the slots that have been tested, the slots that are broken, and the slots that have been released.

If the isolation process was in progress, the BIOS ASR handler releases all slots again, 448 with the exception of those released immediately prior to the ASR event, which is determined from the isolation in progress EV. The released slots prior to the ASR reboot were probably the cause of the ASR review. As a result, these slots are disabled (ie powered down). Next, the numbers of locked slots are logged as error status information, 450 stored in the NVRAM and the isolation in progress EV is cleared. The BIOS ASR handler then checks 452 to determine if the Bus Hanging Pending bit is set. If so, the Bus Hanging Pending bit is cleared (performing an I / O cycle on the secondary PCI bus 32 ) to the bus watcher 129 release again.

If the isolation in progress EV is not set to the active state, 444 Indicating that the isolation process was not running when the ASR event occurred, the program checks 446 to determine if the Bus Hanging Pending bit is set. If not, then the BIOS ASR handler is made. If the Bus Hanging Pending bit is set, 446 indicating that a bus-hang condition has occurred prior to the ASR event, the BIOS ASR handler calls the BIOS isolation handler to isolate the error slot or slots.

As 39 shows, the isoaltion handler first logs 408 to the error status information area of the NVRAM, the bus history and bus state vector information stored in the history and vector FIFOs in the bus monitor 127 , The bus history and bus state vector FIFOs are read and their contents are transferred to the NVRAM. Next, the header information of the isolation-in-progress event variable is set, 410 to indicate that the isoaltion process is progressing. The bus hanging pending bit is cleared (by writing to a predetermined configuration address) to the bus watcher 129 release again. Next, the isolation program releases the first occupied slot (ie, a slot to which a PCI device is connected) (ie, powers it up), 412 , and reads and writes from the PCI configuration space of the device. A slot is written to the slot enable register 817 ( 29 ) released again. Next, the program determines 414 Whether the Bus Hanging Pending bit is set active, indicating that the device connected to the slot caused the bus to hang while reading from it. If this is not the case, the program determines 416 whether all occupied slots have been checked. If this is not the case, the first, occupied slot, locked, 418 , and the isolation-in-progress EV is updated, 420 to indicate that the first occupied slot has been retried by the BIOS isolation handler. If the program certainly, 414 in that the Bus Hanging Pending bit is set active, the slot is indicated as failed (eg, by setting active to a Failure Flag for that slot) in the Failure Status Information Area of the NVRAM. Next, the loop that comes out of the steps 412 . 414 . 416 . 418 and 420 completed until all occupied slots have been tested.

If all occupied slots have been checked, 416 , the program will carry out an examination 424 to determine if any slot is indicated as failed in the failure status information area of the NVRAM. If this is the case, the program returns 398 again only the non-failed slots free, 426 , Then the isolation in progress EV is cleared, 428 and the BIOS isolation program will complete.

If none of the slots are indicated as failed, 424 , then this indicates that the bus hanging state has not been caused by a single slot but may be caused by more than one device active at that same time. To confirm this, the BIOS isolation handler first locks all slots (ie shuts them down by power), 430 , and updates the isolation-in-progress EV with this information. Next, the BIOS Isolation Handler clears 431 a count variable N to 0 and sets a count variable I to the value of N. The count variable N represents the count of occupied slots.

The BIOS isolation handler again releases the occupied slot I (which is initially slot N) (ie, energizes it up), 432 , and reads and writes to this PCI configuration space. The handler then checks 438 to determine if the Bus Hanging Pending bit is set. If this is not the case, the handler decreases 433 the variable I and checks 434 whether the variable I is greater than or equal to zero. If so, the handler updates 435 the isolation-in-progress EV and release the next, occupied slot I again, 432 , and reads and writes with this. The handler then checks 438 Whether the Bus Hanging pending bit is set for this next slot. In this way, for each slot N to be released, the previously enabled slots are also powered up, one at a time, to determine whether a combination of slots is causing the error.

If variable I is determined to 434 that it is less than zero, then checks the handler 436 to determine if all occupied slots have been released. If this is not the case, the variable N is increased, 437 , the isolation-in-progress EV is updated, 439 , and the variable I is reset, 441 , equal to the value of N.

If the Bus Hanging Pending bit is set active, 438 , then potentially two slots are blocked, 440 Slot N (which is the slot currently enabled) and slot I (which is the slot from which is currently being read and to which is currently being written). If the values of I and N are the same, then only slot N is disabled.

If the handler determines 436 that all occupied slots have been freed (and an error could not be identified), then the handler lures the NVRAM to its inability to 442 to isolate the error. Next, the handler clears 428 the isolation-in-progress EV.

As 40 shows, provides the watchdog timer 454 Output signals WD_TMR_OUT [17: 0] (timer count value), HANG_PEND (bus suspended state is present), EN_CAP (the bus vector history information detection software is enabled), TIME_OUT (the watch -Dog timer 454 has expired), a signal HANG_RCOVR_EN (set high by the software to the hang recovery logic in the bus watcher 129 and in the SIO 50 release), and a signal CAP_ILLEG_PROT (to an illegal cycle on the PCI bus 32 display).

The signal HANG_PEND becomes the SIO 50 delivered to close the secondary bus slots. The input signals to the watchdog timer 454 For example, some of the PCI bus signals include a signal WRT_EN_CAP_1 (pulsed high by the software to again detect the bus history and bus vector information through the error isolation block 129 release) and an energy good indicator signal SYNC_POWEROK (indicating that power to the computer system is stable).

A Bus Hanging Recovery Condition Machine 456 receives the signals HANG_PEND, TIME_OUT and HANG_RCOVR_EN from the watchdog timer 454 , The Recovery State Machine 456 also receives some of the PCI signals. The output signals from the Bus Hanging To recovery state machine 456 comprise a device select signal DEVSEL_O for driving the PCI signal DEVSEL_, a signal STOP_O for driving the PCI signal STOP_, a signal SERR_EN enabling a setting of the system error signal SERR_, a signal BR_M_ABORT (indicating that is the bus watcher 129 with a master abort has restored) a signal BR_T_ABORT indicating that the bus watcher 129 with a target abort), and a signal RCOVR_ACTIVE (to indicate when the Bus Hanging Recovery State Machine 456 is active). The Bus Hanging Recovery State Machine 456 Make sure the secondary PCI bus 32 is returned to the idle state to allow the software to isolate the error slot. When the hang state is detected, the ISO moves 50 the secondary bus slots down, which automatically disconnects the bus 32 in the idle state if one of the slot devices was the bus master when the hang state occurred. However, if one of the slot devices was the target (and the bridge chip 48 the master was), if the bus hang occurred, then the bridge chip 48 remain on the bus. To take the bridge chip out of the bus, the recovery state machine is forced 456 one cycle for a retry on the PCI bus 32 by setting up the signal STOP.

A bus history capture block 458 monitors the PCI bus 32 in terms of transactions, and supplies the bus history information (including the address and the data) to output signals BUS_HIST_DATA3 [31: 0] (the bus history address), BUS_HIST_DATA2 [31: 0] (the bus history). Data) and BUS_HIST_DATA1 [15: 0] (parity error signal! PERR_, parity bit PAR, validity data bit VALID_DAT, address parity bit ADDRPAR, burst indicator BURST, master number MASTER [2: 0], byte enable bits CBE [3: 0] _, and command bits CMD [3: 0]). The Bus History Collection Block 458 asserts a HIS_RDY signal if data is available on the BUS_HIST_DATA signals, which is the case at the end of each data phase in a normal transaction, or if the transaction is terminated with a master retirement, a retry during the setup of the time-out signal TIME_OUT.

A bus vector detection block 460 detects the states of certain PCI control signals when any of these control signals changes state. The vector is detected and output as the signal BUS_VECT_DATA [20: 0], which inputs the request signals! REQ [7: 0] _, grant signals! GNT [7: 0] _, a time-out signal TIME_OUT Interlock signal LOCK_, a system error signal SERR_, a parity error signal PERR_, a stop signal STOP_, a target ready signal TRDY_, an initiator ready signal IRDY_, a device selection signal DEVSEL_ and a frame signal FRAME_ included. The Bus Vector Detection Block 460 sets a signal VECT_RDY if any bus vector BUS_VECT_DATA [24: 0] has changed or the watchdog timer 454 has expired (TIME_OUT is high).

The Bus history and bus vector signals are the inputs of a Bus-Watcher FIFOs presents, this includes a 2 deep bus history FIFO and a 4 deep vector history FIFO includes. The exits the bus history FIFOs are output as signals BUS_HIST_REG1 [31: 0], BUS_HIST_REG2 [31: 0] and BUS_HIST_REG3 [31: 0]. The exits of the vector history FIFO are presented as signals BUS_VECT_REG [3: 0]. The system software reads the outputs of the bus history FIFO Generating an I / O read cycle which causes a signal BUS_HIST_RD1 is set up, and reads the outputs of the vector FIFO Generating an I / O read cycle that causes a signal BUS_VECT_RD to be asserted becomes.

As 41 shows, the recovery state machine starts 456 in a state IDLE when the signal SYNC_POWEROK is set low, indicating that energy is still stable until now. The state machine remains in an IDLE state while the HANG_PEND signal is low. In state IDLE, signals BR_M_ABORT, BR_T_ABORT and RCOVR_ACTIVE are set low. The signal RCOVR_ACTIVE is active high in the other states WAIT, ABORT and PEND_OFF. If the SET_HANG_PEND signal is set high, the state machine transitions to a WAIT state. In the transition, the signal DEVSEL_O is set equal to the inverted state of the device select signal DEVSEL_. This ensures that when the device select signal DEVSEL_ is asserted by a target before the bus hang state, the recovery state machine 456 maintains the signal DEVSEL_ situated. In state WAIT, signal DEVSEL_O is set equal to the state of signal DEV_SEL_WAS, which is set high if signal DEVSEL_ is asserted by a target before the state machine transitions to the WAIT state.

From state WAIT goes the Bus Hanging Recovery State Machine 456 to the PEND_OFF state if a signal PCI_IDLE is asserted, indicating that the PCI bus 32 to a Idle has passed (ie signals FRAME_ and IRDY_ are both high). At the transition, the signal BR_M_ABORT is set high to indicate that one of the slot devices was the master before the hang state, and the slot device is powered down due to the PCI bus going to an idle state , A signal SERR_EN is also asserted high to enable assertion of the system error signal SERR_ or if INTA_ is enabled.

If a slot device was a target before the bus hanging state, then the bus master will be on the PCI bus 32 remain. To get the bus master out of the PCI bus 32 Issue the Bus Hanging Recovery State Machine 456 a retry on the PCI bus 32 out. A counter 457 counts a predetermined number of PCLK periods (eg, 15 PCLK periods) after the HANG_PEND signal is asserted high. The 15 PCLK periods ensure sufficient rise time on FRAME_ and IRDY_ to give the signals time to go back to their idle states. If 15 PCLK periods have expired, the counter represents 457 the signal TIME_OUT15 on. If the signal TIME_OUT15 is set high and the signal PCI_IDLE remains low, then the state machine transitions from a state WAIT to a state ABORT. During the transition, the signal STOP_O is set high in order to activate the PCI STOP_ signal to active in order to retry the bus master. The state machine remains in an ABORT state while the bus master keeps the FRAME_ signal low. In the ABORT state, the STOP_O signal is kept high. Once the bus master retires the FRAME_ signal in response to the retry state, the state machine transitions from an ABORT state to a PEND_OFF state. At the transition, the signal BR_T_ABORT is set high to indicate that the target abort was necessary after the bus hang state to the bus 32 to place in the idle state. The SERR_EN signal is also asserted high to enable assertion of the SERR_ signal or if INTA_ is enabled. The state machine remains in state PEND_OFF until the signal WRT_EN_CAP_1 has been asserted high, at which time it goes back to state IDLE.

The System software can detect the value of BR_M_ABORT and BR_T_ABORT signals read to determine if the. Slot Device, included in the bus-hanging state, was a master device or a slave device.

As 42 shows includes the watchdog timer 454 an 18-bit LSFR counter 464 which is clocked by the signal PCLK. The counter 464 is released when the output of an AND gate 467 is set high, which occurs when a new master issues a request (ANY_REQ is high), the bus cycle is started (signals FRAME_ and TRDY_ are both asserted), the enable detect signal EN_CAP is asserted, and Signal TIME_OUT is low. An OR gate 466 receives the signal ANY_REQ and the inverted states of signals FRAME_ and IRDY_. The AND gate 467 receives the output fo of the OR gate 466 , the signal EN_CAP and the inverted state of the signal TIME_OUT. The output of the counter controls signals WD_TMR_OUT [17: 0] and is cleared when a time-out condition is detected (TIME_OUT is high), a data transfer has occurred (both signals IRDY_ and TRDY_ are set low), or all output -Bits of the counter 464 are high (which is an illegal state). The clear state is through an OR gate 470 which receives the signal TIME_OUT, the bitwise AND (AND) of the signals WD_TMR_OUT [17: 0] and the output of an AND gate 472 , The inputs of the AND gate 472 pick up the inverted state of the signal IRDY_ and the inverted state of the signal TRDY_.

The TIME_OUT signal goes high through a time-out detector 474 is set when the timer signals WD_TMR_OUT [17: 0] become the binary value 1000000000000000. The signal TIME_OUT becomes an input of an OR gate 476 whose output is connected to the input of an AND gate 478 connected is. The other input of the AND gate 478 picks up the inverted state of a WRT_EN_CAP_1 signal (controlled by software to allow bus history and bus vector capture again), and its output goes to the D_input of a flip-flop 488 connected by the D-type. The flip-flop 488 is clocked by the signal PCLK and drives an output signal WD_TIME_OUT which goes back to the other input of the OR gate 476 is supplied. The flip-flop 488 is cleared when the power good signal SYNC_POWEROK is negated. As a result, an ASR reset does not clear the WD_TIME_OUT signal.

The HANG_PEND signal is passed through a flip-flop 482 of the D-type set high, whose D input to the output of an AND gate 484 is connected and which is clocked by the signal PCLK. An input of the AND gate 484 is at the output of an OR gate 486 connected, and his other one gear receives the inverted state of the signal WRT_EN_CAP_1. An input of the OR gate 486 is connected to the HANG_PEND signal and the other input is to the output of an AND gate 488 connected. The inputs of the AND gate 488 receive the signal TIME_OUT and the enable signal HANG_RCOVR_EN. As a result, if the system software releases a bus hanging recovery (HANG_RCOVREN is high), then a time out condition will cause the HANG_PEND signal to be asserted high. The HANG_PEND signal is cleared when the system software causes the WRT_EN_CAP_1 signal to assert (performing an I / O cycle on the bus 32 ), or if the signal SYNC_POWEROK is negated. The HANG_PEND bit is not negated by an ASR reboot.

The enable detection signal EN_CAP is passed through a flip-flop 490 generated by the D-type whose D input the output of an AND gate 492 receives. An input of the AND gate 492 is with the output of an OR gate 494 and its other input is connected to the inverted state of a signal CLR_EN_CAP. An input of the OR gate 494 is fed back to the signal EN_CAP and the other input receives the signal WRT_EN_CAP_1. The flip-flop 490 is clocked by the signal PCLK and set high when the signal SYNC_POWEROK is set low. Once the signal EN_CAP is set high by the software via the signal WRT_EN_CAP_1, it is kept high. The CLR_EN_CAP signal is asserted to clear the EN_CAP signal (Disable Capture of Information), which occurs when a timeout has occurred (TIME_OUT is high), a system error has occurred is (SERR_ is low), a parity error has occurred (PERR_ is low), or an illegal bus protocol has been detected (CAP_ILLEG_PROT is high).

The signal CAP_ILLEG_PROT is triggered by a flip-flop 483 generated by the D-type whose D input the output of an AND gate 485 receives. One input of the AND gate receives the inverted state of the signal WRT_EN_CAP_1, and the other input receives the output of an OR gate 487 , The OR gate 487 receives the signals CAP_ILLEG_PROT and SET_ILLEG_PROT. The signal SET_ILLEG_PROT is then asserted when a capture is enabled (EN_CAP is high), the state machine 456 is not active (RCOVR_ACTIVE is low), the bus is idling and any signals DEVSEL_, TRDY_ or IRDY_ are set low. This state is an illegal state that triggers logging of bus history and bus vector information.

As 43 shows, the bus history standby signal HIST_RDY by a flip-flop 502 generated by the D-type, which is clocked by the signal PCLK and cleared by the signal RESET. The D input of the flip-flop 502 is with the output of an OR gate 504 whose inputs are the signal TIME_OUT, a signal M_ABORT (master abort signal, delayed by a PCLK), the output of an AND gate 506 and the output of an AND gate 508 take up. The AND gate 506 asserts its output in case of a renewed attempt to disconnect C or a target abort cycle on the secondary bus 32 is present (the signal FRAME_, the inverted state of the signal IRDY_, the inverted state of the signal STOP_, and the inverted state of the signal DSC_A_B are all true). The AND gate 508 asserts its output when a completed data transfer has occurred (the IRDY_ and TRDY_ signals are both low). As a result, the bus history information is loaded into the bus history FIFOs when the watchdog timer 554 is timed, a retry to interrupt C, or a Target Abort condition exists, the Master has purged the cycle, or one cycle has successfully completed.

The validity data indication signal VALID_DATA is provided by a flip-flop 510 generated by the D-type, which is clocked by the signal PCLK and is cleared by the signal RESET. The D input of the flip-flop 510 is connected to the output of a NOR gate 512 connected, the signal TIME_OUT, the master Abort signal M_ABORT and the output of the AND gate 506 receives. As a result, data is valid without timing being detected, a master abort cycle being issued, or a retry attempt to disconnect C or a target abort cycle present.

The signal VECT_RDY is controlled by a flip-flop 514 generated by the D-type, which is clocked by the signal PCLK and is cleared by the signal RESET. The D input of the flip-flop 514 is connected to the output of an OR gate 516 which receives the timing signal TIME_OUT and a signal CHANGE_STATE indicating that one of the PCI control signals in the bus vector has changed state. As a result, the state vector information is loaded into the vector FIFOs whenever there are control signals on the PCI bus 32 change a state or if a timeout has occurred.

As 44 1, the bus history data {BUS_HIST_DATA3 [31: 0], BUS_HIST_DATA2 [31: 0], BUS_HIST_DATA1 [15: 0]} becomes the input of the bus history register 540 which is the first stage of the bus history FIFO. The bus history 501 provides output signals BUS_HIST_FIFO1 [79: 0] to the register 542 (the second state of the pipeline), which provides output signals BUS_HIST_FIFO0 [79: 0]. Both bus history registers 540 and 542 are clocked by the signal PCLK and cleared when the power good signal SYNC_POWEROK is low.

The Bus History Register 540 and 542 are then loaded when the output of the AND gate 518 is driven high. The AND gate 518 receives the enable detect bit EN_CAP and the OR of the bus history ready signal HIST_RDY and the CAP_ILLEG_PROT signal (OR gate 519 ). The output signals BUS_HIST_FIFO0 [79: 0] and BUS_HIST_FIF01 [79: 0] become the 0 and 1 inputs, respectively, of multiplexers 520 . 522 and 524 delivered. Each of the multiplexers 520 . 522 and 524 is selected by a read address signal HIST_FIFO_RD_ADDR (which starts low to the output of the bus register 502 and toggled at each subsequent reading). The multiplexers 520 . 522 and 524 control output signals BUS HIST_REG3 [31: 0], BUS_HIST_REG2 [31: 0], BUS_HIST_REG1 [15: 0] respectively.

The bus vector data signals BUS_VECT_DATA [24: 0] become the inputs of a bus vector register 544 its output to the input of a bus vector register 546 is continued. The output of the bus vector register 546 becomes the input of a bus vector register 548 whose output in turn leads to the input of a bus vector register 550 is returned. Each of the bus vector registers 0-3 is clocked by the signal PCLK and cleared when the signals SYNC_POWEROK are low. The bus vector registers are then loaded when the output of the AND gate 521 is set high. The AND gate 521 receives the signal EN_CAP and the OR of signals VECT_RDY and CAP_ILLEG_PROT (OR-GATE 523 ). The bus vector registers 550 . 548 . 546 and 544 generate output signals BUS_VECT_FIFO0 [24: 0], BUS_VECT_FIFO1 [24: 0], BUS VECT_FIFO0 [24: 0] and BUS_VECT_FIF03 [24: 0] respectively, which in turn to the 0, 1, 2 and 3 inputs a multiplexer 526 each entered. The output of the multiplexer 526 provides signals BUS_VECT_REG [31: 0], where the multiplexer 526 select one of its inputs based on the state of address signals VECT_FIFO_RD_ADDR [1: 0] (which starts with a binary value 00 and increments each subsequent read).

As a result, the bus history and bus state vector information is in dependence recording of signals HIST_RDY or VECT_RDY respectively logged, or depending setting up the signal CAP_ILEG_PROT if an illegal one Bus protocol state is detected.

EXPANSION CARD SPACE RESERVATION

Unlike conventional computer systems reserved in the initial configuration of the computer system 10 , at power up, the CPU 14 a memory space and PCI bus numbers for the slots or ice tins 36 that are empty (no card 807 is used) or are switched off or shut down.

The CPU 14 As is typically done, allocates bus numbers for PCI buses (eg, PCI buses 24 . 32a - b and PCI bus (s) of the cards 807 in slits 36 are inserted and turned on), which are present when the computer system 10 is first switched on or raised.

Any PCI-to-PCI bridge circuit (eg PCI-PCI bridge 26 . 48 ) in this configuration register space 1252 ( 49 ) has a slave bus number register 1218 and a secondary bus number register 1220 , The sub-bus number register 1218 contains a slave bus number, which is the highest PCI bus number on the output side of the PCI-PCI bridge circuit, and the secondary bus number register 1220 contains a secondary bus number which is the PCI bus number of the PCI bus immediately downstream of the PCI-PCI bridge circuit. As a result, the values stored in the minor 1218 and the secondary 1220 Bus number registers, the range of PCI bus numbers present on the output side of the PCI-PCI bridge circuit.

The configuration register space 1252 also has a primary bus number register 1222 , The Primary Bus Number Register 1222 contains the number of the PCI bus, arranged immediately on the input side of the PCI-PCI bridge circuit.

The system controller / host bridge circuit 18 also owns the secondary 1218 and secondary 1220 Bus number register. After a configuration contains the Ne ben Bus Number Register 1218 the circuit 18 the maximum PCI bus number that exists in the computer system. The secondary bus number register 1220 the circuit 18 contains the bus number zero, since the PCI bus is directly on the output side of the circuit 18 (PCI bus 24 ) is always assigned the bus number zero.

Unlike the known system, the CPU detects 14 that one of the slots 36 , which is initially powered up or is empty, one or more additional PCI bus (s) (present on the card 802 inserted in the slot 36 , shut down at the beginning) in the computer system 10 can introduce into it after the computer system 10 already switched on or started up and configured. Accordingly, during an initial configuration, the CPU reserves 14 Memory space, I / O space, and a predetermined number (eg, one or three) of PCI bus numbers for any slot 36 that is shut down or empty.

As a result, the PCI-PCI bridge circuits of the computer system 10 not reconfigured to the card 807 which has been switched on recently. Only the PCI-PCI bridge circuits of the card 807 that has been switched on recently must be configured. The rest of the computer system 10 remains unchanged.

As part of the resource reservation process builds a basic input / output system (BIOS) stored in the ROM 23 and hidden in the memory 20 entered (and read-only), a table that specifies resource areas for the slots 36 reserved. This table includes a bus number, memory, and I / O resource areas for use in configuring a PCI device new to the system 10 has been added. The operating system uses this table to determine which resources have been reserved and which resources are available for configuring the newly added PCI device.

As in 45 in a recursive PCI configuration program, referred to as BUS_ASSIGN, maps the CPU 14 Configuration Registers 1252 for PCI bus numbers and programs corresponding to the PCI-PCI bridge circuits. The CPU 14 does this by scanning a PCI bus at a time for PCI devices. The BUS_ASSIGN program is part of the BIOS stored in the ROM 23 , and is used initially to the computer system 10 , after turning on, configure.

The CPU 14 sets first 1000, the value of a search parameter PCI bus, equal to the value of another search parameter CURRENT_PCI_BUS, and initializes 1000 search parameters FCN and DEV. The PCI bus parameter indicates the bus number of the PCI bus currently being used by the CPU 14 is sampled, and if the BUS_ASSIGN program first by the CPU 14 is executed, the PCI bus parameter displays the bus number zero.

The parameter CURRENT_PCI_BUS indicates the next PCI bus number available for allocation by the CPU and if the program BUS_ASSIGN is first issued by the CPU 14 is executed, the parameter CURRENT_PCI_BUS indicates a bus number zero. The parameters FCN and DEV indicate the current PCI function and the PCI device, respectively, currently being used by the CPU 14 be scanned.

The CPU 14 certainly, 1001 whether the parameter PCI_BUS indicates a bus number zero, and if so, the CPU stops 14 the secondary bus number register 1220 the system controller / host bridge circuit 18 equal to zero. The CPU 14 then finds 1004 , the next PCI-PCI bridge circuit or the slot 36 that is powered down or blank, on the PCI bus, indicated by the parameter PCI BUS. For purposes of determining whether the next found PCI device is or does not exist a PCI-PCI bridge circuit (a powered down or empty slot), the CPU attempts 14 to read from a value of an ON-word vendor-ID register located in the configuration space of each PCI device. A value of "hFFFF" (where the prefix "h" denotes a hexadecimal representation) is reserved and not used by any vendor. If the attempted read from the vendor ID register returns to a value of "HFFFF", then this indicates that there is no PCI device.

If the CPU 14 certainly, 1006 that there are no other, non-found PCI-PCI bridge circuits or slots 36 There is a drop of the last call on the PCI bus, indicated by the PCI BUS parameter, that are down or empty taken to the BUS_ASSIGN program. Otherwise, the CPU determines 14 . 1008 whether another PCI-PCI bridge circuit has been found, and if not, increases the CPU 14 . 1010 , the parameter CURRENT_PCI_BUS, as a slot or slot 36 which is turned on or empty, and finds, 1004 , the next PCI-PCI bridge circuit. or a slot 36 that is switched off or empty. Consequently, by increasing, 1010 , of the parameter CURRENT_PCI_BUS, the CPU 14 effectively a bus number for the slot 36 that is switched off or empty. Alternatively, the CPU 14 more than one bus number for the slot 36 reserve, which is switched off or empty.

If the CPU 14 found a PCI-PCI bridge circuit, then put the CPU 14 . 1012 , the primary bus number of the PCI-PCI bridge circuit is equal to the parameter CURRENT_PCI_BUS. The CPU 14 then increases, 1014 , set the parameter CURRENT_PCI_BUS and, 1016 , the secondary bus number of the PCI-PCI bridge is equal to the new bus number indicated by the parameter CURRENT_PCI_BUS.

The CPU 14 then, 1018 , the sub-bus number of the PCI-PCI bridge circuit found equal to the maximum possible number of PCI buses by writing to the sub-bus number register 1218 , This value for the slave bus number register 1218 is temporary and allows the CPU 14 , additional output side PCI-PCI bridge circuits or slots 36 to find and program that are turned off or empty.

The CPU 14 finds additional output side PCI-PCI bridge circuits or slots 36 that are off or empty by storing, 1022 calling parameters PCI_BUS, DEV and FCN and respectively, 1022 , the BUS_ASSIGN program. The CPU 14 then save again, 1024 , the values for the PCI_BUS, DEV, and FCN parameters, and returns to the last call of the BUS_ASSIGN program to update the CURRENT_PCI_BUS parameter with the next PCI bus number issued by the CPU 14 should be assigned.

The CPU 14 then updates, 1026 to set the sub-bus number of the found PCI-PCI bridge by setting, 1026 , the sub-bus number is equal to the parameter CURRENT_PCI_BUS. Consequently, this includes the assignment of the PCI bus number to the found PCI-PCI bridge circuit and additional output PCI-PCI bridge circuits and slots 36 off, which are switched off or empty. The CPU 14 then finds 1004 , the next PCI-PCI bridge circuit or the slot 36 that are off or empty on the PCI bus, indicated by the PCI_BUS parameter.

As in 46 is shown, after the PCI bus numbers are assigned, the CPU 14 a memory space allocation program, referred to as MEM_ALLOC, turns off memory space for the PCI functions and slots 36 assign, which are switched off or empty. The CPU 14 initializes first, 1028 , Search parameter, used in supporting the CPU 14 finding the PCI functions and slots 36 that are switched off or empty.

The CPU 14 , then finds 1030 , the next PCI function or the slots 36 that is switched off or empty. If the CPU 14 certainly, 1032 that all PCI functions and all slots or slots 36 that are off or empty, have been allocated to a memory space, the CPU returns 14 from the program MEM_ALLOC. Otherwise, the CPU determines 14 . 1032 whether a PCI function was found.

If so, the CPU maps 14 Memory resources too, 1038 as specified by the PCI function. Otherwise, one of the slots or insertion slots 36 which is turned off or empty, found, and the CPU 14 associates an error memory size and a memory alignment for the slot 36 to, 1036 , The error memory size may either be a predetermined amount, determined prior to turning on the computer system 10 , or a size, after a determination of the memory resources required by the computer system 10 , is determined.

When memory space is allocated, the CPU programs 14 Memory base 1212 and memory limits 1214 Register of PCI-PCI bridge circuits present on the input side of the found PCI function. The CPU 14 Also suitably programs base address registers of the corresponding PCI devices. The CPU 14 then finds 1030 , the next PCI function or the slot 36 that is switched off or empty.

As in 47 is shown, after the PCI bus numbers are assigned, the CPU 14 an I / O space allocation program, referred to as I / O_ALLOC, off to I / O / space for PCI functions and slots 36 that are empty, assign. The CPU 14 initializes first, 1040 , Search parameters, used when Support the CPU 14 , the associated PCI functions and slots 36 that are turned off or empty.

The CPU 14 finds 1042 , the next PCI function or the slot 36 that is switched off or empty. If the CPU 14 certainly, 1044 that all PCI functions and slots 36 that are off or empty, have been assigned to an I / O / space, the CPU returns 14 back from the I / O_ALLOC program. Otherwise, the CPU determines 14 . 1044 whether a PCI function was found. If so, the CPU maps 14 . 1050 , I / O resources too, as specified by the PCI function. Otherwise, arrange a slot 36 that was shut down or found empty, and the CPU 14 an error I / O size and I / O alignment for the slot 36 to, 1048 , The error I / O size may either be a predetermined amount, determined prior to shutdown of the computer system 10 , or a size determined by a determination of the I / O resources required by the computer system 10 , be.

If an I / O / room is assigned then the CPU programs 14 the I / O base 1208 and limited, 1012 , Registers of the PCI-PCI bridge circuits, input side of the PCI function or the slot 36 , The CPU 14 also programs base address registers of the corresponding PCI devices. The CPU 14 then finds 1042 , the next PCI function or the slot 36 that is switched off or empty.

As in 48 after an initial configuration, when an interrupt is generated that indicates that one of the levers 802 open or closed, the CPU 14 an interrupt service program, referred to as CARD_INT, off. The CPU 14 read, 1052 , the contents of the interrupt register 800 , to determine, 1053 whether the lever 802 has been opened or closed. If the CPU 14 certainly, 1053 that the lever 802 that caused the interruption, the CPU returns 14 from the program CARD_INT.

Otherwise, the CPU writes 14 . 1054 , to the slot-release register 817 and pose 1054 , the SO bit to turn on the slot 36 and the card 807 inserted in the slot 36 , to initiate. The CPU 14 then wait (not shown) for the card 807 to turn on. The CPU 14 then pick, 1055 to the PCI bus on the card too, if available. The CPU 14 then determines 1056 whether the card 807 that was just turned on had a PCI bus (and a PCI-to-PCI bridge circuit). If this is the case, determines 1057 , the CPU 14 the primary, secondary and subroutine bus numbers reserved for the slot 36 in which the card 807 was turned on. The CPU 14 subsequently configures 1058 , the PCI-PCI bridge circuit on the card 807 that was turned on.

The CPU 14 then determines 1060 , the location and size of I / O and storage spaces, reserved for the slot 36 , The CPU 14 subsequently writes 1062 to base address registers in the PCI configuration header space of the card 807 that was turned on. The CPU 14 then reads, 1064 , an interrupt pin register in the configuration space of the card 807 , to determine, 1066 whether the card 807 Interrupt requests used. If so, the CPU writes 14 . 1068 , an interrupt line register in the configuration space of the card 807 with an assigned IRQ number.

The CPU then gives 1070 , Command register of the card 870 free in the configuration space of the card 807 are arranged, and allows the card 807 , to memory and I / O access to the PCI bus 32 to appeal. The CPU 14 subsequently writes 1072 to the interrupt register 800 to clear the interrupt request and load, 1074 , a software device driver for the card 807 , The CPU 14 then returns from program CARD_INT.

BRIDGE CONFIGURATION

Functionally form bridge chips 26 and 48 a PCI-PCI bridge between PCI buses 24 and 32 , However, each bridge chip has a configuration space that needs to be independently configured. One solution is to treat two bridges as independent devices forming a bridge, but this would require a modification of the BIOS configuration program. The other solution is the one that cables 28 as define a bus, so the configuration program the input side bridge chip 26 as a PCI-PCI bridge between the PCI bus 24 and the cable 28 and the output side bridge chip 48 as a PCI-PCI bridge between the cable 28 and the PCI bus 32 can configure. An advantage of this second solution is that standard PCI configuration cycles can run to the bridge chips 26 and 48 if they were two PCI-PCI bridges, in fact if the two bridge chips form a PCI-PCI bridge.

There are two types of configuration transactions on the PCI bus: type 0 and type 1. A Type 0 configuration cycle is for devices on the PCI bus on which the configuration cycle is generated while a configuration cycle is in progress Type 1 cycle for devices on a secondary PCI bus accessed via a bridge is provided. 51 represents the address format of type 0 and type 1 configuration cycles. A type 0 configuration command is specified by setting PCI address bits AD [1: 0] to 00 during a configuration cycle. A Type 0 configuration cycle is not continued via a PCI-PCI bridge, but remains locally on the bus where the Type-0 configuration transaction was created.

One Type 1 configuration command is accomplished by setting address bits AD [1: 0] on a binary Value 01 specified. Configuration commands of type 1 can by a PCI-PCI bridge continue to any level in the PCI bus hierarchy. After all converts a PCI-PCI bridge a Type 1 command to a Type 0 order command to devices to configure that connected to the secondary interface of the PCI-PCI bridge are.

Configuration parameters stored in the configuration registers 105 or 125 The bridge, identify the bus numbers for their primary PCI interface (primary bus number) and secondary PCI interface (secondary bus number) and a sibling bus number, which is the highest, numbered PCI bus subordination indicating the bridge. The bus numbers are determined by a PCI configuration program BUS_ASSIGN ( 45 ). For example, in the input side bridge chip 26 , the primary bus number of the bus 24 , the secondary bus number is the number of cable 28 and the slave bus number is the number of the secondary PCI bus 32 or the number of a lower PCI bus, if one exists. In the output side bridge chip 48 the primary bus number is the number of the cable bus 28 , the secondary bus number is the number of the PCI bus 32 and the sibling bus number is the number of a PCI bus located lower in the PCI bus hierarchy, if one exists.

As 53A shows, detection of configuration cycles by logic in the PCI target block 103 or 121 in the input side bridge chip 26 or the output side bridge chip 48 each treated. A configuration cycle of type 0, detected on the input side bus 24 , is established by asserting a signal TYP0_CFG_CYC_US generated by an AND gate 276 , displayed. The AND gate 276 receives signals UPSTREAM_CHIP, IDSEL (chip select during a configuration transaction), CFGCMD (configuration command cycle detected) and ADDR00 (bits 1 and 0 are both 0's). A configuration cycle of type 0 detected by the output side bridge chip 48 , is given by a signal TYP0_CFG_CYC_DS, generated by an AND gate 278 , indicated that a signal S1_BL_IDSEL (IDSEL signal for the output side bridge chip 48 ), the signal CFGCMD, the signal ADDR00, a signal MSTR_ACTIVE (indicating that the bridge chip 48 the master on a secondary PCI bus 32 is), and receives the inverted state of a signal UPSTREAM_CHIP.

A capture of a type 1 configuration cycle by the PCI target 103 in the input side bridge chip 26 is set by asserting a signal TYP1_CFG_CYC_US from an AND gate 280 displayed, the signals CFGCMD, ADDR01 (bits 1 and 0 are low and high respectively) and UPSTREAM_CHIP receives. A detection of a type 1 configuration cycle on the output side bus 32 is done by setting up a TYP_CFG_CYC_DS signal from an AND gate 282 , which receives the signals CFGCMD, ADDR01, and the inverted state of the signal UPSTREAM_CHIP.

The bridge chip that accepts a type 0 transaction uses the register number field 250 in the configuration transaction address to access the appropriate configuration register. The function number field 252 specifies one of eight functions to be performed in a multi-functional device during the configuration transaction. A PCI device may be multi-functional and may have such functions as a hard disk drive controller, a memory controller, a bridge, etc.

If the bridge chip 26 a type 1 configuration transaction on its input side bus 26 sees, he can either continue the transaction on the output side, translate the transaction to a type 0 transaction, convert the transaction to a specific cycle, or ignore the transaction (based on the bus number parameters stored in the configuration registers 105 or 125 ). If a transaction continues, it goes to the PCI master of the destination bridge chip to convert the type 1 transaction to the appropriate transaction. If a bridge chip handles the transaction itself, it will respond to the PCI bus by asserting the signal DEVSEL_ and handle the transaction as a normal, delayed transaction.

In a configuration transaction of type 1 selects the bus number field 260 a unique PCI bus in the PCI hierarchy. A PCI target block 103 performs a type 1 configuration cycle of the input side chip 26 to the output side bridge chip 48 if a PASS_TYP1_DS signal passes through an AND gate 284 is set up. The AND gate 284 receives the signal_TYP1_CFG_CYC_US and a signal IN_RANGE (the bus number field 260 is greater than or equal to the stored secondary bus number and less than or equal to the stored slave bus number). The other input of the AND gate 284 is with the output of an OR gate 286 connected, which has an input to the output of an AND gate 288 and the other input receives the inverted state of a signal SEC_BUS_MATCH. Consequently, if a Type 1 cycle is detected, the IN_RANGE signal is asserted, and if the Bus Number field 260 does not adjust the stored secondary bus number, the PASS_TYP1_DS signal is asserted. If the bus field 260 does not adjust the stored secondary bus number, then the bus devices on or after the output side bus 32 addressed. The AND gate 288 is set to high and the device number field 258 indicates that the target of the Type 1 configuration cycle is the configuration space of the output bridge chip 48 is. If true, the configuration transaction will be type 1 along the cable 28 to the output side bridge chip 48 for a translation of a type 0 configuration transaction. The PCI target 121 in the output side bridge chip 48 responds to the transaction and reads from the and writes to the output side bridge configuration registers 125 corresponding to the type-0 transaction. The control pins of the output-side chip are driven and read and write data appear on the output-side PCI bus 32 if a transaction of type 0 is on the output side bus (for debug purposes), although each IDSEL is on the output side bus 32 is blocked so that no device is actually responsive to a type 0 transaction.

If the PCI target block 103 in the input side bridge chip 26 a configuration transaction of type 1 on its input side bus 24 detected, with a bus number field equal to the stored secondary bus number (the cable bus 28 ), but not addressing a device 0 (look for other devices on the cable bus 28 ), then the target block ignores 103 the transaction on the primary bus 26 ,

If the PCI target 121 a configuration write transaction of type 1 (WR_high) on the secondary PCI bus 32 detected having a bus number field outside the range of the secondary bus number and the sub-bus number (IN_RANGE low), and if the device number 258 , the function number 256 and the register number 254 show a special cycle (SP_MATCH high), then a PASS_TYP1_US signal goes through an AND gate 290 established. The AND gate 290 receives the signal TYP1_CFG_CYC_DS, the signal SP_MATCH, the write / read strobe WR_ and the inverted state of the signal IN_RANGE. If the PCI master 101 in the input side bridge chip 26 When it receives such a cycle, it leaves a special cycle on the primary PCI bus 24 to run.

Configuration transactions are ignored by a bridge chip under certain conditions. If the target block 103 in the input side bridge chip 26 a type 1 configuration transaction on the PCI bus 24 detected (its input side bus) and the bus number field 260 is less than the secondary bus number or greater than the slave bus number stored in the configuration space of the bridge chip, then ignores the target block 103 the transaction.

If the target block 121 in the output side bridge chip 48 a type 1 configuration transaction on the secondary PCI bus 32 detected (its output side bus), and the bus number field 260 is greater than or equal to the secondary bus number, or less than or equal to the slave bus number stored in the bridge chip configuration space, then the target block ignores 121 the transaction. In addition, type 1 configuration instructions going to the input side are ignored if a type 1 instruction does not specify a conversion to a particular cycle transaction, regardless of the bus number specified in the type 1 instruction.

As 53B shows, monitors the PCI master 101 or 123 a configuration cycle, transmitted via the cable 28 , If the PCI master 123 in the output side bridge chip 48 a type 1 configuration transaction from the upstream bridge chip 26 captures, compares the bus number field 260 with the primary bus number and the secondary bus number stored in the bridge chip configuration space 48 , If the bus number field 260 either the stored primary bus number (ie cable 28 ) or the stored secondary bus number (addressing a device directly connected to the output side bus 23 ), then the output side bridge chip translates 48 the transaction becomes a type 0 transaction (by setting AD [1: 0] = 00) when it completes the configuration transaction on the bus continues. The transaction of type 0 will be on the PCI bus 32 through the PCI master block 123 carried out.

The following are translations performed by fields in the type 1 configuration transaction. The device number field 258 in the type 1 configuration transaction is through the PCI master 123 decodes to a unique address in the translated type 0 transaction on the secondary bus 32 to produce, as shown in the table of 52 is defined. The secondary address bits AD [31:16] decoded from the device number field 258 , be through the PCI master 123 used to provide the appropriate chip selection signals IDSEL for the devices on the secondary PCI bus 32 to create. If the address bit AD [15] is equal to 1, then the bridge chip keeps 48 all address bits AD [31:16] set to low (no IDSEL set up). The register number field 254 and the function number field 256 of the type 1 configuration command are passed unmodified to the type 0 configuration command. The function number field 256 selects eight functions, and the register number field 254 selects a double word in the configuration register space of the selected function.

For a type 1 configuration transaction targeted to the output bridge chip 48 , converts the bridge chip 48 the transaction of type 1 to a transaction of type 0, as if it were a device on the output side bus 32 however, the AD [31:16] pins are set to 0's so that no secondary PCI bus device will pick up an IDSEL. The PCI Master logic 123 detects this by setting up a signal TYP1_TO_INT0, driven by an AND gate 262 , The AND gate 262 receives a signal CFG_CMD (indicating a configuration command cycle), the output of an OR gate 264 and the inverted state of the signal UPSTREAM_CHIP (Translation Type-1-to-Type-0 is in the input side bridge chip 26 blocked). The OR gate 264 sets its output high if a PRIM_BUS_MATCH signal is asserted (the bus number field 260 adjusts the stored primary bus number) or if the stored primary bus number CFG2P_PRIM_BUS_NUM [7: 0] is equal to zero (indicating that the primary bus number is in the bridge chip's configuration space 48 has not been configured by the system BIOS until now, and the current type 1 configuration cycle goes to the internal configuration space to the bridge chip's primary bus number 48 to program).

A signal TYP1_TO_EXT0 is passed through an AND gate 266 and responds to an adaptation to a stored secondary bus number. The inputs of the AND gate 266 receive the signal CFG_CMD, the signal SEC_BUS_MATCH, the inverted state of the signal UPSTREAM_CHIP and the inverted state of a signal SP_MATCH (not a special cycle). The TYP1_TO_EXT0 signal indicates that the converted type 0 configuration transaction to a device is targeted on the secondary PCI bus 32 to be led.

The signal TYP1_TO_INT0 becomes the 1 input of a 4: 1 multiplexer 274 delivered. The 2 input is set low and the 0 and 3 input of the multiplexer 274 take a signal LTYP1_TO_INT0 from a flip-flop 270 of the D-type. The selection input S1 of the multiplexer 274 receives a signal CMD_LATCH (FRAME_, asserted for a new cycle on the PCI bus 32 ), and the select input S0 receives a signal P2Q_START_PULSE (indicating, if high, that an address to the PCI bus 32 has been sent). The output of the multiplexer 274 is connected to the D input of a flip-flop 270 which is clocked with the signal PCLK and is cleared by the signal RESET. The IDSEL signals to the secondary bus devices are established by asserting a signal BLOCK_IDSEL from an OR gate 272 blocked, the signals at its inputs Q2P_AD [15] (no conversion is according to Table 1 of the 6 needed), TYP1_TO_INT0 and LTYP1_TO_INT0. The signal LTYP1_TO_INT0 expands the establishment of the signal BLOCK_IDSEL.

If the PCI master 123 in the output side bridge chip 48 a type 1 configuration transaction from the upstream bridge chip 26 receives in which the bus number field 260 is greater than the stored secondary bus number and less than or equal to the stored slave bus number, then the PCI master block is executing 123 the transaction of type 1 to the secondary PCI bus 32 unchanged. A specific other device on the secondary PCI bus 32 , z. B. another bridge device 323 ( 26B ), the type 1 configuration transaction will pick up and transfer it to the secondary bus (PCI bus 325 ) continue.

A configuration transaction of type 1 to a special cycle translation is then performed when the PCI master 123 a configuration write transaction of type 1 from the input side Bridge chip 26 receives and the bus number field 260 adjusts the stored secondary bus number and if the device number field 258 , the function number field 256 and the register number field 254 show a special cycle (SP_MATCH is high). This is done by an AND gate 268 is displayed, which sets a signal TYP1_TO_SPCYC high. The AND gate 268 receives SP_MATCH, and Q2P_CBE_ [0] (command bit for a special cycle). The data from the type 1 configuration transaction becomes the data for the particular cycle on the destination bus. The address during a special cycle is ignored.

BUS FUNCTION MONITOR

The bus monitor 127 ( 3 ) includes a circuit for storing information to calculate certain bus function parameters. The parameters include bus usage, bus efficiency, and read-data-effectiveness. A bus usage is the ratio of the time that the bus is busy, making a transaction, to a given global time period. Bus efficiency is the ratio of the number of PCI clock periods actually used for data transmission to the total number of clock periods during the bus slip period. A read data efficiency is the ratio of the number of read data bytes passed through a device on the secondary PCI bus 32 is accessed by the delayed completion queue (DCQ). 144 ( 4 ), to the total number of data bytes retrieved for that master by the bridge chip 48 , The information stored in the bus monitor 127 , are retrieved by the system software to calculate the desired parameters.

As 54A shows, counts a global-period timer 1300 (which can be 32 bits wide) a whole time period during which the various parameters are to be calculated. The timer 1300 is programmed to the hexadecimal value FFFFFFFF. If the PCI clock PCICLK2 is running at 33 MHz, then the timer period is about 2 minutes. If the timer 1300 reduced to 0, it sets a signal GL_TIME_EXPIRE.

The bus monitor 127 includes 7 slot-specific bus busy counters 1302A - G where six of the counters respectively correspond to the 6 slots on the secondary PCI bus 32 and one of the SIO 50 correspond. The bus-busy counters 1302A - G are cleared when the signal GL_TIME_EXPIRE is set up. Depending on which bus device has control on the secondary bus 32 owns, the Bus Busy counter increases 1302 at every PCI clock in which the secondary PCI bus FRAME_ or IRDY_ signal is set up. The appropriate one of the seven counters is selected by one of the grant signals GNT [7: 0] _. As a result, for example, the bus busy counter 1302A then selected when signal GNT [1] _ is low, indicating that the SIO is the current master on the secondary PCI bus 32 is.

Seven data cycle counters 1306A - G respectively, to the 6 slots on the secondary PCI bus respectively 32 and the SIO 50 , track the time during which a data transfer is actually between a master and a target during a transaction on the PCI bus 32 occurs. The selected data cycle counter 1306 is incremented at each PCI clock at which the secondary bus IRDY_ and TRDY_ signals are both low. The data cycle counter 1306A - G are cleared when the signal GL_TIME_EXPIRE is set up.

Six DCQ data counters 1310A - F are in the bus monitor 127 for logging the amount of data loaded into the DCQ buffers. The six DCQ data counters 1310A - F correspond to the 6 slots on the secondary PCI bus 32 , The selected DCQ data counter 1310 increases with each PCI clock by delaying Delay Read Completion (DRC) data from the cable 28 received and loaded into the prefetch buffers.

Another set of counters, DCQ data usage counters 1314A - F , are used to log the amount of data in the DCQ 144 actually used by the 6 slots on the secondary PCI bus 32 , The selected DCQ data usage counter 1314 increases with each PCI clock in which the secondary bus master reads data from the corresponding DCQ buffer. Both DCQ data counters 1310A - F and DCQ Data Usage Counters 1314A - F increase each data cycle regardless of the number of bytes actually being transmitted. In most cases, the number of bytes transmitted in each data cycle is 4.

If the Global Period Timer 1300 and executes the signal GL_TIME_EXPIRE, various events occur. First, the Global Period Timer loads 1300 its original count value, which is the hexadecimal value FFFFFFFF. The contents of all other counters, including the Bus-Busy counter 1302A - G the data cycle counter 1306A - G , the DCQ data counter 1310A - F and the DCQ data usage counters 1314A - F , be in register 1304 . 1308 . 1312 and 1316 each invited. The counters 1302 . 1306 . 1310 and 1314 will be cleared to 0 The Global Period Timer 1300 then begins to count again after reloading with its original value.

The signal GL_TIME_EXPIRE becomes the interrupt recording block 132 fed the interruption over the cable 28 to the interrupt output block 114 which in turn gives an interrupt to the CPU 14 generated. The CPU 14 responds to the interruption by calling an interrupt handler to perform the bus function analysis. The interruption dealer accesses the contents of the registers 1304 . 1308 . 1312 and 1316 to, and calculates the various parameters including bus usage, bus efficiency, prefetch effectiveness parameters, associated with the 6 secondary bus slots and the SIO 50 ,

The Bus Usage parameter is the value of the Bus-Busy Counter 1302 , divided by the initial value of the global period timer 1300 , which is the hexadecimal value FFFFFFFF. As a result, the bus usage is the percentage of the total global time during which a bus master performs a bus transaction.

A PCI transaction includes an address phase and at least one Data transmission phase. A bus master sets the signal FRAME_ to the beginning and the Duration of an active bus transaction. If the signal FRAME_ is removed, this indicates that the transaction is the End data phase is or the transaction has been completed. The signal IRDY_ indicates that the bus master is able to complete the current data phase of the bus transaction. During one Writing, the signal IRDY_ indicates that valid data is present on the bus are. While a read indicates the signal IRDY_ that the master prepares is to accept read data. The addressed PCI target speaks to the bus transaction by asserting the signal TRDY_ to indicate that the target is capable of the current data phase to complete the transaction. While On reading, signal TRDY_ indicates that valid data is present on the bus are; while In writing, the signal TRDY_ indicates that the target is being prepared is to accept data. Wait states can be between the address and data phases and between successive data phases the bus transactions are used. During the address phase or the wait states does not transmit data indeed on.

Actual data transfer occurs only when both IRDY_ and TRDY_ signals are low. To determine the data, transmit bus efficiency, the interrupt handler shares the value of the data cycle counter 1306 by the value of the bus busy counter 1302 , The bus efficiency represents the amount of time during which data transfer actually occurs during a bus transaction. By calculating this value, the computer system may become aware of target devices that require many wait states and are therefore ineffective.

The bridge chip 48 can read data from the primary PCI bus 26 retrieve and the data in the DCQ 144 to save. The DCQ 144 has eight buffers, each of which can be assigned to a secondary bus master. For example, a memory read multiple transaction, generated by a secondary bus master as a destination on the primary bus, will cause the bridge 26 . 48 a total of 8 cache lines from the memory 20 retrieve them and put them in the DCQ 144 invites. A memory read-line transaction will cause the PCI-PCI bridge 26 . 48 a line of data from the memory 20 retrieves. In addition, as in connection with the 75 and 79 described is the PCI-PCI bridge 26 . 48 perform a read promotion that converts a read request from a secondary bus master to a read request for a larger block of data. In these cases, there is a possibility that not all of the retrieved data will be used by the bus master. In this case, unread data is discarded, which reduces read data effectiveness. Measuring the read-data effectiveness allows system designers to understand how a bus master reads data retrieved by the bridge chip 26 . 48 , from the primary bus 24 , used.

As 54B shows, the counter increases 1310 at the rising edge of the clock PCLK, if the signal DCQ_DATA_RECEIVED [X], X = 2-7, is asserted, indicating that there are four bytes of data through a DCQ buffer associated with a master X from the cable 28 to be received. The counter 1310 outputs a count value DCQ_Data [X] [20: 0], X = 2-7, which is cleared to zero when the signal GL_TIME_EXPIRE is asserted.

The counter 1314 increases at the rising edge of the clock PCLK if a signal DCQ_DATA_TAKEN [X], X = 2-7, is asserted, indicating that four bytes of data are read from a DCQ buffer associated with master X ,. The counter 1314 is cleared when the signal GL_TIME_EXPIRE is high.

To determine the amount of DCQ data that is actually passing through the devices on the secondary PCI bus 32 are used, the prefetch effectiveness is calculated by the interrupt handler. This is determined by the ratio of the value in the counter 1314 , which uses the DCQ data, to the value of the DCQ data counter 1310 is set. Even though not all data transferred into or out of the prefetch buffers is 4 bytes wide, the ratio is closely approximated by an assumption that all data phases carry the same number of bytes.

In dependence the calculated parameter may be a user or the computer manufacturer better understand the function of the computer system. For example could then, if a bus effectiveness is low, the PCI device inserted through different part of the computer manufacturer. A Knowing the DCQ read-data effectiveness allows the computer manufacturer to its DCQ fetch algorithm to change, to better the effectiveness to improve.

USE BY-SIDE BUS DEVICES

As in 88 6 expansion cards are inserted into the six expansion card slots 36a - f , Bus devices 1704 - 1708 one leading to the CPU 14 subordinate and bus devices 1701 - 1702 leading to an I ₂ O processor 1700 are subordinate. Although all sub-bus devices 1701 - 1708 with the common PCI bus 32 are connected, the I ₂ O sub-devices appear 1701 - 1702 to the CPU 14 just so that they have the I ₂ O processor 1700 are addressable and not directly over the PCI bus 32 are addressable. That's why the PCI bus is used 32 both as an I ₂ O sub-device bus and as a sub-device bus of the CPU 14 ,

For purposes of preventing the CPU 14 the I ₂ O by-devices 1701 - 1702 as a device of the PCI bus 32 detects, includes the bridge chip 48 a logic 1710 ( 90 ) to prevent the I ₂ O minor devices 1701 - 1702 respond to configuration cycles by the CPU 14 to run. The expansion box 30 also includes a multiplexing circuit 1712 that with the interruption recording block 132 of the bridge chip 48 works to mask interrupt requests made by the I ₂ O minor devices 1701 - 1702 assume that this to the CPU 14 propagate. Interrupt requests made by the I ₂ O sub-bus devices 1701 - 1702 go out through the interruption recording block 132 to the I ₂ O processor 1700 diverted. The I ₂ O processor 1700 configures the I ₂ O slave devices 1701 - 1702 ; receives and handles interrupt requests made by the I ₂ O slave devices 1701 - 1702 go out; and controls an operation of the I ₂ O sub-devices as done by the CPU 14 is directed.

After turning on the computer system 10 and if a card 807 is powered up (ie, a new bus device is on the PCI bus 32 introduced), the I ₂ O processor scans 1700 the PCI bus 32 to identify I ₂ O sub-bus devices. For the purpose of identifying the type of a bus device (I ₂ O sub-bus device or sub-device of the CPU 14 ) leaves the I ₂ O processor 1700 Configuration cycles on the PCI bus 32 to read the device identification word (device ID) of each bus device. The device ID is located in the configuration header space of all PCI devices. The I ₂ O processor 1700 stores the results of this scan in an I ₂ O minor register 1729 with six bits ( 93 ) within the I ₂ O processor 1700 that by the cpu 14 is accessible. Bits zero to five of the register 1729 are slots or slots 36a - f each assigned. A value of "1" for a bit indicates that the allocated slot 36 a bus slave device to the CPU 14 and a value of "0" for one bit indicates that the allocated slot 36 a bus slave device to the I ₂ O processor 1700 has.

The I ₂ O processor 1700 can in any of the slots or slots 36a - f be used. For purposes of identifying which slot 36 if any is present, contains an I ₂ O processor, the CPU will sample 14 the PCI bus 32 and reads the device ID of the bus devices connected to the bus 32 , The CPU 14 do not try any devices 1704 - 1708 on the bus 32 to configure up a host configuration enable bit 1726 ( 94 ) within the I ₂ O processor 1700 the CPU 14 indicates that the I ₂ O processor 1700 its identification of I ₂ O minor devices 1701 - 1702 on the bus 32 has completed. The host configuration enable bit 1726 has a value of "0" (value at switching on) to configure the devices on the bus 32 through the CPU 14 to lock, and a value "1" to a configuration of the CPU 14 the ancillary devices 1704 - 1708 the CPU 14 on the bus 32 release. If the CPU 14 Bus devices on the bus 32 configured, "sees" the CPU 14 not the I ₂ O by-devices 1701 - 1702 , because of the masking by the logic 1710 , as described below.

After the host release configuration bit 1726 is set, the CPU reads 14 the contents of the I ₂ O minor register 1729 and transmits the read contents to a six-bit I ₂ O sub-register 1428 ( 91 ) of the bridge chip 48 , The registry 1728 shows the slave status (slave I ₂ O processor 1700 or secondary CPU 14 ) of the bus devices in the same manner as the register 1729 at. Before the CPU 14 to the register 1728 writes, contains the register 1728 all "ones" (values at power up), which is the CPU 14 allows the bus 32 after the I ₂ O processor 1700 scan. The interruption recording block 132 uses the register 1728 to identify which interrupt requests received by the block 132 , to the CPU 14 should be performed, and what interrupt requests received by the block 132 to the I ₂ O processor 1700 for processing. Continue to use the logic 1710 the contents of the register 1728 to get a detection by the CPU 14 of I ₂ O by-devices 1701 - 1702 from the CPU 14 to block.

For purposes of indicating to the interrupt receive block 132 Which bus device, if any, is an I ₂ O processor, represents the CPU 14 one bit of an I ₂ O slot register 1730 ( 32 ), bits 0-5 of which are slots 36a - f respectively correspond. For this register 1730 , arranged inside the bridge chip 48 , a value of "0" for one bit indicates that the allocated slot 36 does not have an I ₂ O processor, and a value of "1" for the bit indicates that the allocated slot 36 has an I ₂ O processor.

As in 90 is illustrated, includes the logic 1710 a multi-bit AND gate 1711 , the signals AD_IDSEL [5: 0] to address / data lines of the bus 32 delivers to devices on the bus 32 during configuration cycles. The AND gate 1711 receives a six-bit signal ENABLE [5: 0] having bits corresponding to bits of the I ₂ O sub-register 1728 are indicative and correspond to them. The AND gate 1711 also receives the typical identification selection signals SLOT_IDSEL [5: 0] supplied by the bridge chip 48 to select devices on the bus 32 during configuration cycles. Therefore, the signals ENABLE [5: 0] are used to selectively latch the signals SLOT_IDSEL [5: 0] from the PCI bus 32 to mask when configuration cycles through the CPU 14 to run.

For purposes of controlling the determination of interrupt requests from the slots 36a - d , the four standard PCI interrupt request signals (INTA #, INTB #, INTC # and INTD #) are provided by each slot 36 to a multiplexing circuit 1712 guided ( 88 ). The multiplexing circuit 1712 serializes the PCI interrupt request signals received from the slots 36 , and supplies the signals to the interrupt receive block 132 via four time-multiplexed, serial interrupt request signals: INTSDA #, INTDSB #, INTSDC #, and INTSDD #.

As in 89 is shown, provides the interrupt receive block 132 Interrupt request signals for the CPU 14 to the interrupt output block 114 via a time-multiplexed, serial interrupt request signal INTSDCABLE #. The interrupt receive block 132 provides interrupt request signals to the I ₂ O processor 1700 via a time-multiplexed, serial interrupt request signal INTSDIIO #, delivered via a PCI INTC # line 1709 of the bus 32 to the I ₂ O processor 1700 ,

The interrupt output block 114 provides the interrupt requests, determined via the CPU 14 to one or more of the standard PCI interrupt request lines (INTA #, INTB #, INTC #, and INTD #) of the PCI bus 24 , An interruption control unit 1900 , external to the bridge chip 26 , receives the interrupt requests from the PCI interrupt request lines of the PCI bus 24 , The interruption control unit 1900 prioritizes the interrupt requests (the interrupt requests from other devices on the PCI bus 24 and deliver them to the CPU 14 , The interrupt output block 114 For example, either asynchronously (when in an asynchronous mode), the interrupt request signals may be to the interrupt request lines of the PCI bus 24 or serially (if in a serial mode) it can supply the interrupt request signals to the INTA # line of the PCI bus 24 lead, as described below.

As in 95 4, all of the time-multiplexed serial data signals represent their data through an interrupt cycle 1850 which has eight consecutive time parts (T0-T7). The duration of each time part is one cycle of the PCI clock signal CLK. Each time portion represents a "snapshot" of the status of one or more interrupt request signals 99 1, the INTSDA # signal represents the sampled INTA # interrupt request signals from the slots 36a - f The signal INTSDB # represents the sampled INTB # interrupt request signals from the slots 36a - f The signal INTSDC # represents the sampled INTC # interrupt request signals from the slots 36a - f The signal INTSDD # represents the sampled INTD # interrupt request signals from the slots 36a - f For purposes of combining the interrupt signals INTSDA # -D # into the signal INTSDIIO #, the interrupt receive block is concatenated 132 Logically, the signals INTSDA # -D # together with AND, while simultaneously interrupt request signals, intended for the CPU 14 to be masked. Similarly, for purposes of combining the interrupt signals INTSDA # -D # into the signal INTSDCABLE #, the interrupt record block links 132 logically with AND signals INTSDA # -D # together, while simultaneously interrupt request signals, destined for the CPU 14 to be masked.

For the purpose of instructing the interrupt output block 114 if another interrupt cycle 1850 starts, provides the interruption recording block 132 a synchronization signal INTSYNCCABLE # to the interrupt output block 114 , The falling, or negative, edge of the INTSYNCCABLE # signal indicates that the time portion T0 of the interrupt cycle 1850 , transmitted via the signal INTSDCABLE # on the next positive edge of the CLK signal begins. A signal INTSYNCIIO # is used in an analogous manner to an incoming time slot T0 of the interrupt cycle 1850 , transmitted via the signal INTSDIIO #, display. The signal INTSYNCIIO # is passed through the interrupt receive block 132 to the I ₂ O processor 1700 via a PCI INTD # line 1710 of the bus 32 delivered. For the purpose of instructing the multiplexing circuit 1712 if another interrupt cycle 1850 via the interrupt signals INTS DA # -D #, the interrupt receive block provides 132 a synchronization signal INTSYNC # to the multiplexing circuit 1712 , The falling or negative edge of the signal of the INTSYNC # indicates that the multiplexing circuit 1712 should transmit the time portion T0 of the signals INTSDA # -D # on the next positive edge of the CLK signal.

As in 96 is shown, comprises the multiplexing circuit 1712 four multiplexers 1741 - 1744 which provide the signals INTSDA #, INTSDB #, INTSDC # and INTSDD #, respectively. The selection inputs of the multiplexers 1741 - 1744 receive a time division signal SLICEIN [2: 0] which is used to indicate the time portions T0-T7 of the signals INTSDA # -D #. The INTA-D # interrupt request signals from the slots 36 become inputs to the multiplexers 1741 - 1744 each delivered.

The signal SLICEIN [2: 0] is given by the output of a three-bit counter 1745 which is clocked on the positive edge of the PCI clock signal CLK. The interrupt synchronization signal INTSYNC # is triggered by a clocked enable input of the counter 1745 receive. The counter is set on the negative edge of the signal INTSYNC # 1745 back to zero (SLICEIN [2: 0] equals zero). The counter 1745 increases the value indicated by the SLICEIN [2.0] signal until the SLICEIN [2: 0] signal is equal to "7", where it remains until the counter 1745 is reset again by the INTSYNC # signal.

As in 97A for purposes of logging the time portions T0-T7, the interruption recording block is included 132 a three-bit counter 1750 which is clocked on the positive edge of the CLK signal. The counter 1750 provides an output signal SL1 [2: 0] through the select input of a 3x8 decoder 1752 Will be received. The decoder 1752 provides an eight-bit signal G_CNTR [7: 0], where the established bit of the signal G_CNTR [7: 0] indicates the time portion of the signals INTSDIIO # and INTSDCABLE #.

The INTSYNC # signal is through the output of an inverter 1774 which receives the most significant bit of the G_CNTR [7: 0] signal, G_CNTR [7]. Although the INTSYNC # signal is pulsed to low during the time portion T7, the interruption recording block could 132 alternatively, several cycles of the CLK signal after completion of an interrupt cycle 1850 , wait for a low pulse before the INTSYNC # signal pulses. The signals INTSYNCCABLE # and INTSYNCIIO # are both passed through the output of an inverter 1755 which receives the bit G_CNTR [0].

An additional interrupt request signal CAY_INT # for the CPU 14 is through the SIO circuit 50 delivered. The CAY_INT # signal is logically ANDed with the INTSDA # -D # signals linked to the time part T0. The CRY_INT # signal is passed through the output of an AND gate 1756 which receives a SIO_CMPL # signal, the SI_INTR # signal and an I ² C_INT # signal. The SIO_CMPL # signal is asserted or driven low when the SIO circuit 50 has completed a serial output process. The I ² C_INT # signal is asserted, or driven low, to indicate completion of a transaction over an I ² C bus (not shown) connected to the bridge chip 48 , The I ₂ C_INT # signal is otherwise removed, or driven low.

For purposes of masking interrupt requests, the interrupt receive block generates 132 four masking signals MASKA, MASKB, MASKC and MASKD. When the MASKA signal is asserted or driven high during a particular time portion (T0-T7) of the signal INTSDA #, an interrupt request indicated by the serial interrupt signal INTSDA # during that particular time is Slot, from the CPU 14 masked. If the MASKA signal is deasserted or driven low during the particular time portion, the interrupt request will be indicated by the serial interrupt signal INTSDA # from the I ₂ O processor 1700 masked. The MASKB-D signals operate similarly to the masking interrupt requests provided by the signals INTSDB # -D #.

As in 97B is shown, provides a multiplexer 1758 the MASKA signal. The selection input of the multiplexer 1758 receives the SL1 [2: 0] signal. The eight inputs of the multiplexer 1758 receive inverted IIO_SUB [5: 0] signals for corresponding bits of the I ₂ O sub-register 1728 are indicative. The signals IIO_SUB [5: 0] are sent to the appropriate inputs of the multiplexer 1758 connected so that when the INTSDA # signal is the interrupt status for a particular slot or slot 36 indicates the MASKA signal at the same time the assigned bit of the register 1728 for this slot 36 displays. Three other multiplexers 1760 . 1762 and 1764 provide the signals MASKB, MASKC and MASKD respectively. Similar to the generation of the MASKA signal, the signals IIO_SUB are [5: 0] with the appropriate inputs of multiplexers 1760 . 1762 and 1764 connected so that the MASKB, MASKC and MASKD signals are the bit of the register 1728 assigned to the slot represented by the signals INTSDB #, INTSDC # and INTSDD #. The multiplexers 1760 - 1764 receive the signal SL1 [2: 0] at their select inputs.

As in 97C is illustrated includes the interruption recording block 132 also two multiplexers 1768 and 1770 , the two masking signals IIOTS_D and IIOTS_C, used to mask the INTD # and INTC # signals provided by the slot interrupt lines of the I ₂ O processor 1700 , deliver, as the wires 1709 and 1713 to use the signals INTSDIIO # and INTSYNCIIO # respectively to the I ₂ O processor 1700 to deliver. The select inputs of both multiplexers 1768 and 1770 receive the signal SL1 [2: 0], and the signal inputs of the multiplexer 1768 and 1770 receive signals IIOSLOT [5: 0] corresponding to the corresponding bits of the I ₂ O slot register 1730 are indicative. The signals IIOSLOT [5: 0] are provided with the appropriate inputs from multiplexers 1768 and 1770 connected so that when the INTSDC # -D # signals the interrupt status for a particular slot 36 indicate the IIOSLOT [5: 0] signal selected by the multiplexers 1768 and 1770 , at the same time the allocated bit of the register 1730 for this step 36 displays.

As in 97D shown are six AND gates 1772 - 1782 used to combine the signals INTSDA # -INTSDD # and selected interrupt request signals from the CPU 14 to mask. The AND gate 1772 receives an inverted ECC_ERR_DOWN # signal (asserted to be an error detected by the chip 48b for cable transmissions) and the G_CNTRL [0] bit. The AND gate 1774 receives an inverted INTSDA # signal and the MASKA signal. The AND gate 1776 receives an inverted INTSDB # signal and the MASKB signal. The AND gate 1778 receives an inverted INTSDC # signal, the MASKC signal and the IIOTS_C signal. The AND gate 1780 receives an inverted INTSDC # signal, the MASKD signal and the IIOTS_D signal. The AND gate 1782 receives an inverted CAY_INT signal and the G_CNTRL signal.

The outputs of the AND gates 1772 - 1782 are as inputs to an OR gate 1784 connected its output to the signal input of a flip-flop 1786 owned by the D-type. The flip-flop 1786 is clocked on the positive edge of the CLK signal, and the set input of the flip-flop 1786 receives the RST signal. The inverting output of the flip-flop 1786 returns the INTSDCABLE # signal.

Four AND gates 1790 - 1796 are used to combine the INTSDA # -D # signals and selected interrupt request signals from the I ₂ O processor 1700 to mask. The AND gate 1790 receives an inverted INTSDA # signal and an inverted MASKA signal. Another Input of the AND gate 1790 is at the output of a NOR gate 1802 which masks the INTSDA # signal during the time parts T0 and T7 since no card and interrupt requests are included in these time parts. The NOR gate 1802 receives bits G_CNTRL [0] and G_CNTRL [7]. The AND gate 1732 receives an inverted INTSDB # signal and an inverted MASKB signal. Another input of the AND gate 1792 is at the output of a NOR gate 1804 which masks the INTSDB # signal during the time portions T1 and T4 because no card interrupt requests are included in these time portions. The NOR gate 1802 receives bits G_CNTRL [1] and G_CNTRL [4].

The AND gate 1794 receives an inverted INTSDC # signal and an inverted MASKC signal. Another input of the AND gate 1794 is at the output of a NOR gate 1806 connecting the INTSDC # signal during the time parts T2 and T5, since no card interruption requests are included in these time parts. The NOR gate 1806 receives bits G_CNTRL [2] and G_CNTRL [5]. The AND gate 1796 receives an inverted INTSDD # signal and an inverted MASKD signal. Another input of the AND gate 1796 is at the output of a NOR gate 1808 which masks the INTSDD # signal during the time parts T3 and T6 since no card interrupt requests are included in these time parts. The NOR gate 1808 receives bits G_CNTRL [3] and G_CNTRL [6].

The outputs of the AND gates 1790 - 1796 are as inputs with an OR gate 1798 connected, which has an output to the signal input of a flip-flop 1800 owned by the D-type. The flip-flop 1800 is clocked on the positive edge of the CLK signal and the set input of the flip-flop 1800 receives the RST signal. The inverting output of the flip-flop 1800 returns the INTSDIIO # signal.

As in 98 is illustrated includes the interrupt output block 114 a three-bit counter 1820 from a common design to the counter 1745 , The counter 1820 is clocked on the positive edge of signal CLK, provides an output signal G_CNTR2 [2: 0], and starts counting from 0 to 7 after being reset by the INTSYNC # signal.

For purposes of providing the INTSYNCCPU # signal, the interrupt output block comprises 114 a flip-flop 1822 of the D-type, which is clocked on the positive edge of the CLK signal. The setting input of the flip-flop 1822 receives the RST signal and the signal input of the flip-flop 1822 receives the INTSYNCCABLE # signal. The non-inverting output of the flip-flop 1822 returns the INTSYNCCPU # signal.

For purposes of providing the INTSDCPU # signal, the interrupt output block comprises 114 a flip-flop 1824 of the D-type, which is clocked on the positive edge of the CLK signal. The setting input of the flip-flop 1824 receives the RST signal and the signal input of the flip-flop 1824 receives the INTSDCABLE # signal. The non-inverting output of the flip-flop 1824 returns the INTSDCPU # signal.

The interrupt requests received by the interrupt receive block 114 , become the interruption control unit 1900 either supplied asynchronously or serially. In asynchronous mode, the interrupt requests become the four PCI interrupt lines (commonly referred to as "barber poling") on the PCI bus 24 listed, like this in 100 is shown.

For purposes of holding the interrupt information provided by the INTSDCABLE # signal, the interrupt output block comprises 114 an eight-bit register 1826 , All signal inputs receive the INTSDCABLE # signal. The load enable inputs of bits 0-7 receive bits G_CNTR [0] -G_CNTR [7], respectively. Therefore, for example, during the time part T4, a bit 3 is loaded with the value represented by the INTSDCABLE # signal. Bits 0 (represented by an INT_A1 signal) and 4 (represented by an INT_A2 signal) are listed in a CPUINTA # signal. Bits 1 (represented by an INT_B1 signal) and 5 (represented by an INT_B2 signal) are listed in a CPUINTB # signal. Bits 2 (represented by an INT_C1 signal) and 6 (represented by an INT_C2 signal) are listed in a CPUINTC # signal. Bits 3 (represented by an INT_D1 signal) and 7 (represented by an INT_D2 signal) are listed in a CPUINTD # signal.

Four OR gates 1828 - 1834 provide the CPUINTA #, CPUINTB #, CPUINTC #, and CPUINTD # signals to the PCI interrupt lines INTA #, INTB #, INTC #, and INTD #, respectively, of the PCI bus 24 to be delivered. The OR gate 1828 has an input with the output of an AND gate 1836 connected. The AND gate receives an inverted CM signal. The signal CM is passed through a bit of a configuration register of the bridge chip 26 is delivered and set up, or driven high to indicate the asynchronous mode, and is taken off or driven low to the synchronous mode display. The AND gate 1836 also receives the signal INT_A1, the signal INT_A2, and an ECC_ERR_UP signal (used to indicate a fault in cable transmissions).

The OR gate 1828 has an input to the output of an AND gate 1838 connected. The AND gate 1838 receives the CM signal and the INTSDCPU # signal. Another input of the AND gate 1838 is with the output of an OR gate 1848 connected. The OR gate 1848 receives the ECC_ERR_UP signal and the G_CNTR2 bit [0].

The OR gate 1830 has an input to the output of an AND gate 1840 connected and an input to the output of an AND gate 1842 connected. The AND gate 1840 receives an inverted CM signal, the signal INT_B1, and the signal INT_B2. The AND gate 1842 receives the signal CM and an inverted bit G_CNTR2 [0] (uses the "sync" signal to the interrupt controller 1900 during the serial mode).

The OR gate 1832 has an input to the output of an AND gate 1844 and connected to an input receiving the CM signal. The AND gate 1844 receives an inverted CM signal, the INT_C1 signal and the INT_C2 signal. The OR gate 1834 has an input to the output of an AND gate 1846 and connected to an input receiving the CM signal. The AND gate 1846 receives an inverted CM signal, the INT_D1 signal and the INT_D2 signal.

Other embodiments are within the scope of the following claims. For example can different types of buses are used, including any one Type of host bus or peripheral bus. A180, the bridge chip, can, for. A host-to-peripheral bus bridge, a host-to-host bus bridge or a peripheral-to-peripheral bridge be.

Claims (19)

A computer system comprising: a data storage device ( 20 . 18 ) on a first data bus ( 24 ); a requesting device ( 327A . 327B ), which, on a second data bus ( 32 ), an initial request directed to the data storage device ( 20 . 18 ) and the control of the second data bus ( 32 ) while awaiting a response to the initial request; a bridge device ( 26 . 48 ), which the data buses ( 24 . 32 ), which, upon the initial request, subsequently request on the first data bus ( 24 ) and begins, on the first data bus, the requested data from the data storage device ( 20 . 18 ), the bridge device ( 26 . 48 ) is arranged to respond to the re-submission of the initial request from the requesting device, and characterized in that, when the requesting device is again in control of the second data bus ( 32 ), upon a re-submission of the initial request, the bridge is operable to begin requesting the requested data to the requesting device ( 327A . 327B ) on the second bus, even while the data storage device ( 20 . 18 ) nor the requested data to the bridge device ( 26 . 48 ) on the first bus. The system of claim 1, further comprising a bus arbitrator ( 124 ), which assigns a higher bus arbitration priority to the requesting device to restore control of the second data bus (FIG. 32 ) when the data storage device ( 20 . 18 ) begins, the requested data to the bridge ( 26 . 48 ). The system of claim 1, wherein the requesting device maintains the higher priority until the data storage device (16) 20 . 18 ), data about the bridge ( 26 . 48 ). The system of claim 1, wherein when the data storage device ( 20 . 18 ) begins to provide the requested data to the bridge device ( 26 . 48 ), the bridge device initiates a transaction after the requesting device initiates control of the bus ( 32 ) gives up, finished. System according to claim 1, wherein the bridge device ( 26 . 48 ) a transaction on one of the data buses ( 24 . 32 ) to allow the requesting device to communicate with the second data bus (FIG. 32 ) while the data storage device ( 20 . 18 ) the requested data on the first data bus ( 24 ). The system of any one of claims 3 to 5, wherein after the transaction is completed, the requesting device is assigned a higher bus arbitration priority to re-establish control of the second data bus ( 32 ) to obtain. The system of claim 1, wherein the first data bus ( 24 ) and the second data bus ( 32 ) each have a PCI bus, and wherein the bridge device ( 26 . 48 ) has a PCI-to-PCI bridge. System according to claim 6, wherein the bridge ( 26 . 48 ) terminate a transaction on the second PCI bus ( 32 ), when the data storage device ( 20 . 18 ) begins to provide the requested data. A system according to any one of claims 1 to 8, further comprising a bus arbitrator ( 124 ), which assigns a higher bus arbitration priority to the PCI device in order to restore control of the second data bus (FIG. 32 ), when the memory device ( 20 . 18 ) begins, the requested data to the bridge ( 26 . 48 ). The system of claim 9, wherein the bus arbitrator ( 124 ) assigns a higher bus arbitration priority to the requesting device after the transaction is completed. The system of any one of claims 1 to 10, wherein the request from the requesting device a memory read multiple request having. Method for generating a data flow directly from a data storage device ( 20 . 18 ) on a first data bus ( 24 ) in a computer system to a requesting device ( 327A . 327B ), which, on a second data bus ( 32 ), a request directed to the data storage device ( 20 . 18 ), the method comprising: forcing the requesting device ( 327A . 327B ), a controller of the second data bus ( 32 ) after the request on the second data bus ( 32 ) while waiting for a response to the request; wherein, upon request, a bridge device ( 26 . 48 ), the first and the second data bus ( 24 . 32 ), subsequently connecting the request on the first data bus ( 24 ) and the requested data on the first data bus from the storage device ( 20 . 18 ) receives; characterized by granting the request to regain control of the second bus when the requesting device ( 327A . 327B ) the request on the second data bus ( 32 ), and allowing the bridge device ( 26 . 48 ) begins to process the requested data to the requesting device ( 327A . 327B ) on the second bus, even while the data storage device ( 20 . 18 ) nor the requested data to the bridge device ( 26 . 48 ) on the first bus. The method of claim 12, further comprising terminating another transaction resident on the second data bus (10). 32 ) occurs when the requesting device resumes control of the second data bus ( 32 ) demands. The method of claim 12, further comprising terminating a transaction on the second data bus ( 32 ) occurs when the requested data begins to be retrieved from the storage device ( 20 . 18 ) to flow. The method of claim 13, wherein the completed transaction a write transaction having. The method of claim 13, wherein the completed transaction has a posted write transaction. The method of claim 12, wherein the completed transaction a read transaction having. The method of claim 12, further comprising associating to the requesting device of higher bus arbitration priority, after the transaction is completed. The method of any one of claims 12 to 18, further comprising, after establishing the data flow from the data storage device (12). 24 ) assigns, to the requesting device, a bus arbitration priority higher than that of any other device attempting to connect the second data bus (FIG. 32 ) to control.