DE69708215T2 - Analog to digital converter - Google Patents

Description

The invention relates to analog/digital converters, i.e. electronic circuits capable of converting an analog input signal into a precise digital value representing the amplitude of the analog signal. The digital value is obtained in the form of a word made up of several bits, generally with pure binary coding.

There are several conversion methods, and the choice of one of them depends on the properties that the converter should have. The most important parameters for these properties are:

- the resolution, which is defined by the number of bits of the output word and represents exactly the amplitude of the analog signal. The number of bits can be 16 to 18 or even 20 for the most precise converters and the accuracy is generally defined by half of the bit of least weight;

- the speed, i.e. the number of conversion operations that can be performed in one second;

- power consumption; a fast and precise converter consumes significantly more energy than a slow and inaccurate converter. However, power consumption leads to heating of the integrated chip on which the converter is implemented. This heating must be compensated by cooling agents, which make it difficult to use the circuit when space is limited. With the increasing use of portable devices powered by batteries, the criterion of high power consumption is becoming synonymous with a short operating time of the device;

- and of course the costs of designing and manufacturing the converter, which depend in particular on the size of the chip occupied by the converter.

The qualities of an analog-to-digital converter are based on a compromise between the above parameters, and an aim of the present invention is to improve this compromise.

Among the known structures of analog/digital converters, the following can be cited:

- The multiple approximation converters, which compare the analog input signal Vin one after the other with digital values that are each a little closer to the value of the analog signal; these converters operate in at least N phases when the value is encoded over N bits. They are therefore generally very slow for an accuracy that exceeds six or eight bits. The so-called flash converters, which use 2N comparators in parallel; the comparators receive the analog signal on one side and one of 2N reference voltages defined by a chain of 2N precision resistors on the other. These converters are very fast (generally only two phases) but take up a lot of space and consume a lot of power when N reaches 10 or 12 bits.

- The mixed converters, which have a coarse converter to define the high-weighted hits and a fine converter to define the low-weighted bits. The coarse converter can be fast and only slightly accurate (e.g. four to six bits). The fine converter must be accurate, even if it is slower.

In the area of mixed converters, several solutions have already been proposed:

In one case, the coarse converter is a flash converter that supplies P bits, i.e. the bits with a higher weighting. This value is converted back into an analog signal by a digital/analog converter with P bits. The difference between the analog signal Vin and this converted value, which is also called the remainder, is calculated by a fine converter. which determines the bits of low importance of the conversion. This provides a gain in power consumption and space compared to a flash converter, but the digital-to-analog conversion requires time and precise control of the gains of the different parts of the circuit (analog-to-digital converter and digital-to-analog converter).

In another case, the coarse converter is a parallel subrange selection type circuit. It consists of a selection circuit for a group (or range) of three adjacent reference voltages from a number (or range) of more than three reference voltages.

This circuit can compare the input signal Vin with the various reference voltages and then select a group of three adjacent main reference voltages such that Vin lies between these reference voltages. Then the connections required between these three reference voltages, three differential amplifiers and a fine converter circuit are made.

The coarse converter provides (via a flash converter) a digital value that indicates the group of three reference values between which Vin lies.

A range of adjacent reference voltages is thus determined which frames Vin as closely as possible. Such a structure was described in patent FR-A-2 699 025.

Within this main reference voltage range, Vin is then finely encoded by generating new intermediate reference values at equal intervals. There are various methods for this, but in any case the number of intermediate reference voltages must be doubled each time the accuracy of the fine encoding is to be increased by a factor of two (i.e. by one bit).

These intermediate reference values are generated by so-called interpolation circuits. The latter can be parallel or series interpolation circuits.

In parallel interpolation circuits, the number of components (resistors, amplifiers, etc.) increases in proportion to the number of intermediate reference values, i.e. by a factor of two for every one-bit increase in the precision of the fine coding. For N bits, this results in 2N components. One quickly reaches the limits of the available space and power consumption.

In series interpolation circuits, however, only N elements are required to obtain N bits of information.

The gain in terms of space requirements and power consumption is therefore considerable compared to parallel interpolation.

Such structures have been described in patents US-A-5 126 742 and FR-A-2 699 025.

In these circuits, the number of generated intermediate reference values increases by a factor of two at the output of each interpolation circuit. The latter all have the same structure and are suitable for cascade arrangements.

The signals are periodic functions of the analog input voltage Vin in sinusoidal form. These new signals pass through zero not only when Vin is equal to the main reference voltages, but also for intermediate reference voltages located in the middle of the interval between two adjacent main reference voltages.

The signals therefore provide an additional bit of information compared to the high-weighted bits determined in the coarse converter. The bits thus obtained at the output of a series interpolation circuit or stage are applied to the next stage, which is constructed in exactly the same way and has the same function as the previous stage (generation of signals whose "period" is again doubled).

The next stage provides another bit for the value of Vin.

This is continued by several stages in cascaded to obtain the successive bits of lower weight of the conversion (note that these "folded" sinusoidal signals consist of static points that depend on the static values of Vin, and therefore not primarily on time).

However, one important disadvantage of the circuits that perform the folding must be mentioned: the use of folded signals requires, by design, the use of highly nonlinear elements, which contradicts the formation of precise intermediate voltages.

The new values of the intermediate reference voltages are therefore not equally spaced and the accuracy of the quantification of Vin decreases.

Regardless of which interpolation method is used for the fine conversion, the intermediate reference voltages generated between the main reference voltages should have as equal distances as possible.

Any inaccuracy in this parameter limits the accuracy of the fine coding of Vin. Thus, although series interpolation circuits have solved the problems of space and power consumption compared to parallel interpolation circuits, they have difficulty providing a coding accuracy higher than 10 bits.

This is directly due to the nonlinearity of the folding method used.

The aim of the invention is therefore to propose a new structure of an analog/digital converter with which both a small space requirement and low power consumption as well as high accuracy can be achieved.

Therefore, the subject of the invention is a method for analog/digital conversion of an input voltage Vin, which uses several interpolation circuits in cascade, characterized in that

- three pairs of analog signals coming from three pairs of outputs of a preceding interpolation circuit of rank k are applied to the input of an interpolation circuit of rank k-1, the signals of a pair having equal values when the voltage Vin is equal to one of three main reference voltages of rank k-1 each associated with a pair, and these three voltages define between them a voltage interval composed of two half-intervals of rank k-1,

- from these three pairs of signals P = 2P+1, pairs of interpolation signals (p > 1, P > 3) are generated, each containing two interpolation signals varying symmetrically and monotonically as a function of the voltage Vin, the signals of a pair being equal when the voltage Vin is equal to a reference voltage associated with this pair, and the P reference voltages associated with the P pairs essentially corresponding, on the one hand, to the three main reference voltages of rank k-1 and, on the other hand, to at least two intermediate voltages located in the middle of the half-intervals defined by the three main reference voltages of rank k-1, these P reference voltages being able to define 2P-1 voltage intervals whose width is equal to a fraction 1/2P-1 of the interval of rank k-1,

- depending on the levels of the three pairs of input signals, it is determined which of the 2P-1 intervals is the voltage interval that best frames the input voltage Vin, this interval being made up of two half-intervals delimited by three of the P reference voltages, which are called main reference voltages of rank k,

- one selects from the P pairs the three pairs associated with the three reference voltages of rank k and one applies these three pairs to the output of the interpolation circuit of rank k.

The corresponding converter structure contains several Interpolation circuits in cascade with at least one interpolation and selection circuit of rank k, comprising:

- three pairs of inputs receiving as input signals three pairs of output signals from a preceding interpolation circuit, the signals of a pair having equal values when the voltage Vin is equal to one of the three main reference voltages of rank k-1 each associated with a corresponding pair, and these three voltages together defining an interval composed of two half-intervals of the voltage of rank k-1,

- means for generating, from the input signals P = 2P+1, pairs of interpolation signals (p > 1 and P > 3), each pair being associated with two interpolation signals which vary symmetrically and monotonically as a function of the voltage Vin, and the signals of a pair being equal when the voltage Vin is equal to a reference voltage associated with that pair, and the P reference voltages associated with the P pairs essentially forming, on the one hand, the three main reference voltages of rank k-1 and, on the other hand, P-3 intermediate reference voltages, and the P reference voltages can define 2p-1 voltage intervals whose width corresponds to a fraction 1/2P-1 of the interval of rank k-1,

- decision means for determining, depending on the levels of the three input signal pairs, which of the 2p-1 intervals is the voltage interval that best frames the input voltage Vin, this interval consisting of two half-intervals delimited by three of five reference voltages, these three reference voltages being called the reference voltages of rank k,

- and means for selecting from the P pairs the three pairs associated with the three reference voltages of rank k to apply them to the output of the interpolation circuit of rank k.

Applied to the case where p = 2 and P = 5, the invention proposes an analogue/digital converter having an input for receiving the analogue voltage Vin to be converted and characterized in that it comprises a sequence of interpolation and selection circuits in cascade with at least one interpolation and selection circuit of rank k and comprising:

- three pairs of inputs receiving as input signals three pairs of output signals from an interpolation circuit of rank k-1, the signals of a pair having equal values when the voltage Vin to be converted is equal to one of the three main reference voltages of rank k-1, and these three voltages together define an interval composed of two voltage half-intervals of rank k-1,

- means for generating, from the input signals, five pairs of interpolation signals, each pair comprising two interpolation signals varying symmetrically and monotonically as a function of the voltage Vin, the signals of a pair being equal when the voltage Vin is equal to a reference voltage associated with that pair, and the five reference voltages associated with those five pairs essentially constituting, on the one hand, the three main reference voltages of rank k-1 and, on the other hand, two intermediate reference voltages located in the middle of the half-intervals defined by the three main reference voltages of rank k-1, and the five reference voltages can define three voltage intervals whose width corresponds to that of a half-interval of rank k-1,

- decision means for determining the five reference voltages which define an interval of width equal to a half-interval of rank k-1 and best frame the input voltage Vin, these selected reference voltages being the three main reference voltages of rank k,

- and means for selecting from the five pairs of interpolation signals the three pairs such that the signals of a pair are equal when the voltage Vin is equal to one of the main reference voltages of rank k.

This cascade structure uses monotonic signals that cross at a common point for each stage, in contrast to the state of the art, which uses periodic convolved signals that cross at numerous points.

The interpolation and selection circuit of rank k provides one or two information bits of rank k, linked to the value of the voltage Vin to be converted. The successive circuits of increasing rank each time determine a voltage interval that frames the voltage Vin as closely as possible, and the interval defined for the circuit of rank k is half the width of the interval defined for rank k-1.

The converter defined in this way can be used as an autonomous converter on its own, or as a fine converter in a structure with a coarse converter for the bits with higher weighting and a fine converter for the bits with lower weighting.

The rank 1 interpolation and selection circuit preferably receives as input signals the differential outputs of three differential amplifiers, which in turn receive the voltage Vin to be converted at a first input and one of three main reference voltages at a second input. These amplifiers each provide two output voltages, which vary symmetrically and monotonically depending on the voltage Vin to be converted. The main reference voltages are spaced apart from one another such that the curves of the output voltages of the amplifier corresponding to the central main reference voltage cross the curves of the output voltages of the other two amplifiers in a linear zone of these output voltages.

In practice, the interpolation circuits contain five differential amplifiers, a decision circuit and a selection circuit controlled by the decision circuit to pass the outputs of three differential amplifiers selected from the five differential amplifiers to the outputs of the circuit.

However, it is also possible to generalize the conversion structure according to the invention by using interpolation and decision circuits containing more differential amplifiers and able to select a voltage interval of rank k from seven intervals or even 15 rather than just three. This can be useful for reducing the number of cascade stages, but of course increases the number of differential amplifiers used in each stage since nine or 17 reference voltages must be generated from which three must be selected.

Finally, it should be noted that the prior art according to European patent application EP-A-0 406 973 discloses a converter employing the principle of overlapping voltage ranges for each successive approach, but not the principle of selecting three pairs of output signals from 2P+1 pairs to feed three inputs of a subsequent stage.

Other features and advantages of the invention will now be explained in more detail with reference to the accompanying drawings.

Fig. 1 shows schematically the general structure of the converter according to the invention.

Fig. 2 shows a typical circuit diagram of a differential amplifier such as amplifier A1 in Fig. 1.

Fig. 3 shows the output voltage curve of one of the input differential amplifiers as a function of the voltage Vin to be converted.

Fig. 4 shows the superposition of the curves of the output voltages of the three input differential amplifiers.

Fig. 5 explains the principle of successive approach to Vin by selecting voltage ranges.

Fig. 6 shows the waveform of the output signals of the rank 1 interpolation and selection circuit in comparison with the other signals generated in this circuit but not selected.

Fig. 7 shows the general configuration of an interpolation and selection circuit, e.g. the circuit CIS1 in Fig. 1.

Fig. 8 shows the circuit diagram of a differential amplifier with increased linearity, as used according to the invention.

Fig. 9 shows a practical circuit diagram of a selection circuit for three signal pairs from five pairs, which in turn are formed on the basis of three pairs of input signals.

Fig. 10 shows a decision circuit with which three pairs of signals can be selected from five pairs.

Fig. 11 shows a voltage diagram that provides the logical rationale of the decision circuit of Fig. 10.

Fig. 12 shows a structure of a decoder formed by cascaded adders and providing a digital value for Vin.

Fig. 13 shows a variant of the implementation of the interpolation and selection circuit, with which one can select three pairs of signals from nine signal pairs to select a sub-range from seven sub-ranges.

The general structure of the converter according to the invention is shown in Fig. 1.

The task of this converter is to provide a digital signal over n bits, which represents in digital form the value of the amplitude of an input signal Vin. The n bits result in a binary code for a value of Vin from 2n evenly distributed between two main reference voltages VRA and VRB.

The input signal Vin can take any value between two limit values Vext1 and Vext2, which can also exceed the range of values between VRA and VRB, but in all cases the output of the converter provides a digital value for Vin only if Vin is between VRA and VRB. However, it is shown that the converter can also provide an overshoot signal up or down, indicating whether the signal Vin has left the range between VRA and VRB.

The main reference voltages VRA and VRB as well as another main reference voltage VRM, which maintains the same distances from the values VRA and VRB, are each applied to a first input of a differential amplifier A1 (for VRB) or A2 (for VRM) or A3 (for VRA).

The reference voltages are generated in any way, but preferably via a chain of precision resistors that lies between two global reference potentials VA and VB. The intermediate taps in this chain are calculated in such a way that the main reference voltages VRV, VRM and VRA are obtained.

Each differential amplifier has a second input to which the input voltage Vin to be converted is applied. Preferably, this voltage comes from the output of a sample and hold circuit ECHB. The output voltage Vin of this circuit periodically supplies the value of the voltage Ve at the input of the circuit and keeps this value constant between two consecutive sampling times. In the following, it is assumed that Vin forms the input signal of the converter, although the analog signal to be converted is in reality the signal Ve.

The ECHB sample and hold circuit allows the value of the signal to be converted to be temporarily kept constant in order to perform the conversion using a stable input value.

The differential amplifiers A1, A2, A3 are identical.

The special features of their transfer function (which represents the course of their output voltage depending on their input voltage) will be explained later. However, it can already be said here that these transfer functions are obtained with completely conventional amplifiers, which in the simplest design are formed, for example, by a pair of differential branches that are globally fed by a constant current source and have an input transistor and a load resistor in each branch. Fig. 2 shows such a differential amplifier A1.

Each differential amplifier has two differential outputs. It delivers two voltages to these outputs which vary symmetrically depending on the value of Vin, essentially linearly around a mean value Vm which is the same for the two outputs and identical for all three amplifiers. This mean common value is obtained at the output of an amplifier when the voltages at the two inputs of this amplifier are equal. The amplifiers are also designed so that the voltages at the differential outputs vary monotonically with Vin for the entire possible range of values of Vin (in the interval from VRB to VRA, and beyond this range between Vext1 and Vext2 of the possible values of Vin).

Fig. 3 shows the course of the two output differential voltages V1A0, V1B0 for a single amplifier A1. The curves do not show the time course of the output voltages, but the course of these voltages depending on the value of the input voltage Vin. These curves V1A0, V1B0 represent the usual transfer functions of a simple symmetrical differential amplifier with two input transistors and a first input that receives the reference voltage VRB and a second input that receives Vin. The curves V1A0 and V1B0 are symmetrical and monotonous and cross at a point with the abscissa VRB and the ordinate Vm, where Vm is the value of the common potential of the outputs for an input differential voltage of zero (Vin = VRB).

The regions of the curve around the crossover point and well beyond it are linear. Moving further away from it, they approach asymptotically two extreme values of the output potential, which depend on the amplifier supply voltages and currents. The slope of the linear regions is lower if an emitter resistor is placed in series with the emitter of the transistor in each branch of the amplifier. The linearity of the linear region is also improved with such an emitter resistor, and it might therefore be useful to use differential amplifiers with emitter resistors.

It is important to ensure good linearity and good agreement of the average voltage values Vm for the three amplifiers, and linearity correction circuits can preferably be associated with amplifiers A1, A2 and A3 (see below).

Fig. 4 shows the six output voltages V1A0/V1B0 for A1, V2A0/V2B0 for A2 and V3A0/V3B0 for A3. These curves are equal to each other but are offset from each other since they are centered on three different main reference voltages VRB, VRM and VRA.

The following remarks can be derived from the curves of the output signals of the amplifiers A1, A2 and A3:

- On the one hand, in the circuit of Fig. 1, one can provide a comparator CMPX which receives the output signals of the first amplifier A1 and supplies a logic signal DX of undershoot (Vin < VRB), and a comparator CMPY which receives the output signals of the third amplifier A3 and supplies a logic signal of overshoot (Vin > VRA).

- If the amplifiers A1, A2, A3 are linear in a fairly large and equal range, then the following special features arise:

a) The curves of the symmetrical pair V1A0/V1B0 intersect in the center of their linear zone, as do the curves of the pairs V2A0/V2B0 and V3A0/V3B0.

b) The curves of the cross-pair V1A0/V2B0 (or the other cross-pair V2A0/V1B0) also cross in their linear zones (but not in their centre) for values of Vin equal to a fictitious intermediate reference voltage V'RB located in the middle of the half-interval VRB/- VRM .

c) The curves of the cross-pair V2A0/V3B0 (or the other cross-pair V3A0/V2B0) also cross in their linear zones (but not in their centre) for values of Vin equal to a fictitious intermediate reference voltage V'RA located in the middle of the half-interval VRM/- VRA.

If the symmetrical pair of signals V1A0/V1B0 is applied to a new symmetrical and linear differential amplifier, this amplifier will provide a new pair of signals varying monotonically and symmetrically as a function of Vin, the curves of the course of these signals crossing again at the center of their linear zone when Vin is equal to the main reference voltage VRB. The same applies to the pair V2A0/V2B0 with respect to the reference voltage VRM, and for the pair V3A0/V3B0 the curves crossing at their center when Vin is equal to the main reference voltage VRA.

If the crossover pair V1A0/V2B0 is applied to a linear symmetrical differential amplifier, this amplifier delivers a new pair of signals whose course is monotonic and symmetrical depending on Vin. The curves of the course of these signals cross in the center of their linear zones (which was not the case for the pairs of curves V1A0/V2B0 themselves) for a value of the input voltage Vin = V'RB.

The same applies to the crossover pair V2A0/V3B0, which, when applied to a symmetrical linear differential amplifier, produces two signals whose monotonic and symmetrical curves cross at their center when Vin = V'RA.

The additional differential amplifiers mentioned above can therefore be used to form five pairs of signals that can be called interpolation signals, namely:

- three pairs that are completely analogous to the output signals of the amplifiers A1, A2, A3, with the crossing points of their curves corresponding to the three main reference voltages VRB, VRM and VRA,

- two additional pairs, very similar to the first three pairs, but whose curves are inserted between those of the other three pairs, the crossing point of one pair being for Vin = V'RA and that of the other pair being for Vin = V'RB, i.e. for the two fictitious intermediate reference voltages.

Below we will discuss the waveforms of the output signals of these additional differential amplifiers, which, as shown, belong to an interpolation cell CI1, which in turn is part of an interpolation and selection circuit CIS1 in a structure with several interpolation and selection circuits in cascade.

The reference voltage range in which the five reference voltages are located is the range from VRB through VRM to VRA, which can be referred to as the rank 0 range, and is divided into two rank 0 half-intervals, which are the VRB/VRM and VRM/VRA half-intervals.

According to the invention, within this range of rank 0, a range of rank 1 of half the size, ie a width equal to a half interval of rank 0, is selected. This range of rank 1 has as end points two of the five reference voltages of the range of rank 0 and as center another of these five reference voltages.

There are three possibilities, namely the area (VRB, VR'B, VRM), the area (VR'B,VRM, VR'A) and the area (VRM, VR'A, VRA).

The range that surrounds the voltage Vin as closely as possible is chosen, which is possible by comparing the values of the three pairs of output signals from amplifiers A1, A2, A3 (detailed explanations of this comparison are given below). The three ranges overlap, i.e. the central range extends into the other two ranges.

Selecting one of three ranges simply means selecting three pairs of signals from among the five pairs of signals formed by five differential amplifiers in the interpolation circuit CIS1.

The rank 1 interpolation circuit, CIS1, thus forms five pairs of signals with an interpolation cell CI1 containing five differential amplifiers, but it only delivers three selected pairs at its output, called VIA1/VIB1, V2A1/V2B1, V3A1/V3B1. The selected pairs are those corresponding to three reference voltages that frame the input voltage Vin as closely as possible.

A decision circuit CD1 is therefore associated with the cell CI1 to control the selection of three of the five pairs, the unit consisting of CD1 and CI1 forming the interpolation circuit CIS1 of rank 1.

Three pairs of signals were therefore developed, the waveform of which, depending on Vin, is similar to that of the output signals of the three amplifiers A1, A2, A3 and which intersect for three selected reference voltages, which are now called main reference voltages of rank 1. These reference voltages are fictitious and, just as the three real reference voltages VRB, VRM, VRA defined a voltage interval of rank 0 with the amplitude VRA-VRB, These three fictitious reference voltages form a voltage interval or a voltage range of rank 1 which is half the size of that of rank 0 and is centred as closely as possible on the voltage Vin.

The interpolation circuit CIS1 is also able to provide information on the selected voltage range, since the circuit itself selects this range, and this information (for example two bits for selecting one of three ranges) can of course be used for the analogue/digital conversion of Vin, since it corresponds to a selection of the range best centred on Vin. The digital information thus obtained is of course a rough approximation of Vin, i.e. it results in a bit of conversion with a high weight. It will be explained below how exactly this information is evaluated, but it can already be said here that the information on the range selection is transmitted to a decoding circuit DEC, which produces the digital value B0, B1, ..., Bn of the analogue/digital conversion of Vin.

Now only the three pairs of output signals of the CIS1 circuit must be used for further transmission to a series of further interpolation circuits in cascade, namely CIS2, ..., CISn, which are similar to the CIS1 circuit. Each circuit receives three pairs of signals and processes five, and selects three for the next circuit. In each stage, the three signal pairs have the same course as shown in Fig. 4, i.e.

- their curves are monotonic according to Vin,

- the courses of a pair are symmetrical to each other and intersect at their centre, which defines a main reference voltage, so that the three pairs define three main reference voltages,

- the curves of one pair intersect with the curves of the adjacent pair in their linear zones and define two intermediate reference voltages,

- the curves of the three pairs are compressed and their distances are each reduced by half compared to the distances of the curves of the previous stage,

- and that Vin always lies within the range defined by the three main reference voltages, which narrows from stage to stage.

Therefore, an interpolation and selection circuit CISk of rank k receives three pairs of signals V1Ak-1/V1Bk-1, V2Ak-1/V2Bk-1, V3Ak-1/V3Bk-1. The signal pairs vary as a function of Vin according to symmetrical and monotonic curves which intersect at the center of their linear zones for three main reference voltages of rank k-1 defining a range of rank k-1. The circuit CISk forms five signal pairs and selects three which are the signal pairs V1Ak/V1Bk, V2Ak/V2Bk, V3Ak/V3Bk.

It should be noted that the three selected pairs of output voltages have a waveform of Vin, which all intersect in a linear zone of these waveforms, so that in the next stage these signals can be used to generate further well-defined interpolation voltages.

The CISk circuit also provides information (basically two bits) about the selected voltage range for rank k, and this information is transmitted to the decoder DEC.

In rank 0 there is no other circuit than amplifiers A1, A2, A3. The rank 1 circuit therefore receives directly the output signals of amplifiers A1, A2, A3. The last interpolation circuit of rank n can, by means of a comparator CMPn, provide a bit of information on the position of Vin with respect to the average reference voltage of the group of main reference voltages of rank n. This information is obtained by comparing the output signals V2An and V2Bn of the rank n circuit CISn. It is transmitted to the decoder which uses it to form the digital value B0, B1, B2, ..., Bn of Vin required.

Since the converter consists of a cascade of interpolation circuits, the range selection logic must be operated sequentially from one stage to the next, whereby the formation of a range of rank k only makes sense if the range of rank k-1 has been selected beforehand. The converter therefore operates under the control of a sequential circuit and the clock signals applied to the stages of rank k are delayed by a short period of time, for example by means of a delay circuit Rk, with respect to the clock signals applied to the previous stage. These delay circuits R₁, R₂, ..., Rn are shown in Fig. 1.

Fig. 5 is an explanatory diagram showing pictorially the concept of successive voltage ranges which are successively halved, wherein a range of rank k is decomposed into three ranges of rank k+1 which overlap, and from among them a range of rank k+1 which best frames the voltage Vin is selected.

Fig. 5 shows symbolically the principle of selecting ever smaller areas around the value Vin, on which the construction of the cascade structure according to Fig. 1 is based.

Vin is initially in the range of voltages VRB, VRM, VRA, which are plotted vertically in Fig. 5. If Vin is not in this range, this is indicated by the comparator CMPX or the comparator CMPY.

The range VRB, VRM, VRA is the range of rank zero and consists of two half-intervals of rank zero, namely VRB/VRM and VRM/VRA.

The use of the three pairs of signals from the amplifiers A1, A2, A3 makes it possible, as explained above, to define five fictitious reference voltages in the CIS1 circuit of rank 1 (three main reference voltages VRB, VRM and VRA and two intermediate reference voltages V'RB and V'RA, which are in the middle of the half intervals VRB/VRM and VRM/VRA.

These five reference voltages define three rank 1 voltage ranges, each with an amplitude equal to half of the rank zero ranges, which overlap each other and form two rank 1 half-intervals, the amplitude of which corresponds to half of the rank zero half-intervals.

These voltage ranges overlap, and the voltage Vin may lie within one or two of these ranges. However, it is closely bounded by only one of these ranges (namely, the one whose center is closer to the voltage Vin).

One task of the interpolation and selection circuit, or more precisely one task of the associated decision circuit, is to select this range which best frames Vin. In Fig. 5, this is the range VRM/VRA, whose intermediate reference voltage is V'RA.

This range is the selected range of rank 1 and, to standardize the designation, the three fictitious main reference voltages of rank 1 that this range defines for the interpolation circuit of the subsequent rank 2 can be named VRB₁, VRM₁, VRA₁.

These three main rank 1 reference voltages are theoretically VRM, V'RA and VRA, but due to the linearity errors, the fictitious reference voltages defined by the interpolation circuit may not exactly equal the rank 0 reference voltages. Therefore, the rank 1 reference voltages were designated VRB₁, VRM₁, VRA₁.

This selection of three ranges corresponds in practice, within the interpolation and selection circuit of rank 1, i.e. CIS1, to the selection of three pairs of signals among five pairs formed in this circuit, these three selected pairs forming the output of the circuit CIS1 and being fed to the input of the circuit CIS2 be created.

Similarly, starting from the three pairs of signals applied to the rank 2 circuit CIS2, it is possible to form five pairs of signals and to select three pairs of rank 2 output signals, V1A₂, VIB₂; V2A₂, V2B₂; V3A₂, V3B₂, corresponding to a rank 2 voltage range of an amplitude half that of the rank 1 range and divided into two half-intervals designated by the reference voltages VRB₂, VRM₂ and VRA₂, the selected range being the one closest to the value of Vin.

Step by step, you then select further areas that frame Vin more and more closely.

The choice of the most suitable range for rank k is made by the selection circuit CDk associated with the interpolation cell CIk of rank k. This decision circuit makes the decision depending on the value of the voltages applied to the input of the circuit of rank k.

The overlap of the ranges makes it possible to limit the accuracy required for the decision circuits. This accuracy does not have to be as high as the conversion accuracy of the converter.

Fig. 6 shows five pairs of signals formed in the interpolation circuit CIS1, of which three (marked with solid lines) are selected because they define a range of rank 1 that best frames Vin, while two others (shown in dashed lines) are not used because they serve only to form the two unselected ranges.

The five signal pairs have (Vin-dependent) waveforms similar to those shown in Fig. 4.

Although the curves of Fig. 6 were shown with the same slopes at the crossing points as the curves shown in Fig. 4, it should be noted that other slopes can be present without changing the operating principle. In general, the slope of the signal curves of one stage as a function of Vin is not necessarily the same as the slope of the signal curves of the previous stage as a function of Vin. Preferably, the slope is twice as large. This point will be discussed again below.

Fig. 7 shows the schematic structure of an interpolation and selection circuit, for example the circuit CIS1 of rank 1, whereby the others can be designed in the same way.

The circuit includes five differential amplifiers AD1, AD2, AD3, AD4 and AD5, which may be constructed in the manner of the circuit according to Fig. 2 or may be improved in terms of linearity like the circuit in Fig. 8, since linearity is an important accuracy factor in the structure according to the invention.

The amplifiers AD1, AD3 and AD5 receive on the input side the pairs of balanced signals V1A₀/V1B₀, V2A₀/V2B₀, V3A₀/V3B₀. The amplifiers AD2 and AD4 receive crossover pairs V1A₀/V2B₀ and V2A₀/V3B₀ respectively.

They generate five pairs of signals for a multiplexer MUX, which selects three of them under the control of the decision circuit CI1. The three selected signal pairs are as follows: V1A₁/V1B₁, V2A₁/V2B₁, V3A₁/V3B₁. They are applied as input signals to the next stage.

The decision circuit CI1 receives the input signals V1A₀, V1B₀, V2A₀, V2B₀, V3A₀, V3B₀ (or only certain of these signals, provided that they form symmetrical pairs). It generates logic signals H1₁, H2₁, H3₁ and their complement, if necessary. These signals control the multiplexer MUX: the signal H1₁ is at a high logic level when the lower voltage range is selected; the signal H2₁ is at a high level when the middle range is selected. is selected, and the signal H3₁ is at high level when the upper range is selected.

The signals formed by the circuit CD1, more precisely the signals H2₁ and H3₁, also form binary logical information which is supplied to the decoder DEC of Fig. 1 to form the digital value of Vin.

Similarly, a circuit CISk of rank k generates output signals H1k, H2k and H3k, of which the signals H2k and H3k are transmitted to the decoder.

Fig. 8 shows a possible structure of the amplifiers AD1 to AD5 or the amplifiers A1, A2, A3, where cascode transistors (the base electrodes are connected to a common fixed potential) are inserted into the main differential branches and two additional differential branches crossed with respect to the main branches are added at the output. Such amplifiers are known for their good linearity in a wide input voltage range.

Fig. 9 shows a practical embodiment of the interpolation cell CI1 with its five differential amplifiers and its multiplexing circuits. In this example, the actual differential amplifier is that of Fig. 2, but the load resistors connected to the collectors of the transistors are separated from the collectors, i.e. the multiplexing circuits are inserted between the transistors and the load resistors.

This gives five pairs of transistors with only three pairs of load resistors. The job of the multiplexer is to connect the three pairs of load resistors to three selected ones of the five pairs of transistors. The collectors of the other transistors are then connected to the supply voltage Vcc.

The structure of Fig. 9 must of course be modified if amplifiers according to Fig. 8 are used. The cascode transistors and the additional differential pairs are then connected to the three pairs of load resistors at the output of the multiplexer.

The gain of the differential amplifiers in the interpolation circuits preferably has a value of 2 (gain of the differential output voltage with respect to the differential input voltage). To explain this choice, reference is again made to Figs. 4 and 6.

In Fig. 6 one can see the signals generated by the five differential amplifiers of the interpolation circuit CIS1. These signals have been represented with the same slope (depending on Vin) as the input signals V1A₀, V1B₀, etc. of this stage, as can be seen in Fig. 4. This would correspond to the case where the differential amplifiers of the circuit CIS1 have a unity gain.

In this case, it is easy to see that the voltage levels at the crossing point of the voltage curves from one stage to the next are not constant: for example, the adjacent crossover pairs at the output of the amplifiers A1, A2, A3 cross for a voltage Vm0. The adjacent crossover pairs at the output of the circuit CIS1 cross for a voltage Vm1 such that Vm1-Vm is half as large as Vm0-Vm. The adjacent crossover pairs at the output of the following stage CIS2 cross for a voltage Vm2 such that (Vm2-Vm) is half as large as (Vm1-Vm), and so on.

The transistors of the amplifiers of the different stages do not operate under the same conditions.

It is therefore advantageous to increase the slope of the curves as a function of Vin from one stage to the next in order to keep the level at the crossing point at the same value Vm0 each time. This can be easily achieved by providing a gain of about 2 for the differential amplifiers of the various interpolation circuits.

The decision circuit CI1 is shown in detail in Fig. 10. It generates logic signals H1₁, H2₁ and H3₁ based on analog additions between certain of the Input signals V1A₀, V1B₀, V2A₀, V2B₀, V3A₀, V3B₀. These signals depend on Vin and their sums depend on Vin (except the sum of the signals of a common pair).

To explain the principle of the decision circuit, we first refer to Fig. 11. In order to find the best of the three voltage ranges to be selected (the one that best frames Vin) when the reference voltages are VRB, V'RB, VRM, V'RA and VRA, we must determine the position of Vin with respect to the voltages VD1 and VD2, which are in the middle of the half-interval V'RB/VRM and VRM/V'RA, respectively.

In fact, if Vin is less than VD1, the lower range VRB/VRM must be selected, since Vin is closer to the middle of this range than to the middle of the other ranges. If Vin is between VD1 and VD2, the central range V'RB/V'RA must be selected, since Vin is closer to the middle of this range than to the middle of the other ranges. Finally, if Vin is greater than VD2, the upper range VRM/VRA must be selected.

To compare Vin with VD1 and VD2 when one does not have VD1 and VD2 directly but only the input signals of the CIS1 circuit, one can combine some of these input signals in differential amplifiers which act as algebraic summing elements.

Thus, the circuit which performs the comparison of Vin with VD1 (upper part of Fig. 10) consists of a double pair of cross-differential branches using two common load resistors. The four transistors of this double pair receive as input voltages the voltages V1A₀ and V2A₀ (the transistors Q1 and Q2 are connected to one of the load resistors) and the voltage V2B₀ (the transistors Q3 and Q4 are connected to the other load resistor). The two outputs of this double differential pair are fed to a comparator COMP1 which converts the logic signal H1₁ and its logic complement The double differential pair produces a signal whose variation with Vin is monotonically increasing negatively when (V2B₀-V2A₀) + (V2B₀-V1A₀) is negative, and positive when (V2B₀-V2A₀) + (V2B₀-V1A₀) is positive.

Looking at the curves in Fig. 4, it is easy to see that the above algebraic sum becomes zero when Vin passes through the center VD1 of the interval V'RB/VRM. The comparator COMP1 therefore tips over when Vin becomes larger than VD1.

Similarly, H3₁ is formed by a similar circuit which receives V2A₀, V2B₀ and V3B₀ and provides at the output of a comparator COMP2 the signal H3₁ and its complement, which flips when Vin becomes greater than VD2. Finally, a logic adder generates the signal H2₁, which is the complement of the sum H1₁ + H3₁ and indicates whether or not Vin is between VD1 and VD2.

Finally, as shown in Fig. 11, the signal H1₁ is at a level of 1 corresponding to the choice of the lower range (VRB/VRM) when Vin is less than VD1 and at a level of 0 when Vin is greater than VD1. The logic signal H2₁ is at a level of 1 corresponding to the choice of the central range V'RD/V'RA when Vin is between VD1 and VD2 and at a level of 0 when Vin is outside this interval. Finally, the signal H3₁ is at a level of 1 corresponding to the choice of the upper range VRM/VRA when Vin is greater than VD2 and at a level of 0 in the opposite case.

The same applies to the other interpolation and selection circuits, with the signals H1k, H2k, H3k for the rank k circuit forming the three range selection options of rank k.

The range selection signals H1k, H2k, H3k are used by the decoder DEC (Fig. 1) to determine the digital value of Vin.

The meaning of this decoding is as follows:

Due to the overlap of the ranges, the value of the signals H1k, H2k, H3k does not directly determine a range of values of Vin. The information has a clear meaning when the upper range or the lower range of rank k is selected (H2k = 0), but an ambiguous one when the central range is selected (H1k = 1).

In this latter case, the choice of the range of rank k+1 resolves this ambiguity, unless the central range is also chosen here. This proceeds by evaluating the combination of the selection information for the range of rank k and the range selection information for rank k+1 to resolve the ambiguity regarding the range in which Vin is located. If the central range is selected in the last rank n, the ambiguity (which then only concerns one hit of the smallest weight of the analog/digital conversion) is resolved by comparing the output signals V2An and V2Bn of the interpolation circuit CISn of rank n (comparator COMPn in Fig. 1). This comparison shows whether Vin is closer to the lower or closer to the upper range, even if Vin is in the central range.

The principle of the decoder DEC is as follows: The bit B0 with the highest weighting during conversion has the value 1 if H3₁ has the value 1, since Vin is then greater than VD2. The bit B0 with the highest weighting has the value 0 if H3₁ and H2₁ both have the value 0 (which means that H1₁ has the value 1), since Vin is then less than VD1. However, if H3₁ has the value 0 and H2₁ has the value 1, there is an ambiguity that is only resolved when H3₂ is checked.

The bit B0 can therefore be obtained by adding H3₁ and a bit which in turn depends on H3₂ and H2₁, and it should also be noted that the addition of H3₂ and H2₁ in turn provides the bit B1 of the next smallest weight, provided there is no ambiguity (with H3₂ = 0 and H2₂ = 1).

The structure of the decoder proposed here is shown in Fig. 12 and thus contains

- an adder ADD0 for the highest weighting, which receives H3₁ and the carry C1 of an adder ADD1 of the next lowest weighting and delivers B0;

- an adder ADD1 which receives H2₁ from the decision circuit CD2 and H3₂ from the decision circuit CD2 as well as the carry C2 of a subsequent adder ADD2 and supplies the bit H1 for the conversion and the carry C1 ;

- and further adders ADDk, each receiving H₂k and H3k+1 as well as the carry Ck+1 of the next adder and supplying the conversion bit Bk as well as a carry Ck;

- and for the last level of rank n, an adder ADDn which receives H2n and a final ambiguity resolution bit coming from the output of the comparator CMPn, while the adder supplies the conversion bit Bn and a carry for the previous level.

The final ambiguity removal for the bit with the least weight is done using the level of Vin with respect to the mean main reference voltage formed by the last interpolation circuit CISn. This comparison is provided by the comparator CMPn which receives the signals V2An and V2Bn.

Thus, the circuit according to Fig. 1 has been fully described in a preferred embodiment. It should be noted that variants of the embodiment can be provided without departing from the scope of the invention and these variants will now be described.

First of all, it should be noted that the entire circuit can be implemented using MOS technology, i.e. using only field-effect transistors with an insulated gate electrode instead of bipolar transistors. The production of linear differential amplifiers using MOS technology is known.

Then the analogue/digital converter can contain only two or three stages of interpolation circuits as described above. The bits of the lowest weight of the conversion can in fact be obtained by cascade-type interpolation circuits according to the state of the art or by other means. Likewise, the bits of the highest weight (higher than B0) can be obtained by means of fast coarse converters as already mentioned.

In addition, the interpolation and selection circuits described in detail in the preferred embodiment contain five differential amplifiers and use a multiplexer to select three of the five signal pairs. However, to reduce the number of cascade stages, one could increase the complexity of these stages somewhat and provide one or more of the interpolation and selection circuits with a larger number of differential amplifiers capable of selecting three signal pairs from 2P+1 signal pairs.

In practice, p can have the value 3 (in the case described above, however, p = 2). This means that with three pairs of input signals, nine pairs of signals are generated, each corresponding to a fictitious reference voltage, and three adjacent reference voltages are selected, defining an interval that best frames Vin. These three reference voltages allow three pairs of output signals to be defined, which are used as inputs to the next stage.

Fig. 13 shows the general structure of an interpolation and selection circuit operating with p = 3.

This circuit contains two consecutive amplification stages and a single multiplexer MUX at the output of the second stage to select three pairs from the nine pairs. The first stage contains five amplifiers AD1 to AD5 corresponding to those in Fig. 7. These amplifiers receive the three uncrossed pairs and two crossover pairs of input signals, as explained with reference to Fig. 7. The second stage comprises nine amplifiers AD6 to AD14 and receives the five uncrossed pairs from the first stage and four crossover pairs also from the first stage. The gains of the amplifiers AD1 to AD14 are preferably approximately 2. The nine amplifiers of the second stage produce pairs of symmetrical and monotonic signals defining nine fictitious reference voltages evenly distributed over an interval, the boundaries of these intervals being the main reference voltages defined by the three pairs of input signals. The decision circuit CD1 selects three of these nine reference voltages, that is to say three pairs of output signals from the nine possible pairs. These three fictitious reference voltages thus chosen, which become the main reference voltages for the next stage and whose magnitude is four times smaller than the interval between the main reference voltages defined by the input signals, are those which best frame the input voltage Vin. The decision circuit which selects these three reference voltages from the nine possible ones carries out analog subtractions and comparisons from the five pairs of input signals of the second stage, according to the principle explained with reference to Figs. 10 and 11, to generate logic signals (three bits for seven possibilities) which document the choice made. These logic signals are directly linked to the range in which Vin is located and can be decoded to provide an indication of the digital value of Vin. The scheme of Fig. 13 reduces the number of cascade stages, since a voltage range of rank k has an amplitude four times smaller than a voltage range of rank k-1, but of course this comes at the expense of increasing the complexity of each stage.

Claims (10)

1. Analogue/digital converter having an input for receiving an analogue voltage Vin to be converted, characterised in that it has a cascaded sequence of interpolation and selection circuits (CIS1, CIS2, ...) with at least one interpolation and selection circuit of rank k, which has: - three pairs of inputs receiving as input signals three pairs of output signals (V3a₁, V3B₁; V2A₁, V2B1; V1A₁, V1B₁) from a preceding interpolation circuit, the signals of a pair having equal values when the voltage Vin is equal to one of the three main reference voltages of rank k-1, each associated with a corresponding pair, and these three voltages together define an interval composed of two half-intervals of the voltage of rank k-1, - means for generating, from the input signals P = 2P+1, pairs of interpolation signals (p > 1; P > 3), each pair being associated with two interpolation signals which vary symmetrically and monotonically as a function of the voltage Vin, and the signals of a pair being equal when the voltage Vin is equal to a reference voltage associated with that pair, and the P reference voltages associated with the P pairs essentially forming, on the one hand, the three main reference voltages of rank k-1 and, on the other hand, P-3 intermediate reference voltages, and the P reference voltages can define 2P-1 voltage intervals whose width corresponds to a fraction 1/2P-1 of the interval of rank k-1, - Decision means for determining, depending on the levels of the three input signal pairs, which of the 2P-1 intervals is the voltage interval that best frames the input voltage Vin, this interval consisting of consists of two half-intervals bounded by three of P reference voltages, and these three voltages are called the reference voltages of rank k, - and means for selecting from the P pairs the three pairs (V3a₂, V3B₂; V2A₂, V2B₂; V1A₂, V1B₂) associated with the three reference voltages of rank k to apply them to the output of the interpolation circuit of rank k. 2. Analog/digital converter according to claim 1, characterized in that the means for forming the interpolation signals contain at least one stage of parallel differential amplifiers, each having a gain of approximately 2. 3. Analogue/digital converter according to one of claims 1 and 2, characterized in that p = 2 and P = 5 and in that the five reference voltages associated with the five pairs of interpolation signals are, on the one hand, the three main reference voltages of rank k-1 and, on the other hand, two intermediate reference voltages located in the middle of the half-intervals defined by the three main reference voltages of rank k-1, these five reference voltages defining between them three voltage intervals of a width equal to that of a half-interval of rank k-1 and the selection means selecting three pairs from the five pairs of interpolation signals so that the signals of a pair are equal when the voltage Vin is equal to one of the main reference voltages of rank k. 4. Analogue/digital converter according to claim 3, characterized in that the interpolation and selection circuit of rank 1 receives as input signals the differential outputs of three differential amplifiers (A1, A2, A3) which in turn receive at a first input the voltage Vin to be converted and at a second input each of three Receive main reference voltages (VRB, VRM, VRA) and each provide two output voltages that vary symmetrically and monotonically depending on the voltage Vin to be converted. 5. Analog/digital converter according to claim 4, characterized in that the main reference voltages are spaced apart from one another such that the curves of the output voltages of the amplifier corresponding to the central main reference voltage (VRM) cross the curves of the output voltages of the two other amplifiers in a linear zone of these output voltages. 6. Analogue/digital converter according to one of claims 3 to 5, characterized in that the interpolation and selection circuit of rank k comprises five differential amplifiers, a decision circuit and a selection circuit, the latter being controlled by the decision circuit to direct the output signals of three differential amplifiers selected from the five amplifiers present to the outputs of the circuit. 7. Analog/digital converter according to one of claims 3 to 6, characterized in that the three selected pairs of output voltages have curves dependent on Vin which intersect in a linear zone of these curves. 8. Analog/digital converter according to one of claims 3 to 7, characterized in that it contains a decoding circuit which receives logic signals from the decision means of the interpolation and selection circuits and supplies digital bits representing a digital value of Vin. 9. Analog/digital converter according to claim 8, characterized characterized in that the decoding circuit includes at least one adder of rank k which supplies a bit of the result of the conversion for rank k and receives at the input a bit of a logic decision signal from an interpolation circuit of rank k, a further bit of a logic decision signal from an interpolation circuit of rank k+1 and an addition carry from an adder of rank k+1. 10. Method for analog/digital conversion of an input voltage Vin, which uses several interpolation circuits (CIS1, CIS2, ...) in cascade, characterized in that - three pairs of analog signals are applied to the input of an interpolation circuit of rank k, coming from three pairs of outputs (V3a₁/V3B₁, V2A₁/V2B₁, V1A₁/V1B₁) of a preceding interpolation circuit of rank k-1, the signals of a pair having equal values when the voltage Vin is equal to one of the three main reference voltages of rank k-1 associated with each pair, and these three voltages define between them a voltage interval composed of two half-intervals of rank k-1, - from these three pairs of signals P = 2P+1, pairs of interpolation signals (p > 1, P > 3) are generated, each pair comprising two interpolation signals varying symmetrically and monotonically as a function of the voltage Vin, the signals of a pair being equal when the voltage Vin is equal to a reference voltage associated with this pair, and the P reference voltages associated with the P pairs essentially corresponding, on the one hand, to the three main reference voltages of rank k-1 and, on the other hand, to at least two intermediate voltages located in the middle of the half-intervals defined by the three main reference voltages of rank k-1, these P reference voltages corresponding to 2P-1 voltage intervals whose width is equal to a fraction 1/2P-1 of the interval of rank k-1, - depending on the levels of the three pairs of input signals, it is determined which of the 2P-1 intervals is the voltage interval that best frames the input voltage Vin, this interval being made up of two half-intervals delimited by three of the P reference voltages, which are called main reference voltages of rank k, - from the P pairs, the three pairs (V3a₂/V3B₂, V2A₂/V2B₂, V1A₂/V1B₂) associated with the three reference voltages of rank k are selected and these three pairs are applied to the output of the interpolation circuit of rank k.