DE69636861D1 - Mikroprozessor mit Lade-/Speicheroperation zu/von mehreren Registern - Google Patents

Mikroprozessor mit Lade-/Speicheroperation zu/von mehreren Registern

Info

Publication number
DE69636861D1
DE69636861D1 DE69636861T DE69636861T DE69636861D1 DE 69636861 D1 DE69636861 D1 DE 69636861D1 DE 69636861 T DE69636861 T DE 69636861T DE 69636861 T DE69636861 T DE 69636861T DE 69636861 D1 DE69636861 D1 DE 69636861D1
Authority
DE
Germany
Prior art keywords
microprocessor
load
store operation
multiple registers
registers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69636861T
Other languages
English (en)
Other versions
DE69636861T2 (de
Inventor
James A Kahle
Albert J Loper
Soummya Mallick
Aubrey D Ogden
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE69636861D1 publication Critical patent/DE69636861D1/de
Application granted granted Critical
Publication of DE69636861T2 publication Critical patent/DE69636861T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3834—Maintaining memory consistency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Memory System (AREA)
DE69636861T 1995-09-11 1996-08-29 Mikroprozessor mit Lade-/Speicheroperation zu/von mehreren Registern Expired - Lifetime DE69636861T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/526,343 US5694565A (en) 1995-09-11 1995-09-11 Method and device for early deallocation of resources during load/store multiple operations to allow simultaneous dispatch/execution of subsequent instructions
US526343 1995-09-11

Publications (2)

Publication Number Publication Date
DE69636861D1 true DE69636861D1 (de) 2007-03-15
DE69636861T2 DE69636861T2 (de) 2007-07-05

Family

ID=24096948

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69636861T Expired - Lifetime DE69636861T2 (de) 1995-09-11 1996-08-29 Mikroprozessor mit Lade-/Speicheroperation zu/von mehreren Registern

Country Status (5)

Country Link
US (2) US5694565A (de)
EP (1) EP0762270B1 (de)
JP (1) JP3096427B2 (de)
KR (1) KR100234646B1 (de)
DE (1) DE69636861T2 (de)

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH096614A (ja) * 1995-06-21 1997-01-10 Sanyo Electric Co Ltd データ処理装置
US6006320A (en) * 1996-07-01 1999-12-21 Sun Microsystems, Inc. Processor architecture with independent OS resources
US5859999A (en) * 1996-10-03 1999-01-12 Idea Corporation System for restoring predicate registers via a mask having at least a single bit corresponding to a plurality of registers
US5913054A (en) * 1996-12-16 1999-06-15 International Business Machines Corporation Method and system for processing a multiple-register instruction that permit multiple data words to be written in a single processor cycle
US6006325A (en) * 1996-12-19 1999-12-21 Institute For The Development Of Emerging Architectures, L.L.C. Method and apparatus for instruction and data serialization in a computer processor
US7272703B2 (en) * 1997-08-01 2007-09-18 Micron Technology, Inc. Program controlled embedded-DRAM-DSP architecture and methods
US6039765A (en) * 1997-12-15 2000-03-21 Motorola, Inc. Computer instruction which generates multiple results of different data types to improve software emulation
US6035394A (en) * 1998-02-17 2000-03-07 International Business Machines Corporation System for providing high performance speculative processing of complex load/store instructions by generating primitive instructions in the load/store unit and sequencer in parallel
US6202130B1 (en) 1998-04-17 2001-03-13 Motorola, Inc. Data processing system for processing vector data and method therefor
US20080184017A1 (en) * 1999-04-09 2008-07-31 Dave Stuttard Parallel data processing apparatus
GB0023697D0 (en) * 2000-09-27 2000-11-08 Univ Bristol Register assignment in a processor
US6789187B2 (en) * 2000-12-15 2004-09-07 Intel Corporation Processor reset and instruction fetches
JP2004151915A (ja) * 2002-10-30 2004-05-27 Renesas Technology Corp データ処理装置
GB2402759B (en) * 2003-06-12 2005-12-21 Advanced Risc Mach Ltd Data processing apparatus and method for transferring data values between a register file and a memory
CA2434257A1 (en) * 2003-07-03 2005-01-03 Ibm Canada Limited - Ibm Canada Limitee Pairing of spills for parallel registers
WO2007069000A1 (en) * 2005-12-16 2007-06-21 Freescale Semiconductor, Inc. Device and method for processing instructions
US8261046B2 (en) 2006-10-27 2012-09-04 Intel Corporation Access of register files of other threads using synchronization
US7600099B2 (en) * 2007-03-08 2009-10-06 International Business Machines Corporation System and method for predictive early allocation of stores in a microprocessor
US7913067B2 (en) * 2008-02-20 2011-03-22 International Business Machines Corporation Method and system for overlapping execution of instructions through non-uniform execution pipelines in an in-order processor
US7987343B2 (en) * 2008-03-19 2011-07-26 International Business Machines Corporation Processor and method for synchronous load multiple fetching sequence and pipeline stage result tracking to facilitate early address generation interlock bypass
US9104399B2 (en) * 2009-12-23 2015-08-11 International Business Machines Corporation Dual issuing of complex instruction set instructions
US8082467B2 (en) * 2009-12-23 2011-12-20 International Business Machines Corporation Triggering workaround capabilities based on events active in a processor pipeline
US9135005B2 (en) * 2010-01-28 2015-09-15 International Business Machines Corporation History and alignment based cracking for store multiple instructions for optimizing operand store compare penalties
US8495341B2 (en) * 2010-02-17 2013-07-23 International Business Machines Corporation Instruction length based cracking for instruction of variable length storage operands
US8938605B2 (en) * 2010-03-05 2015-01-20 International Business Machines Corporation Instruction cracking based on machine state
US8464030B2 (en) 2010-04-09 2013-06-11 International Business Machines Corporation Instruction cracking and issue shortening based on instruction base fields, index fields, operand fields, and various other instruction text bits
US8645669B2 (en) 2010-05-05 2014-02-04 International Business Machines Corporation Cracking destructively overlapping operands in variable length instructions
US9201656B2 (en) * 2011-12-02 2015-12-01 Arm Limited Data processing apparatus and method for performing register renaming for certain data processing operations without additional registers
US8914616B2 (en) 2011-12-02 2014-12-16 Arm Limited Exchanging physical to logical register mapping for obfuscation purpose when instruction of no operational impact is executed
US20130173886A1 (en) * 2012-01-04 2013-07-04 Qualcomm Incorporated Processor with Hazard Tracking Employing Register Range Compares
FR3083351B1 (fr) * 2018-06-29 2021-01-01 Vsora Architecture de processeur asynchrone

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4493020A (en) * 1980-05-06 1985-01-08 Burroughs Corporation Microprogrammed digital data processor employing microinstruction tasking and dynamic register allocation
US4903196A (en) * 1986-05-02 1990-02-20 International Business Machines Corporation Method and apparatus for guaranteeing the logical integrity of data in the general purpose registers of a complex multi-execution unit uniprocessor
GB8817911D0 (en) * 1988-07-27 1988-09-01 Int Computers Ltd Data processing apparatus
US5471593A (en) * 1989-12-11 1995-11-28 Branigin; Michael H. Computer processor with an efficient means of executing many instructions simultaneously
US5241636A (en) * 1990-02-14 1993-08-31 Intel Corporation Method for parallel instruction execution in a computer
JPH0455986A (ja) * 1990-06-26 1992-02-24 Toshiba Corp 画像処理装置
JP2556182B2 (ja) * 1990-08-29 1996-11-20 三菱電機株式会社 デ−タ処理装置
US5355457A (en) * 1991-05-21 1994-10-11 Motorola, Inc. Data processor for performing simultaneous instruction retirement and backtracking
US5539911A (en) * 1991-07-08 1996-07-23 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
DE69329778T2 (de) * 1992-09-29 2001-04-26 Seiko Epson Corp., Tokio/Tokyo System und verfahren zur handhabung von laden und/oder speichern in einem superskalar mikroprozessor
US5416911A (en) * 1993-02-02 1995-05-16 International Business Machines Corporation Performance enhancement for load multiple register instruction
US5878245A (en) * 1993-10-29 1999-03-02 Advanced Micro Devices, Inc. High performance load/store functional unit and data cache
EP0651321B1 (de) * 1993-10-29 2001-11-14 Advanced Micro Devices, Inc. Superskalarmikroprozessoren
US5559976A (en) * 1994-03-31 1996-09-24 International Business Machines Corporation System for instruction completion independent of result write-back responsive to both exception free completion of execution and completion of all logically prior instructions
EP0686912B1 (de) * 1994-06-03 1998-12-16 Motorola, Inc. Datenprozessor mit einer Ausführungseinheit zur Durchführung von Ladebefehlen und Verfahren zu seinem Betrieb

Also Published As

Publication number Publication date
KR970016945A (ko) 1997-04-28
JPH09146770A (ja) 1997-06-06
EP0762270A3 (de) 2004-07-28
US5694565A (en) 1997-12-02
KR100234646B1 (ko) 1999-12-15
EP0762270A2 (de) 1997-03-12
JP3096427B2 (ja) 2000-10-10
DE69636861T2 (de) 2007-07-05
EP0762270B1 (de) 2007-01-24
US5867684A (en) 1999-02-02

Similar Documents

Publication Publication Date Title
DE69636861D1 (de) Mikroprozessor mit Lade-/Speicheroperation zu/von mehreren Registern
DE69525294D1 (de) Registerdatei mit Multi-tasking Unterstützung
DE69418596D1 (de) Erfassung von verfälschten objekten
DE69423408D1 (de) Selbstbedienungssystem mit Vorhersagefähigkeit
DK0635102T3 (da) Belastningsindikerende fastgørelseselement
DE69427564D1 (de) Optimierender Kompilierer
FR2705804B1 (fr) Architecture de processeur multi-tâches.
DE69401376D1 (de) Wirbelhaken
NO923000D0 (no) Stridsammunisjon, saerlig i teleskopisk utfoerelse
DE69706648D1 (de) Verbinden von rohren zu gegenständen
DE69429492D1 (de) Mikroprozessor mit Registerbankarchitektur
DE59400720D1 (de) Spulengatter
DE59403006D1 (de) Kleinladungsträger
KR950006483U (ko) 조립식 빨래 건조대
KR950002748U (ko) 개고리
KR950017313U (ko) 직물지
KR950001338U (ko) 천정부착식 빨래건조대
KR950006430U (ko) 빨래판
KR950011688U (ko) 세제투입반
KR950002894U (ko) 전시용 접착 걸이구
KR950014349U (ko) 입식 빨래대
KR960037294U (ko) 적재가 용이한 랙장치
NO931436D0 (no) Krok
KR950005293U (ko) 통발끈 고정용 걸고리
KR950000202U (ko) 개고리

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)