DE69625474D1 - Verfahren und vorrichtung zur erzeugung von pseudozufallsbefehlen für entwurfsprüfung - Google Patents

Verfahren und vorrichtung zur erzeugung von pseudozufallsbefehlen für entwurfsprüfung

Info

Publication number
DE69625474D1
DE69625474D1 DE69625474T DE69625474T DE69625474D1 DE 69625474 D1 DE69625474 D1 DE 69625474D1 DE 69625474 T DE69625474 T DE 69625474T DE 69625474 T DE69625474 T DE 69625474T DE 69625474 D1 DE69625474 D1 DE 69625474D1
Authority
DE
Germany
Prior art keywords
pseudo random
design verification
generating pseudo
random commands
commands
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69625474T
Other languages
English (en)
Inventor
D Whitman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sun Microsystems Inc
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Application granted granted Critical
Publication of DE69625474D1 publication Critical patent/DE69625474D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/273—Tester hardware, i.e. output processing circuits
    • G06F11/2736—Tester hardware, i.e. output processing circuits using a dedicated service processor for test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318307—Generation of test inputs, e.g. test vectors, patterns or sequences computer-aided, e.g. automatic test program generator [ATPG], program translations, test program debugging
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318385—Random or pseudo-random test pattern
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318392—Generation of test inputs, e.g. test vectors, patterns or sequences for sequential circuits
DE69625474T 1995-03-28 1996-03-27 Verfahren und vorrichtung zur erzeugung von pseudozufallsbefehlen für entwurfsprüfung Expired - Lifetime DE69625474D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/412,157 US5572666A (en) 1995-03-28 1995-03-28 System and method for generating pseudo-random instructions for design verification
PCT/US1996/004264 WO1996030834A1 (en) 1995-03-28 1996-03-27 System and method for generating pseudo-random instructions for design verification

Publications (1)

Publication Number Publication Date
DE69625474D1 true DE69625474D1 (de) 2003-01-30

Family

ID=23631830

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69625474T Expired - Lifetime DE69625474D1 (de) 1995-03-28 1996-03-27 Verfahren und vorrichtung zur erzeugung von pseudozufallsbefehlen für entwurfsprüfung

Country Status (5)

Country Link
US (1) US5572666A (de)
EP (1) EP0818002B1 (de)
JP (1) JP3936737B2 (de)
DE (1) DE69625474D1 (de)
WO (1) WO1996030834A1 (de)

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US5774726A (en) * 1995-04-24 1998-06-30 Sun Microsystems, Inc. System for controlled generation of assembly language instructions using assembly language data types including instruction types in a computer language as input to compiler
US5956478A (en) * 1995-09-11 1999-09-21 Digital Equipment Corporation Method for generating random test cases without causing infinite loops
US6044377A (en) * 1995-11-07 2000-03-28 Sun Microsystem, Inc. User-defined object type and method of making the object type wherein a file associated with a rule is invoked by accessing the file which generates code at run time
US5859962A (en) * 1995-12-21 1999-01-12 Ncr Corporation Automated verification of digital design
US6002876A (en) * 1996-09-27 1999-12-14 Texas Instruments Incorporated Maintaining code consistency among plural instruction sets via function naming convention
US6178533B1 (en) 1997-06-30 2001-01-23 Sun Microsystems, Inc. Method and system for design verification
US6397353B1 (en) * 1998-04-17 2002-05-28 Allied Signal Inc. Method and apparatus for protecting sensitive data during automatic testing of hardware
US6249891B1 (en) * 1998-07-02 2001-06-19 Advantest Corp. High speed test pattern evaluation apparatus
US6253344B1 (en) * 1998-10-29 2001-06-26 Hewlett Packard Company System and method for testing a microprocessor with an onboard test vector generator
US6212493B1 (en) * 1998-12-01 2001-04-03 Compaq Computer Corporation Profile directed simulation used to target time-critical crossproducts during random vector testing
US6233675B1 (en) * 1999-03-25 2001-05-15 Rise Technology Company Facility to allow fast execution of and, or, and test instructions
US6606721B1 (en) * 1999-11-12 2003-08-12 Obsidian Software Method and apparatus that tracks processor resources in a dynamic pseudo-random test program generator
US6643800B1 (en) * 2000-02-02 2003-11-04 Hewlett-Packard Development Company, L.P. Method and apparatus for testing microarchitectural features by using tests written in microcode
US6925405B2 (en) * 2002-01-09 2005-08-02 International Business Machines Corporation Adaptive test program generation
US7028067B2 (en) * 2002-02-20 2006-04-11 International Business Machines Corporation Generation of mask-constrained floating-point addition and subtraction test cases, and method and system therefor
TWI278778B (en) * 2002-05-06 2007-04-11 Nextest Systems Corp Apparatus for testing semiconductor devices and method for use therewith
KR100896274B1 (ko) * 2002-07-10 2009-05-07 엘지전자 주식회사 의사 랜덤 코드 생성 장치
US6918098B2 (en) * 2002-07-16 2005-07-12 Hewlett-Packard Development Company, L.P. Random code generation using genetic algorithms
US20040093536A1 (en) * 2002-11-12 2004-05-13 Weller Christopher Todd System and method for providing coherency during the evaluation of a multiprocessor system
US7398515B2 (en) * 2003-07-16 2008-07-08 International Business Machines Corporation Buckets of commands in a multiprocessor-based verification environment
CA2452274A1 (en) * 2003-12-03 2005-06-03 Robert F. Enenkel System and method of testing and evaluating mathematical functions
US20060115645A1 (en) * 2004-11-29 2006-06-01 A Major Corporation Punch pad
US7254509B1 (en) 2004-12-01 2007-08-07 Advanced Micro Devices, Inc. Method and system for testing a memory of a microprocessor
US7404110B1 (en) 2004-12-01 2008-07-22 Advanced Micro Devices, Inc. Method and system for self-assembling instruction opcodes for a custom random functional test of a microprocessor
US7356436B2 (en) * 2005-02-02 2008-04-08 International Business Machines Corporation Method, system, and storage medium for estimating and improving test case generation
US20080189528A1 (en) * 2007-02-02 2008-08-07 Mips Technologies, Inc. System, Method and Software Application for the Generation of Verification Programs
US7979238B2 (en) * 2007-08-24 2011-07-12 International Business Machines Corporation System, method and computer program product for evaluating a test of an alternative system
US20090307468A1 (en) * 2008-06-06 2009-12-10 International Business Machines Corporation Generating a Test Case Micro Generator During Processor Design Verification and Validation
KR102025694B1 (ko) 2012-09-07 2019-09-27 삼성전자 주식회사 재구성 가능한 프로세서의 검증 방법
US10901878B2 (en) 2018-12-19 2021-01-26 International Business Machines Corporation Reduction of pseudo-random test case generation overhead
US11204859B2 (en) * 2019-07-09 2021-12-21 International Business Machines Corporation Partial-results post-silicon hardware exerciser

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4339819A (en) * 1980-06-17 1982-07-13 Zehntel, Inc. Programmable sequence generator for in-circuit digital testing
US4500993A (en) * 1980-06-17 1985-02-19 Zehntel, Inc. In-circuit digital tester for testing microprocessor boards
US4493078A (en) * 1982-09-29 1985-01-08 Siemens Corporation Method and apparatus for testing a digital computer
DE3418360A1 (de) * 1984-05-17 1985-11-21 Siemens AG, 1000 Berlin und 8000 München Anordnung fuer die zugriffsmoeglichkeit zu einzelnen programmabschnitten eines programmspeichers
US4931722A (en) * 1985-11-07 1990-06-05 Control Data Corporation Flexible imbedded test system for VLSI circuits
FR2592957B1 (fr) * 1986-01-10 1988-04-08 Trt Telecom Radio Electr Dispositif de test de circuit logique combinatoire et circuit integre comportant un tel dispositif.
DE3921628A1 (de) * 1989-06-30 1991-01-10 Siemens Ag Verfahren zur erzeugung von assemblern und/oder disassemblern fuer die beschreibung des maschinenbefehlssatzes eines mikroprozessorbausteins
IL94115A (en) * 1990-04-18 1996-06-18 Ibm Israel Dynamic process for creating pseudo-random test templates for pompous hardware design violence
US5455938A (en) * 1994-09-14 1995-10-03 Ahmed; Sultan Network based machine instruction generator for design verification

Also Published As

Publication number Publication date
EP0818002B1 (de) 2002-12-18
WO1996030834A1 (en) 1996-10-03
US5572666A (en) 1996-11-05
EP0818002A1 (de) 1998-01-14
JPH11508710A (ja) 1999-07-27
JP3936737B2 (ja) 2007-06-27

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Legal Events

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8332 No legal effect for de