DE69618386D1 - Damaszener-Doppelprozess mit Löchern mit abgeschrägten Flauben - Google Patents

Damaszener-Doppelprozess mit Löchern mit abgeschrägten Flauben

Info

Publication number
DE69618386D1
DE69618386D1 DE69618386T DE69618386T DE69618386D1 DE 69618386 D1 DE69618386 D1 DE 69618386D1 DE 69618386 T DE69618386 T DE 69618386T DE 69618386 T DE69618386 T DE 69618386T DE 69618386 D1 DE69618386 D1 DE 69618386D1
Authority
DE
Germany
Prior art keywords
damascus
chamfered
leaves
holes
double process
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69618386T
Other languages
English (en)
Other versions
DE69618386T2 (de
Inventor
Thomas John Licata
Ronald Wayne Nunes
Motoya Okazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
International Business Machines Corp
Original Assignee
Toshiba Corp
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, International Business Machines Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE69618386D1 publication Critical patent/DE69618386D1/de
Publication of DE69618386T2 publication Critical patent/DE69618386T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)
DE69618386T 1995-06-05 1996-05-07 Damaszener-Doppelprozess mit Löchern mit abgeschrägten Flauben Expired - Fee Related DE69618386T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/461,813 US5874201A (en) 1995-06-05 1995-06-05 Dual damascene process having tapered vias

Publications (2)

Publication Number Publication Date
DE69618386D1 true DE69618386D1 (de) 2002-02-14
DE69618386T2 DE69618386T2 (de) 2002-09-26

Family

ID=23834023

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69618386T Expired - Fee Related DE69618386T2 (de) 1995-06-05 1996-05-07 Damaszener-Doppelprozess mit Löchern mit abgeschrägten Flauben

Country Status (4)

Country Link
US (1) US5874201A (de)
EP (1) EP0747947B1 (de)
JP (1) JP3262496B2 (de)
DE (1) DE69618386T2 (de)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6537905B1 (en) 1996-12-30 2003-03-25 Applied Materials, Inc. Fully planarized dual damascene metallization using copper line interconnect and selective CVD aluminum plug
US6677226B1 (en) * 1998-05-11 2004-01-13 Motorola, Inc. Method for forming an integrated circuit having a bonding pad and a fuse
KR100505602B1 (ko) * 1998-05-12 2005-09-26 삼성전자주식회사 반도체소자 제조에 사용되는 반사방지막 및 이를 포함한 다층막전면식각방법
TW377492B (en) * 1998-06-08 1999-12-21 United Microelectronics Corp Method of manufacturing dual damascene
JP4226699B2 (ja) * 1998-09-11 2009-02-18 株式会社ルネサステクノロジ 半導体装置の製造方法
US6211071B1 (en) * 1999-04-22 2001-04-03 Advanced Micro Devices, Inc. Optimized trench/via profile for damascene filling
DE19937994C2 (de) * 1999-08-11 2003-12-11 Infineon Technologies Ag Ätzprozeß für eine Dual Damascene Strukturierung einer Isolierschicht auf einer Halbleiterstruktur
US6107177A (en) * 1999-08-25 2000-08-22 Siemens Aktienesellschaft Silylation method for reducing critical dimension loss and resist loss
US6153935A (en) 1999-09-30 2000-11-28 International Business Machines Corporation Dual etch stop/diffusion barrier for damascene interconnects
US6319821B1 (en) 2000-04-24 2001-11-20 Taiwan Semiconductor Manufacturing Company Dual damascene approach for small geometry dimension
US6258709B1 (en) 2000-06-07 2001-07-10 Micron Technology, Inc. Formation of electrical interconnect lines by selective metal etch
DE10030444A1 (de) 2000-06-22 2002-01-10 Infineon Technologies Ag Verfahren zur Herstellung einer dielektrischen Antifuse-Struktur
US6461877B1 (en) 2000-06-30 2002-10-08 International Business Machines Corporation Variable data compensation for vias or contacts
JP4858895B2 (ja) * 2000-07-21 2012-01-18 富士通セミコンダクター株式会社 半導体装置の製造方法
US6475810B1 (en) 2000-08-10 2002-11-05 Chartered Semiconductor Manufacturing Ltd. Method of manufacturing embedded organic stop layer for dual damascene patterning
EP1311563A4 (de) 2000-08-16 2006-09-06 Brewer Science Inc Photosensitive harzzusammensetzungen für farbfilteranwendungen
US6465358B1 (en) * 2000-10-06 2002-10-15 Intel Corporation Post etch clean sequence for making a semiconductor device
KR100364812B1 (ko) * 2000-12-30 2002-12-16 주식회사 하이닉스반도체 반도체 소자의 제조방법
US8124516B2 (en) 2006-08-21 2012-02-28 Lam Research Corporation Trilayer resist organic layer etch
JP2012038965A (ja) * 2010-08-09 2012-02-23 Lapis Semiconductor Co Ltd 半導体装置及びその製造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4461672A (en) * 1982-11-18 1984-07-24 Texas Instruments, Inc. Process for etching tapered vias in silicon dioxide
JPS60261141A (ja) * 1984-06-07 1985-12-24 Rohm Co Ltd 半導体装置およびその製造方法
US4758305A (en) * 1986-03-11 1988-07-19 Texas Instruments Incorporated Contact etch method
US4902377A (en) * 1989-05-23 1990-02-20 Motorola, Inc. Sloped contact etch process
US5173442A (en) * 1990-07-23 1992-12-22 Microelectronics And Computer Technology Corporation Methods of forming channels and vias in insulating layers
US5171412A (en) * 1991-08-23 1992-12-15 Applied Materials, Inc. Material deposition method for integrated circuit manufacturing
US5308742A (en) * 1992-06-03 1994-05-03 At&T Bell Laboratories Method of etching anti-reflection coating

Also Published As

Publication number Publication date
DE69618386T2 (de) 2002-09-26
EP0747947A3 (de) 1997-04-02
JPH08330504A (ja) 1996-12-13
EP0747947B1 (de) 2002-01-09
US5874201A (en) 1999-02-23
EP0747947A2 (de) 1996-12-11
JP3262496B2 (ja) 2002-03-04

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee