DE69531460D1 - Zusätzliches tor für systemverwaltung - Google Patents
Zusätzliches tor für systemverwaltungInfo
- Publication number
- DE69531460D1 DE69531460D1 DE69531460T DE69531460T DE69531460D1 DE 69531460 D1 DE69531460 D1 DE 69531460D1 DE 69531460 T DE69531460 T DE 69531460T DE 69531460 T DE69531460 T DE 69531460T DE 69531460 D1 DE69531460 D1 DE 69531460D1
- Authority
- DE
- Germany
- Prior art keywords
- system management
- additional system
- management gate
- gate
- additional
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
- G06F1/3215—Monitoring of peripheral devices
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
- G06F13/423—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with synchronous protocol
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Power Sources (AREA)
- Multi Processors (AREA)
- Debugging And Monitoring (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/US1995/002305 WO1996026488A1 (en) | 1995-02-24 | 1995-02-24 | System management shadow port |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69531460D1 true DE69531460D1 (de) | 2003-09-11 |
DE69531460T2 DE69531460T2 (de) | 2004-06-24 |
Family
ID=22248720
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69531460T Expired - Lifetime DE69531460T2 (de) | 1995-02-24 | 1995-02-24 | Zusätzliches tor für systemverwaltung |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP0811197B1 (de) |
AU (1) | AU1930595A (de) |
DE (1) | DE69531460T2 (de) |
WO (1) | WO1996026488A1 (de) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6282570B1 (en) | 1998-12-07 | 2001-08-28 | International Business Machines Corporation | Monitoring a large parallel database through dynamic grouping and sequential sampling |
EP2391095A1 (de) * | 2010-05-31 | 2011-11-30 | Fluke Corporation | Automatisches Adressierschema für eine serielle 2-Wire-Busschnittstelle |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5150467A (en) * | 1987-09-04 | 1992-09-22 | Digital Equipment Corporation | Method and apparatus for suspending and restarting a bus cycle |
US5131082A (en) * | 1989-06-09 | 1992-07-14 | International Business Machines Corporation | Command delivery for a computing system for transfers between a host and subsystem including providing direct commands or indirect commands indicating the address of the subsystem control block |
JPH0387958A (ja) * | 1989-06-30 | 1991-04-12 | Nec Corp | バスロツク制御方式 |
US5283792A (en) * | 1990-10-19 | 1994-02-01 | Benchmarq Microelectronics, Inc. | Power up/power down controller and power fail detector for processor |
US5237692A (en) * | 1990-11-09 | 1993-08-17 | Ast Research Inc. | Internal interrupt controller for a peripheral controller |
US5410711A (en) * | 1991-02-14 | 1995-04-25 | Dell Usa, L.P. | Portable computer with BIOS-independent power management |
-
1995
- 1995-02-24 DE DE69531460T patent/DE69531460T2/de not_active Expired - Lifetime
- 1995-02-24 EP EP95911910A patent/EP0811197B1/de not_active Expired - Lifetime
- 1995-02-24 WO PCT/US1995/002305 patent/WO1996026488A1/en active IP Right Grant
- 1995-02-24 AU AU19305/95A patent/AU1930595A/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
AU1930595A (en) | 1996-09-11 |
DE69531460T2 (de) | 2004-06-24 |
EP0811197A4 (de) | 1999-11-24 |
EP0811197B1 (de) | 2003-08-06 |
WO1996026488A1 (en) | 1996-08-29 |
EP0811197A1 (de) | 1997-12-10 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |